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-rw-r--r--src/mame/drivers/nforcepc.cpp230
1 files changed, 213 insertions, 17 deletions
diff --git a/src/mame/drivers/nforcepc.cpp b/src/mame/drivers/nforcepc.cpp
index 9eeba267bc5..3bb38d17b8b 100644
--- a/src/mame/drivers/nforcepc.cpp
+++ b/src/mame/drivers/nforcepc.cpp
@@ -4,7 +4,7 @@
/*
Computer based on a motherboard utilizing the nForce chipset (also known as CRUSH11 or CRUSH12)
- Start with the following compoents:
+ Start with the following components:
- An Asus A7N266-C motherboard using:
- nForce 415-D northbridge
- nForce MCP-D southbridge (with integrated APU)
@@ -14,6 +14,7 @@
- An IDE hard disk
- A floppy disk drive
- A keyboard
+ - A ddr dimm memory module
Later add:
- A Nvidia NV25 based AGP video card
@@ -24,18 +25,29 @@
#include "cpu/i386/i386.h"
#include "machine/pci.h"
#include "machine/pci-ide.h"
+#include "includes/xbox_pci.h"
#include "includes/nforcepc.h"
+// for now let's use this as the contents of the spd chip in the ddr dimm memory module
+static const uint8_t test_spd_data[] = {
+ 0x80,0x08,0x07,0x0D,0x0A,0x01,0x40,0x00,0x04,0x75,0x75,0x00,0x82,0x10,0x00,0x01,0x0E,0x04,0x0C,0x01,0x02,0x20,0xC0,0xA0,0x75,0x00,
+ 0x00,0x50,0x3C,0x50,0x2D,0x40,0x90,0x90,0x50,0x50,0x00,0x00,0x00,0x00,0x00,0x41,0x4B,0x30,0x32,0x75,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xEA,0xAD,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x59,0x4D,0x44,0x35,
+ 0x33,0x32,0x4D,0x36,0x34,0x36,0x43,0x36,0x2D,0x48,0x20,0x20,0x20
+};
+
/*
Pci devices
*/
+// NVIDIA Corporation nForce CPU bridge
+
DEFINE_DEVICE_TYPE(CRUSH11, crush11_host_device, "crush11", "NVIDIA Corporation nForce CPU bridge")
void crush11_host_device::config_map(address_map &map)
{
pci_host_device::config_map(map);
- map(0x50, 0x50).rw(FUNC(crush11_host_device::test_r), FUNC(crush11_host_device::test_w));
+ map(0xf0, 0xf0).rw(FUNC(crush11_host_device::test_r), FUNC(crush11_host_device::test_w));
}
crush11_host_device::crush11_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
@@ -90,7 +102,7 @@ void crush11_host_device::map_extra(uint64_t memory_window_start, uint64_t memor
READ8_MEMBER(crush11_host_device::test_r)
{
- return 0;
+ return 4;
}
WRITE8_MEMBER(crush11_host_device::test_w)
@@ -99,13 +111,156 @@ WRITE8_MEMBER(crush11_host_device::test_w)
}
/*
+ Ddevices connected to SMBus
+*/
+
+// access logger
+
+DEFINE_DEVICE_TYPE(SMBUS_LOGGER, smbus_logger_device, "smbus_logger", "SMBUS LOGGER")
+
+smbus_logger_device::smbus_logger_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : device_t(mconfig, SMBUS_LOGGER, tag, owner, clock)
+{
+}
+
+int smbus_logger_device::execute_command(int command, int rw, int data)
+{
+ if (rw == 1)
+ {
+ logerror("smbus read from %02x R %02x\n", command, buffer[command]);
+ return buffer[command];
+ }
+ buffer[command] = (uint8_t)data;
+ logerror("smbus write to %02x W %02x\n", command, data);
+ return 0;
+}
+
+void smbus_logger_device::device_start()
+{
+ memset(buffer, 0, sizeof(buffer));
+}
+
+void smbus_logger_device::device_reset()
+{
+}
+
+// read-only data
+
+DEFINE_DEVICE_TYPE(SMBUS_ROM, smbus_rom_device, "smbus_rom", "SMBUS ROM")
+
+smbus_rom_device::smbus_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+ device_t(mconfig, SMBUS_ROM, tag, owner, clock)
+{
+}
+
+smbus_rom_device::smbus_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, const uint8_t *data, int size) :
+ smbus_rom_device(mconfig, tag, owner, clock)
+{
+ buffer = data;
+ buffer_size = size;
+}
+
+int smbus_rom_device::execute_command(int command, int rw, int data)
+{
+ if ((rw == 1) && (command < buffer_size) && (buffer != nullptr))
+ {
+ logerror("smbus rom read from %02x %02x\n", command, buffer[command]);
+ return buffer[command];
+ }
+ return 0;
+}
+
+void smbus_rom_device::device_start()
+{
+}
+
+void smbus_rom_device::device_reset()
+{
+}
+
+// Asus AS99127F chip
+
+DEFINE_DEVICE_TYPE(AS99127F, as99127f_device, "as99127f", "Asus AS99127F")
+
+as99127f_device::as99127f_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : device_t(mconfig, AS99127F, tag, owner, clock)
+{
+}
+
+int as99127f_device::execute_command(int command, int rw, int data)
+{
+ if (rw == 1)
+ {
+ logerror("smbus read from %02x R %02x\n", command, buffer[command]);
+ return buffer[command];
+ }
+ buffer[command] = (uint8_t)data;
+ logerror("smbus write to %02x W %02x\n", command, data);
+ return 0;
+}
+
+void as99127f_device::device_start()
+{
+ memset(buffer, 0, sizeof(buffer));
+}
+
+DEFINE_DEVICE_TYPE(AS99127F_SENSOR2, as99127f_sensor2_device, "as99127f_sensor2", "Asus AS99127F temperature sensor 2")
+
+as99127f_sensor2_device::as99127f_sensor2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : device_t(mconfig, AS99127F_SENSOR2, tag, owner, clock)
+{
+}
+
+int as99127f_sensor2_device::execute_command(int command, int rw, int data)
+{
+ if (rw == 1)
+ {
+ logerror("smbus read from %02x R %02x\n", command, buffer[command]);
+ return buffer[command];
+ }
+ buffer[command] = (uint8_t)data;
+ logerror("smbus write to %02x W %02x\n", command, data);
+ return 0;
+}
+
+void as99127f_sensor2_device::device_start()
+{
+ memset(buffer, 0, sizeof(buffer));
+}
+
+DEFINE_DEVICE_TYPE(AS99127F_SENSOR3, as99127f_sensor3_device, "as99127f_sensor3", "Asus AS99127F temperature sensor 3")
+
+as99127f_sensor3_device::as99127f_sensor3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : device_t(mconfig, AS99127F_SENSOR3, tag, owner, clock)
+{
+}
+
+int as99127f_sensor3_device::execute_command(int command, int rw, int data)
+{
+ if (rw == 1)
+ {
+ logerror("smbus read from %02x R %02x\n", command, buffer[command]);
+ return buffer[command];
+ }
+ buffer[command] = (uint8_t)data;
+ logerror("smbus write to %02x W %02x\n", command, data);
+ return 0;
+}
+
+void as99127f_sensor3_device::device_start()
+{
+ memset(buffer, 0, sizeof(buffer));
+}
+
+/*
Machine state
*/
class nforcepc_state : public driver_device
{
public:
- struct boot_state_info {
+ struct boot_state_info
+ {
uint8_t val;
const char *const message;
};
@@ -120,17 +275,28 @@ private:
void nforce_map(address_map &map);
void nforce_map_io(address_map &map);
DECLARE_WRITE8_MEMBER(boot_state_award_w);
+ IRQ_CALLBACK_MEMBER(irq_callback);
+ DECLARE_WRITE_LINE_MEMBER(maincpu_interrupt);
virtual void machine_start() override;
virtual void machine_reset() override;
+
+ required_device<cpu_device> m_maincpu;
+ required_device<mcpx_isalpc_device> isalpc;
+ required_device<as99127f_device> m_as99127f;
};
-nforcepc_state::nforcepc_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag)
+nforcepc_state::nforcepc_state(const machine_config &mconfig, device_type type, const char *tag) :
+ driver_device(mconfig, type, tag),
+ m_maincpu(*this, "maincpu"),
+ isalpc(*this, ":pci:01.0"),
+ m_as99127f(*this, ":pci:01.1:12d")
{
}
void nforcepc_state::machine_start()
{
+ m_as99127f->get_buffer()[0x4f] = 0x12;
}
void nforcepc_state::machine_reset()
@@ -138,19 +304,30 @@ void nforcepc_state::machine_reset()
}
const nforcepc_state::boot_state_info nforcepc_state::boot_state_infos_award[] = {
+ { 0xC0, "Turn off chipset cache" },
{ 0, nullptr }
};
WRITE8_MEMBER(nforcepc_state::boot_state_award_w)
{
const char *desc = "";
- for(int i=0; boot_state_infos_award[i].message; i++)
- if(boot_state_infos_award[i].val == data) {
+ for (int i = 0; boot_state_infos_award[i].message; i++)
+ if (boot_state_infos_award[i].val == data)
+ {
desc = boot_state_infos_award[i].message;
break;
}
logerror("Boot state %02x - %s\n", data, desc);
+}
+
+IRQ_CALLBACK_MEMBER(nforcepc_state::irq_callback)
+{
+ return isalpc->acknowledge();
+}
+WRITE_LINE_MEMBER(nforcepc_state::maincpu_interrupt)
+{
+ m_maincpu->set_input_line(0, state ? HOLD_LINE : CLEAR_LINE);
}
void nforcepc_state::nforce_map(address_map &map)
@@ -172,14 +349,33 @@ void nforcepc_state::nforcepc(machine_config &config)
athlonxp_device &maincpu(ATHLONXP(config, "maincpu", 90000000));
maincpu.set_addrmap(AS_PROGRAM, &nforcepc_state::nforce_map);
maincpu.set_addrmap(AS_IO, &nforcepc_state::nforce_map_io);
- PCI_ROOT(config, ":pci", 0);
- CRUSH11(config, ":pci:00.0", 0, "maincpu", 2 * 1024 * 1024);
- /* maincpu.set_irq_acknowledge_callback("pci:07.0:pic8259_master", FUNC(pic8259_device::inta_cb));
- maincpu.smiact().set("pci:00.0", FUNC(i82439hx_host_device::smi_act_w));
+ maincpu.set_irq_acknowledge_callback(FUNC(nforcepc_state::irq_callback));
- i82371sb_isa_device &isa(I82371SB_ISA(config, ":pci:07.0", 0));
- isa.boot_state_hook().set(FUNC(nforcepc_state::boot_state_phoenix_ver40_rev6_w));
- isa.smi().set_inputline(":maincpu", INPUT_LINE_SMI);
+ PCI_ROOT(config, ":pci", 0);
+ CRUSH11(config, ":pci:00.0", 0, "maincpu", 2 * 1024 * 1024); /* 10de:01a4 NVIDIA Corporation nForce CPU bridge
+ 10de:01ac NVIDIA Corporation nForce 220/420 Memory Controller
+ 10de:01ad NVIDIA Corporation nForce 220/420 Memory Controller
+ 10de:01ab NVIDIA Corporation nForce 420 Memory Controller (DDR)*/
+ mcpx_isalpc_device &isa(MCPX_ISALPC(config, ":pci:01.0", 0, 0x10430c11)); // 10de:01b2 NVIDIA Corporation nForce ISA Bridge (LPC bus)
+ isa.boot_state_hook().set(FUNC(nforcepc_state::boot_state_award_w));
+ isa.interrupt_output().set(FUNC(nforcepc_state::maincpu_interrupt));
+ MCPX_SMBUS(config, ":pci:01.1", 0); // 10de:01b4 NVIDIA Corporation nForce PCI System Management (SMBus)
+ SMBUS_ROM(config, ":pci:01.1:050", 0, test_spd_data, sizeof(test_spd_data)); // these 3 are on smbus number 0
+ SMBUS_LOGGER(config, ":pci:01.1:051", 0);
+ SMBUS_LOGGER(config, ":pci:01.1:052", 0);
+ SMBUS_LOGGER(config, ":pci:01.1:108", 0); // these 4 are on smbus number 1
+ AS99127F(config, ":pci:01.1:12d", 0);
+ AS99127F_SENSOR2(config, ":pci:01.1:148", 0);
+ AS99127F_SENSOR3(config, ":pci:01.1:149", 0);
+ /*10de:01c2 NVIDIA Corporation nForce USB Controller
+ 10de:01c2 NVIDIA Corporation nForce USB Controller
+ 10de:01b0 NVIDIA Corporation nForce Audio Processing Unit
+ 10de:01b1 NVIDIA Corporation nForce AC'97 Audio Controller
+ 10de:01b8 NVIDIA Corporation nForce PCI-to-PCI bridge
+ 10de:01bc NVIDIA Corporation nForce IDE
+ 10de:01b7 NVIDIA Corporation nForce AGP to PCI Bridge
+ */
+ /* maincpu.smiact().set("pci:00.0", FUNC(i82439hx_host_device::smi_act_w));
i82371sb_ide_device &ide(I82371SB_IDE(config, ":pci:07.1", 0));
ide.irq_pri().set(":pci:07.0", FUNC(i82371sb_isa_device::pc_irq14_w));
@@ -189,9 +385,9 @@ void nforcepc_state::nforcepc(machine_config &config)
ROM_START(nforcepc)
ROM_REGION32_LE(0x40000, ":pci:00.0", 0) /* PC bios */
ROM_SYSTEM_BIOS(0, "a7n266c", "a7n266c") // Motherboard dump. Chip: SST49LF020 Package: PLCC32 Label had 3 lines of text: "A7NC3" "1001.D" "GSQ98"
- ROMX_LOAD("a7n266c.bin", 0, 0x40000, CRC(F4F0E4FC), ROM_BIOS(0))
- ROM_SYSTEM_BIOS(1, "a7n266c1001d", "a7n266c1001d") // bios version 1001.D dwonloaded from Asus website
- ROMX_LOAD("a7nc101d.awd", 0, 0x40000, CRC(EAD1147C), ROM_BIOS(1))
+ ROMX_LOAD("a7n266c.bin", 0, 0x40000, CRC(f4f0e4fc) SHA1(87f11545db178914623e41fb51e328da479a2efc), ROM_BIOS(0))
+ ROM_SYSTEM_BIOS(1, "a7n266c1001d", "a7n266c1001d") // bios version 1001.D downloaded from Asus website
+ ROMX_LOAD("a7nc101d.awd", 0, 0x40000, CRC(ead1147c) SHA1(27227df98e0c5fb9fecdb4bb6ef72df19766c330), ROM_BIOS(1))
ROM_END
static INPUT_PORTS_START(nforcepc)