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Diffstat (limited to 'src/mame/drivers/naomi.cpp')
-rw-r--r--src/mame/drivers/naomi.cpp26
1 files changed, 13 insertions, 13 deletions
diff --git a/src/mame/drivers/naomi.cpp b/src/mame/drivers/naomi.cpp
index c41b9ae0c93..e97ed70a585 100644
--- a/src/mame/drivers/naomi.cpp
+++ b/src/mame/drivers/naomi.cpp
@@ -1754,13 +1754,13 @@ void naomi_state::naomi_map(address_map &map)
map(0x13000000, 0x13ffffff).w(m_powervr2, FUNC(powervr2_device::ta_texture_directpath1_w)); // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)
/* Area 5 */
- //AM_RANGE(0x14000000, 0x17ffffff) AM_NOP // MPX Ext.
+ //map(0x14000000, 0x17ffffff).noprw(); // MPX Ext.
/* Area 6 */
- //AM_RANGE(0x18000000, 0x1bffffff) AM_NOP // Unassigned
+ //map(0x18000000, 0x1bffffff).noprw(); // Unassigned
/* Area 7 */
- //AM_RANGE(0x1c000000, 0x1fffffff) AM_NOP // SH4 Internal
+ //map(0x1c000000, 0x1fffffff).noprw(); // SH4 Internal
}
/*
@@ -1797,9 +1797,9 @@ void naomi2_state::naomi2_map(address_map &map)
map(0x025f7c00, 0x025f7cff).m(m_powervr2_slave, FUNC(powervr2_device::pd_dma_map));
map(0x025f8000, 0x025f9fff).m(m_powervr2_slave, FUNC(powervr2_device::ta_map));
-// AM_RANGE(0x025f6800, 0x025f69ff) AM_READWRITE(dc_sysctrl_r, dc_sysctrl_w ) // second PVR DMA!
-// AM_RANGE(0x025f7c00, 0x025f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, 0xffffffffffffffffU)
-// AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, 0xffffffffffffffffU)
+// map(0x025f6800, 0x025f69ff).rw(FUNC(naomi2_state::dc_sysctrl_r), FUNC(naomi2_state::dc_sysctrl_w)); // second PVR DMA!
+// map(0x025f7c00, 0x025f7cff).rw("powervr2", FUNC(powervr2_device::pvr_ctrl_r), FUNC(powervr2_device::pvr_ctrl_w));
+// map(0x005f8000, 0x005f9fff).mirror(0x02000000).m("powervr2", FUNC(powervr2_device::ta_map));
/* Area 1 */
map(0x04000000, 0x04ffffff).ram().share("dc_texture_ram"); // texture memory 64 bit access
@@ -1811,7 +1811,7 @@ void naomi2_state::naomi2_map(address_map &map)
map(0x085f6800, 0x085f69ff).w(FUNC(naomi2_state::dc_sysctrl_w)); // TODO: writes to BOTH PVRs
map(0x085f8000, 0x085f9fff).w(FUNC(naomi2_state::both_pvr2_ta_w));
map(0x08800000, 0x088000ff).rw(m_powervr2, FUNC(powervr2_device::elan_regs_r), FUNC(powervr2_device::elan_regs_w)); // T&L chip registers
-// AM_RANGE(0x09000000, 0x09??????) T&L command processing
+// map(0x09000000, 0x09??????) T&L command processing
map(0x0a000000, 0x0bffffff).ram().share("elan_ram"); // T&L chip RAM
/* Area 3 */
@@ -1825,13 +1825,13 @@ void naomi2_state::naomi2_map(address_map &map)
map(0x13000000, 0x13ffffff).w(m_powervr2, FUNC(powervr2_device::ta_texture_directpath1_w)); // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)
/* Area 5 */
- //AM_RANGE(0x14000000, 0x17ffffff) AM_NOP // MPX Ext.
+ //map(0x14000000, 0x17ffffff).noprw(); // MPX Ext.
/* Area 6 */
- //AM_RANGE(0x18000000, 0x1bffffff) AM_NOP // Unassigned
+ //map(0x18000000, 0x1bffffff).noprw(); // Unassigned
/* Area 7 */
- //AM_RANGE(0x1c000000, 0x1fffffff) AM_NOP // SH4 Internal
+ //map(0x1c000000, 0x1fffffff).noprw(); // SH4 Internal
}
@@ -1994,13 +1994,13 @@ void atomiswave_state::aw_map(address_map &map)
/* Area 5 */
- //AM_RANGE(0x14000000, 0x17ffffff) AM_NOP // MPX Ext.
+ //map(0x14000000, 0x17ffffff).noprw(); // MPX Ext.
/* Area 6 */
- //AM_RANGE(0x18000000, 0x1bffffff) AM_NOP // Unassigned
+ //map(0x18000000, 0x1bffffff).noprw(); // Unassigned
/* Area 7 */
- //AM_RANGE(0x1c000000, 0x1fffffff) AM_NOP // SH4 Internal
+ //map(0x1c000000, 0x1fffffff).noprw(); // SH4 Internal
}
void atomiswave_state::aw_port(address_map &map)