diff options
Diffstat (limited to 'src/mame/drivers/model3.cpp')
-rw-r--r-- | src/mame/drivers/model3.cpp | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/src/mame/drivers/model3.cpp b/src/mame/drivers/model3.cpp index 3113d0b8fbd..a98a8ebae7c 100644 --- a/src/mame/drivers/model3.cpp +++ b/src/mame/drivers/model3.cpp @@ -1073,28 +1073,28 @@ READ64_MEMBER(model3_state::scsi_r) int reg = offset*8; uint64_t r = 0; if (ACCESSING_BITS_56_63) { - r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+0) << 56; + r |= (uint64_t)m_lsi53c810->reg_r(reg+0) << 56; } if (ACCESSING_BITS_48_55) { - r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+1) << 48; + r |= (uint64_t)m_lsi53c810->reg_r(reg+1) << 48; } if (ACCESSING_BITS_40_47) { - r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+2) << 40; + r |= (uint64_t)m_lsi53c810->reg_r(reg+2) << 40; } if (ACCESSING_BITS_32_39) { - r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+3) << 32; + r |= (uint64_t)m_lsi53c810->reg_r(reg+3) << 32; } if (ACCESSING_BITS_24_31) { - r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+4) << 24; + r |= (uint64_t)m_lsi53c810->reg_r(reg+4) << 24; } if (ACCESSING_BITS_16_23) { - r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+5) << 16; + r |= (uint64_t)m_lsi53c810->reg_r(reg+5) << 16; } if (ACCESSING_BITS_8_15) { - r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+6) << 8; + r |= (uint64_t)m_lsi53c810->reg_r(reg+6) << 8; } if (ACCESSING_BITS_0_7) { - r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+7) << 0; + r |= (uint64_t)m_lsi53c810->reg_r(reg+7) << 0; } return r; @@ -1104,28 +1104,28 @@ WRITE64_MEMBER(model3_state::scsi_w) { int reg = offset*8; if (ACCESSING_BITS_56_63) { - m_lsi53c810->lsi53c810_reg_w(reg+0, data >> 56); + m_lsi53c810->reg_w(reg+0, data >> 56); } if (ACCESSING_BITS_48_55) { - m_lsi53c810->lsi53c810_reg_w(reg+1, data >> 48); + m_lsi53c810->reg_w(reg+1, data >> 48); } if (ACCESSING_BITS_40_47) { - m_lsi53c810->lsi53c810_reg_w(reg+2, data >> 40); + m_lsi53c810->reg_w(reg+2, data >> 40); } if (ACCESSING_BITS_32_39) { - m_lsi53c810->lsi53c810_reg_w(reg+3, data >> 32); + m_lsi53c810->reg_w(reg+3, data >> 32); } if (ACCESSING_BITS_24_31) { - m_lsi53c810->lsi53c810_reg_w(reg+4, data >> 24); + m_lsi53c810->reg_w(reg+4, data >> 24); } if (ACCESSING_BITS_16_23) { - m_lsi53c810->lsi53c810_reg_w(reg+5, data >> 16); + m_lsi53c810->reg_w(reg+5, data >> 16); } if (ACCESSING_BITS_8_15) { - m_lsi53c810->lsi53c810_reg_w(reg+6, data >> 8); + m_lsi53c810->reg_w(reg+6, data >> 8); } if (ACCESSING_BITS_0_7) { - m_lsi53c810->lsi53c810_reg_w(reg+7, data >> 0); + m_lsi53c810->reg_w(reg+7, data >> 0); } } @@ -5701,7 +5701,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(model3_state::model3_interrupt) } } -static MACHINE_CONFIG_START( model3_10, model3_state ) +static MACHINE_CONFIG_START( model3_10 ) MCFG_CPU_ADD("maincpu", PPC603E, 66000000) MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 1, Bus = 66MHz, Core = 66MHz */ MCFG_CPU_PROGRAM_MAP(model3_10_mem) @@ -5749,7 +5749,7 @@ static MACHINE_CONFIG_START( model3_10, model3_state ) MCFG_LEGACY_SCSI_PORT("scsi") MACHINE_CONFIG_END -static MACHINE_CONFIG_START( model3_15, model3_state ) +static MACHINE_CONFIG_START( model3_15 ) MCFG_CPU_ADD("maincpu", PPC603E, 100000000) MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ MCFG_CPU_PROGRAM_MAP(model3_mem) @@ -5810,7 +5810,7 @@ static MACHINE_CONFIG_DERIVED(scud, model3_15) MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("uart", i8251_device, write_rxc)) MACHINE_CONFIG_END -static MACHINE_CONFIG_START(model3_20, model3_state) +static MACHINE_CONFIG_START(model3_20) MCFG_CPU_ADD("maincpu", PPC603R, 166000000) MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 2.5, Bus = 66MHz, Core = 166MHz */ MCFG_CPU_PROGRAM_MAP(model3_mem) @@ -5855,7 +5855,7 @@ static MACHINE_CONFIG_DERIVED(model3_20_5881, model3_20) MCFG_SET_READ_CALLBACK(model3_state, crypt_read_callback) MACHINE_CONFIG_END -static MACHINE_CONFIG_START(model3_21, model3_state) +static MACHINE_CONFIG_START(model3_21) MCFG_CPU_ADD("maincpu", PPC603R, 166000000) MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 2.5, Bus = 66MHz, Core = 166MHz */ MCFG_CPU_PROGRAM_MAP(model3_mem) |