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path: root/src/mame/drivers/midqslvr.c
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Diffstat (limited to 'src/mame/drivers/midqslvr.c')
-rw-r--r--src/mame/drivers/midqslvr.c78
1 files changed, 39 insertions, 39 deletions
diff --git a/src/mame/drivers/midqslvr.c b/src/mame/drivers/midqslvr.c
index 7d32b557c5f..867340150e9 100644
--- a/src/mame/drivers/midqslvr.c
+++ b/src/mame/drivers/midqslvr.c
@@ -40,13 +40,13 @@ class midqslvr_state : public driver_device
public:
midqslvr_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
- m_maincpu(*this, "maincpu"),
- m_pit8254(*this, "pit8254"),
- m_dma8237_1(*this, "dma8237_1"),
- m_dma8237_2(*this, "dma8237_2"),
- m_pic8259_1(*this, "pic8259_1"),
- m_pic8259_2(*this, "pic8259_2")
- { }
+ m_maincpu(*this, "maincpu"),
+ m_pit8254(*this, "pit8254"),
+ m_dma8237_1(*this, "dma8237_1"),
+ m_dma8237_2(*this, "dma8237_2"),
+ m_pic8259_1(*this, "pic8259_1"),
+ m_pic8259_2(*this, "pic8259_2")
+ { }
UINT32 *m_bios_ram;
UINT32 *m_bios_ext1_ram;
@@ -120,32 +120,32 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i
printf("MXTC: write %d, %02X, %02X\n", function, reg, data);
/*
- memory banking with North Bridge:
- 0x59 (PAM0) xxxx ---- BIOS area 0xf0000-0xfffff
- ---- xxxx Reserved
- 0x5a (PAM1) xxxx ---- ISA add-on BIOS 0xc4000 - 0xc7fff
- ---- xxxx ISA add-on BIOS 0xc0000 - 0xc3fff
- 0x5b (PAM2) xxxx ---- ISA add-on BIOS 0xcc000 - 0xcffff
- ---- xxxx ISA add-on BIOS 0xc8000 - 0xcbfff
- 0x5c (PAM3) xxxx ---- ISA add-on BIOS 0xd4000 - 0xd7fff
- ---- xxxx ISA add-on BIOS 0xd0000 - 0xd3fff
- 0x5d (PAM4) xxxx ---- ISA add-on BIOS 0xdc000 - 0xdffff
- ---- xxxx ISA add-on BIOS 0xd8000 - 0xdbfff
- 0x5e (PAM5) xxxx ---- BIOS extension 0xe4000 - 0xe7fff
- ---- xxxx BIOS extension 0xe0000 - 0xe3fff
- 0x5f (PAM6) xxxx ---- BIOS extension 0xec000 - 0xeffff
- ---- xxxx BIOS extension 0xe8000 - 0xebfff
-
- 3210 -> 3 = reserved, 2 = Cache Enable, 1 = Write Enable, 0 = Read Enable
- */
+ memory banking with North Bridge:
+ 0x59 (PAM0) xxxx ---- BIOS area 0xf0000-0xfffff
+ ---- xxxx Reserved
+ 0x5a (PAM1) xxxx ---- ISA add-on BIOS 0xc4000 - 0xc7fff
+ ---- xxxx ISA add-on BIOS 0xc0000 - 0xc3fff
+ 0x5b (PAM2) xxxx ---- ISA add-on BIOS 0xcc000 - 0xcffff
+ ---- xxxx ISA add-on BIOS 0xc8000 - 0xcbfff
+ 0x5c (PAM3) xxxx ---- ISA add-on BIOS 0xd4000 - 0xd7fff
+ ---- xxxx ISA add-on BIOS 0xd0000 - 0xd3fff
+ 0x5d (PAM4) xxxx ---- ISA add-on BIOS 0xdc000 - 0xdffff
+ ---- xxxx ISA add-on BIOS 0xd8000 - 0xdbfff
+ 0x5e (PAM5) xxxx ---- BIOS extension 0xe4000 - 0xe7fff
+ ---- xxxx BIOS extension 0xe0000 - 0xe3fff
+ 0x5f (PAM6) xxxx ---- BIOS extension 0xec000 - 0xeffff
+ ---- xxxx BIOS extension 0xe8000 - 0xebfff
+
+ 3210 -> 3 = reserved, 2 = Cache Enable, 1 = Write Enable, 0 = Read Enable
+ */
switch(reg)
{
case 0x59: // PAM0
{
- if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
+ if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
state->membank("bios_bank")->set_base(state->m_bios_ram);
- else // disable RAM access (reads go to BIOS ROM)
+ else // disable RAM access (reads go to BIOS ROM)
state->membank("bios_bank")->set_base(state->memregion("bios")->base() + 0x70000);
break;
}
@@ -335,7 +335,7 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi
WRITE32_MEMBER(midqslvr_state::isa_ram1_w)
{
- if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
+ if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
{
COMBINE_DATA(m_isa_ram1 + offset);
}
@@ -343,7 +343,7 @@ WRITE32_MEMBER(midqslvr_state::isa_ram1_w)
WRITE32_MEMBER(midqslvr_state::isa_ram2_w)
{
- if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
+ if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
{
COMBINE_DATA(m_isa_ram2 + offset);
}
@@ -351,7 +351,7 @@ WRITE32_MEMBER(midqslvr_state::isa_ram2_w)
WRITE32_MEMBER(midqslvr_state::bios_ext1_ram_w)
{
- if (m_mxtc_config_reg[0x5e] & 0x2) // write to RAM if this region is write-enabled
+ if (m_mxtc_config_reg[0x5e] & 0x2) // write to RAM if this region is write-enabled
{
COMBINE_DATA(m_bios_ext1_ram + offset);
}
@@ -360,7 +360,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext1_ram_w)
WRITE32_MEMBER(midqslvr_state::bios_ext2_ram_w)
{
- if (m_mxtc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled
+ if (m_mxtc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled
{
COMBINE_DATA(m_bios_ext2_ram + offset);
}
@@ -369,7 +369,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext2_ram_w)
WRITE32_MEMBER(midqslvr_state::bios_ext3_ram_w)
{
- if (m_mxtc_config_reg[0x5f] & 0x2) // write to RAM if this region is write-enabled
+ if (m_mxtc_config_reg[0x5f] & 0x2) // write to RAM if this region is write-enabled
{
COMBINE_DATA(m_bios_ext3_ram + offset);
}
@@ -378,7 +378,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext3_ram_w)
WRITE32_MEMBER(midqslvr_state::bios_ext4_ram_w)
{
- if (m_mxtc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled
+ if (m_mxtc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled
{
COMBINE_DATA(m_bios_ext4_ram + offset);
}
@@ -387,7 +387,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext4_ram_w)
WRITE32_MEMBER(midqslvr_state::bios_ram_w)
{
- if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
+ if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
{
COMBINE_DATA(m_bios_ram + offset);
}
@@ -543,7 +543,7 @@ static ADDRESS_MAP_START(midqslvr_map, AS_PROGRAM, 32, midqslvr_state)
AM_RANGE(0x000ec000, 0x000effff) AM_ROMBANK("bios_ext4") AM_WRITE(bios_ext4_ram_w)
AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bios_bank") AM_WRITE(bios_ram_w)
AM_RANGE(0x00100000, 0x01ffffff) AM_RAM
- AM_RANGE(0xfff80000, 0xffffffff) AM_ROM AM_REGION("bios", 0) /* System BIOS */
+ AM_RANGE(0xfff80000, 0xffffffff) AM_ROM AM_REGION("bios", 0) /* System BIOS */
ADDRESS_MAP_END
static ADDRESS_MAP_START(midqslvr_io, AS_IO, 32, midqslvr_state)
@@ -570,15 +570,15 @@ static const struct pit8253_config midqslvr_pit8254_config =
{
{
{
- 4772720/4, /* heartbeat IRQ */
+ 4772720/4, /* heartbeat IRQ */
DEVCB_NULL,
DEVCB_DEVICE_LINE("pic8259_1", pic8259_ir0_w)
}, {
- 4772720/4, /* dram refresh */
+ 4772720/4, /* dram refresh */
DEVCB_NULL,
DEVCB_NULL
}, {
- 4772720/4, /* pio port c pin 4, and speaker polling enough */
+ 4772720/4, /* pio port c pin 4, and speaker polling enough */
DEVCB_NULL,
DEVCB_NULL
}
@@ -680,7 +680,7 @@ void midqslvr_state::machine_reset()
}
static MACHINE_CONFIG_START( midqslvr, midqslvr_state )
- MCFG_CPU_ADD("maincpu", PENTIUM, 333000000) // actually Celeron 333
+ MCFG_CPU_ADD("maincpu", PENTIUM, 333000000) // actually Celeron 333
MCFG_CPU_PROGRAM_MAP(midqslvr_map)
MCFG_CPU_IO_MAP(midqslvr_io)