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-rw-r--r--src/mame/drivers/icebox.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mame/drivers/icebox.cpp b/src/mame/drivers/icebox.cpp
index 7ebd68045ae..3a1c7599cd7 100644
--- a/src/mame/drivers/icebox.cpp
+++ b/src/mame/drivers/icebox.cpp
@@ -108,8 +108,8 @@ on the boards to say which of the four selects it responds to.
The three byte fifo and a register jams a zero onto the data bus (when?), and we have the source for the CP/M version
of the debugger/boot prom to see how interrupt handling occurs.
-When the floppy controller generates a DRQ or INTRQ it also generates a Z80 INT, which uses IM 0
-and forces a NOP (00) onto the bus. This allows firmware and/or disk routines to resume after a HALT.
+When the floppy controller generates a DRQ or INTRQ it also generates a Z80 INT, which uses IM 0
+and forces a NOP (00) onto the bus. This allows firmware and/or disk routines to resume after a HALT.
I can sort of piece together what Terse implements and what it evolved from. I think it started as the Caltech FORTH
implemented for the PDP-10 and 11 with a lot of words stripped out, and others added. This was submitted to DECUS as