diff options
Diffstat (limited to 'src/emu/sound/tms5220.c')
-rw-r--r-- | src/emu/sound/tms5220.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/emu/sound/tms5220.c b/src/emu/sound/tms5220.c index dfee397802a..a60509d951f 100644 --- a/src/emu/sound/tms5220.c +++ b/src/emu/sound/tms5220.c @@ -153,7 +153,7 @@ Interpolation is inhibited (i.e. interpolation at IP frames will not happen ****Documentation of chip commands:*** - x0x0xbcc : on 5200/5220: NOP (does nothing); on 5220C: Select frame length by cc, and b selects whether every frame is preceeded by 2 bits to select the frame length (instead of using the value set by cc); the default (and after a reset command) is as if '0x00' was written, i.e. for frame length (200 samples) and 0 for whether the preceeding 2 bits are enabled (off) + x0x0xbcc : on 5200/5220: NOP (does nothing); on 5220C: Select frame length by cc, and b selects whether every frame is preceded by 2 bits to select the frame length (instead of using the value set by cc); the default (and after a reset command) is as if '0x00' was written, i.e. for frame length (200 samples) and 0 for whether the preceding 2 bits are enabled (off) x001xxxx: READ BYTE (RDBY) Sends eight read bit commands (M0 high M1 low) to VSM and reads the resulting bits serially into a temporary register, which becomes readable as the next byte read from the tms52xx once ready goes active. Note the bit order of the byte read from the TMS52xx is BACKWARDS as compared to the actual data order as in the rom on the VSM chips; the read byte command of the tms5100 reads the bits in the 'correct' order. This was IMHO a rather silly design decision of TI. (I (LN) asked Larry Brantingham about this but he wasn't involved with the TMS52xx chips, just the 5100); There's ASCII data in the TI 99/4 speech module VSMs which has the bit order reversed on purpose because of this! TALK STATUS must be CLEAR for this command to work; otherwise it is treated as a NOP. @@ -1041,7 +1041,7 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size tms->current_pitch += (((tms->target_pitch - tms->current_pitch)*(1-inhibit_state)) INTERP_SHIFT); break; case 2: case 3: case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11: - /* PC = 2 thru 11, B cycle, write updated K1 thru K10 */ + /* PC = 2 through 11, B cycle, write updated K1 through K10 */ tms->current_k[tms->PC-2] += (((tms->target_k[tms->PC-2] - tms->current_k[tms->PC-2])*(1-inhibit_state)) INTERP_SHIFT); break; case 12: /* PC = 12, do nothing */ @@ -1452,7 +1452,7 @@ static void parse_frame(tms5220_state *tms) // We actually don't care how many bits are left in the fifo here; the frame subpart will be processed normally, and any bits extracted 'past the end' of the fifo will be read as zeroes; the fifo being emptied will set the /BE latch which will halt speech exactly as if a stop frame had been encountered (instead of whatever partial frame was read); the same exact circuitry is used for both on the real chip, see us patent 4335277 sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS (decode disable) which is active during speak external). /* if the chip is a tms5220C, and the rate mode is set to that each frame (0x04 bit set) - has a 2 bit rate preceeding it, grab two bits here and store them as the rate; */ + has a 2 bit rate preceding it, grab two bits here and store them as the rate; */ if ((tms->variant == SUBTYPE_TMS5220C) && (tms->tms5220c_rate & 0x04)) { indx = extract_bits(tms, 2); |