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Diffstat (limited to 'src/emu/sound/fm.c')
-rw-r--r--src/emu/sound/fm.c826
1 files changed, 413 insertions, 413 deletions
diff --git a/src/emu/sound/fm.c b/src/emu/sound/fm.c
index b3c292c1c22..8e736522315 100644
--- a/src/emu/sound/fm.c
+++ b/src/emu/sound/fm.c
@@ -140,41 +140,41 @@
-#define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
-#define EG_SH 16 /* 16.16 fixed point (envelope generator timing) */
-#define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
-#define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
+#define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
+#define EG_SH 16 /* 16.16 fixed point (envelope generator timing) */
+#define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
+#define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
-#define FREQ_MASK ((1<<FREQ_SH)-1)
+#define FREQ_MASK ((1<<FREQ_SH)-1)
-#define ENV_BITS 10
-#define ENV_LEN (1<<ENV_BITS)
-#define ENV_STEP (128.0/ENV_LEN)
+#define ENV_BITS 10
+#define ENV_LEN (1<<ENV_BITS)
+#define ENV_STEP (128.0/ENV_LEN)
-#define MAX_ATT_INDEX (ENV_LEN-1) /* 1023 */
-#define MIN_ATT_INDEX (0) /* 0 */
+#define MAX_ATT_INDEX (ENV_LEN-1) /* 1023 */
+#define MIN_ATT_INDEX (0) /* 0 */
-#define EG_ATT 4
-#define EG_DEC 3
-#define EG_SUS 2
-#define EG_REL 1
-#define EG_OFF 0
+#define EG_ATT 4
+#define EG_DEC 3
+#define EG_SUS 2
+#define EG_REL 1
+#define EG_OFF 0
-#define SIN_BITS 10
-#define SIN_LEN (1<<SIN_BITS)
-#define SIN_MASK (SIN_LEN-1)
+#define SIN_BITS 10
+#define SIN_LEN (1<<SIN_BITS)
+#define SIN_MASK (SIN_LEN-1)
-#define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
+#define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
#if (FM_SAMPLE_BITS==16)
- #define FINAL_SH (0)
- #define MAXOUT (+32767)
- #define MINOUT (-32768)
+ #define FINAL_SH (0)
+ #define MAXOUT (+32767)
+ #define MINOUT (-32768)
#else
- #define FINAL_SH (8)
- #define MAXOUT (+127)
- #define MINOUT (-128)
+ #define FINAL_SH (8)
+ #define MAXOUT (+127)
+ #define MINOUT (-128)
#endif
@@ -186,7 +186,7 @@
#define TL_TAB_LEN (13*2*TL_RES_LEN)
static signed int tl_tab[TL_TAB_LEN];
-#define ENV_QUIET (TL_TAB_LEN>>3)
+#define ENV_QUIET (TL_TAB_LEN>>3)
/* sin waveform table in 'decibel' scale */
static unsigned int sin_tab[SIN_LEN];
@@ -199,8 +199,8 @@ static unsigned int sin_tab[SIN_LEN];
/* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
#define SC(db) (UINT32) ( db * (4.0/ENV_STEP) )
static const UINT32 sl_table[16]={
- SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
- SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
+ SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
+ SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
};
#undef SC
@@ -239,7 +239,7 @@ static const UINT8 eg_inc[19*RATE_STEPS]={
#define O(a) (a*RATE_STEPS)
/*note that there is no O(17) in this table - it's directly in the code */
-static const UINT8 eg_rate_select[32+64+32]={ /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
+static const UINT8 eg_rate_select[32+64+32]={ /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
/* 32 infinite time rates */
O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
@@ -287,7 +287,7 @@ O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
/*mask 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0, 0 */
#define O(a) (a*1)
-static const UINT8 eg_rate_shift[32+64+32]={ /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
+static const UINT8 eg_rate_shift[32+64+32]={ /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
/* 32 infinite time rates */
O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
@@ -499,15 +499,15 @@ static INT32 lfo_pm_table[128*8*32]; /* 128 combinations of 7 bits meaningful (o
#ifdef SAVE_SAMPLE
static FILE *sample[1];
- #if 1 /*save to MONO file */
+ #if 1 /*save to MONO file */
#define SAVE_ALL_CHANNELS \
- { signed int pom = lt; \
+ { signed int pom = lt; \
fputc((unsigned short)pom&0xff,sample[0]); \
fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
}
- #else /*save to STEREO file */
+ #else /*save to STEREO file */
#define SAVE_ALL_CHANNELS \
- { signed int pom = lt; \
+ { signed int pom = lt; \
fputc((unsigned short)pom&0xff,sample[0]); \
fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
pom = rt; \
@@ -521,97 +521,97 @@ static FILE *sample[1];
/* struct describing a single operator (SLOT) */
struct FM_SLOT
{
- INT32 *DT; /* detune :dt_tab[DT] */
- UINT8 KSR; /* key scale rate :3-KSR */
- UINT32 ar; /* attack rate */
- UINT32 d1r; /* decay rate */
- UINT32 d2r; /* sustain rate */
- UINT32 rr; /* release rate */
- UINT8 ksr; /* key scale rate :kcode>>(3-KSR) */
- UINT32 mul; /* multiple :ML_TABLE[ML] */
+ INT32 *DT; /* detune :dt_tab[DT] */
+ UINT8 KSR; /* key scale rate :3-KSR */
+ UINT32 ar; /* attack rate */
+ UINT32 d1r; /* decay rate */
+ UINT32 d2r; /* sustain rate */
+ UINT32 rr; /* release rate */
+ UINT8 ksr; /* key scale rate :kcode>>(3-KSR) */
+ UINT32 mul; /* multiple :ML_TABLE[ML] */
/* Phase Generator */
- UINT32 phase; /* phase counter */
- INT32 Incr; /* phase step */
+ UINT32 phase; /* phase counter */
+ INT32 Incr; /* phase step */
/* Envelope Generator */
- UINT8 state; /* phase type */
- UINT32 tl; /* total level: TL << 3 */
- INT32 volume; /* envelope counter */
- UINT32 sl; /* sustain level:sl_table[SL] */
- UINT32 vol_out; /* current output from EG circuit (without AM from LFO) */
-
- UINT8 eg_sh_ar; /* (attack state) */
- UINT8 eg_sel_ar; /* (attack state) */
- UINT8 eg_sh_d1r; /* (decay state) */
- UINT8 eg_sel_d1r; /* (decay state) */
- UINT8 eg_sh_d2r; /* (sustain state) */
- UINT8 eg_sel_d2r; /* (sustain state) */
- UINT8 eg_sh_rr; /* (release state) */
- UINT8 eg_sel_rr; /* (release state) */
-
- UINT8 ssg; /* SSG-EG waveform */
- UINT8 ssgn; /* SSG-EG negated output */
-
- UINT32 key; /* 0=last key was KEY OFF, 1=KEY ON */
+ UINT8 state; /* phase type */
+ UINT32 tl; /* total level: TL << 3 */
+ INT32 volume; /* envelope counter */
+ UINT32 sl; /* sustain level:sl_table[SL] */
+ UINT32 vol_out; /* current output from EG circuit (without AM from LFO) */
+
+ UINT8 eg_sh_ar; /* (attack state) */
+ UINT8 eg_sel_ar; /* (attack state) */
+ UINT8 eg_sh_d1r; /* (decay state) */
+ UINT8 eg_sel_d1r; /* (decay state) */
+ UINT8 eg_sh_d2r; /* (sustain state) */
+ UINT8 eg_sel_d2r; /* (sustain state) */
+ UINT8 eg_sh_rr; /* (release state) */
+ UINT8 eg_sel_rr; /* (release state) */
+
+ UINT8 ssg; /* SSG-EG waveform */
+ UINT8 ssgn; /* SSG-EG negated output */
+
+ UINT32 key; /* 0=last key was KEY OFF, 1=KEY ON */
/* LFO */
- UINT32 AMmask; /* AM enable flag */
+ UINT32 AMmask; /* AM enable flag */
};
struct FM_CH
{
- FM_SLOT SLOT[4]; /* four SLOTs (operators) */
+ FM_SLOT SLOT[4]; /* four SLOTs (operators) */
- UINT8 ALGO; /* algorithm */
- UINT8 FB; /* feedback shift */
- INT32 op1_out[2]; /* op1 output for feedback */
+ UINT8 ALGO; /* algorithm */
+ UINT8 FB; /* feedback shift */
+ INT32 op1_out[2]; /* op1 output for feedback */
- INT32 *connect1; /* SLOT1 output pointer */
- INT32 *connect3; /* SLOT3 output pointer */
- INT32 *connect2; /* SLOT2 output pointer */
- INT32 *connect4; /* SLOT4 output pointer */
+ INT32 *connect1; /* SLOT1 output pointer */
+ INT32 *connect3; /* SLOT3 output pointer */
+ INT32 *connect2; /* SLOT2 output pointer */
+ INT32 *connect4; /* SLOT4 output pointer */
- INT32 *mem_connect;/* where to put the delayed sample (MEM) */
- INT32 mem_value; /* delayed sample (MEM) value */
+ INT32 *mem_connect;/* where to put the delayed sample (MEM) */
+ INT32 mem_value; /* delayed sample (MEM) value */
- INT32 pms; /* channel PMS */
- UINT8 ams; /* channel AMS */
+ INT32 pms; /* channel PMS */
+ UINT8 ams; /* channel AMS */
- UINT32 fc; /* fnum,blk:adjusted to sample rate */
- UINT8 kcode; /* key code: */
- UINT32 block_fnum; /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
+ UINT32 fc; /* fnum,blk:adjusted to sample rate */
+ UINT8 kcode; /* key code: */
+ UINT32 block_fnum; /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
};
struct FM_ST
{
device_t *device;
- void * param; /* this chip parameter */
- int clock; /* master clock (Hz) */
- int rate; /* sampling rate (Hz) */
- double freqbase; /* frequency base */
- int timer_prescaler; /* timer prescaler */
+ void * param; /* this chip parameter */
+ int clock; /* master clock (Hz) */
+ int rate; /* sampling rate (Hz) */
+ double freqbase; /* frequency base */
+ int timer_prescaler; /* timer prescaler */
#if FM_BUSY_FLAG_SUPPORT
- TIME_TYPE busy_expiry_time; /* expiry time of the busy status */
+ TIME_TYPE busy_expiry_time; /* expiry time of the busy status */
#endif
- UINT8 address; /* address register */
- UINT8 irq; /* interrupt level */
- UINT8 irqmask; /* irq mask */
- UINT8 status; /* status flag */
- UINT32 mode; /* mode CSM / 3SLOT */
- UINT8 prescaler_sel; /* prescaler selector */
- UINT8 fn_h; /* freq latch */
- INT32 TA; /* timer a */
- INT32 TAC; /* timer a counter */
- UINT8 TB; /* timer b */
- INT32 TBC; /* timer b counter */
+ UINT8 address; /* address register */
+ UINT8 irq; /* interrupt level */
+ UINT8 irqmask; /* irq mask */
+ UINT8 status; /* status flag */
+ UINT32 mode; /* mode CSM / 3SLOT */
+ UINT8 prescaler_sel; /* prescaler selector */
+ UINT8 fn_h; /* freq latch */
+ INT32 TA; /* timer a */
+ INT32 TAC; /* timer a counter */
+ UINT8 TB; /* timer b */
+ INT32 TBC; /* timer b counter */
/* local time tables */
- INT32 dt_tab[8][32]; /* DeTune table */
+ INT32 dt_tab[8][32]; /* DeTune table */
/* Extention Timer and IRQ handler */
- FM_TIMERHANDLER timer_handler;
- FM_IRQHANDLER IRQ_Handler;
+ FM_TIMERHANDLER timer_handler;
+ FM_IRQHANDLER IRQ_Handler;
const ssg_callbacks *SSG;
};
@@ -624,50 +624,50 @@ struct FM_ST
/* OPN 3slot struct */
struct FM_3SLOT
{
- UINT32 fc[3]; /* fnum3,blk3: calculated */
- UINT8 fn_h; /* freq3 latch */
- UINT8 kcode[3]; /* key code */
- UINT32 block_fnum[3]; /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
+ UINT32 fc[3]; /* fnum3,blk3: calculated */
+ UINT8 fn_h; /* freq3 latch */
+ UINT8 kcode[3]; /* key code */
+ UINT32 block_fnum[3]; /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
};
/* OPN/A/B common state */
struct FM_OPN
{
- UINT8 type; /* chip type */
- FM_ST ST; /* general state */
- FM_3SLOT SL3; /* 3 slot mode state */
- FM_CH *P_CH; /* pointer of CH */
- unsigned int pan[6*2]; /* fm channels output masks (0xffffffff = enable) */
+ UINT8 type; /* chip type */
+ FM_ST ST; /* general state */
+ FM_3SLOT SL3; /* 3 slot mode state */
+ FM_CH *P_CH; /* pointer of CH */
+ unsigned int pan[6*2]; /* fm channels output masks (0xffffffff = enable) */
- UINT32 eg_cnt; /* global envelope generator counter */
- UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/64/3 */
- UINT32 eg_timer_add; /* step of eg_timer */
- UINT32 eg_timer_overflow;/* envelope generator timer overlfows every 3 samples (on real chip) */
+ UINT32 eg_cnt; /* global envelope generator counter */
+ UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/64/3 */
+ UINT32 eg_timer_add; /* step of eg_timer */
+ UINT32 eg_timer_overflow;/* envelope generator timer overlfows every 3 samples (on real chip) */
/* there are 2048 FNUMs that can be generated using FNUM/BLK registers
- but LFO works with one more bit of a precision so we really need 4096 elements */
+ but LFO works with one more bit of a precision so we really need 4096 elements */
- UINT32 fn_table[4096]; /* fnumber->increment counter */
+ UINT32 fn_table[4096]; /* fnumber->increment counter */
UINT32 fn_max; /* maximal phase increment (used for phase overflow) */
/* LFO */
- UINT32 LFO_AM; /* runtime LFO calculations helper */
- INT32 LFO_PM; /* runtime LFO calculations helper */
+ UINT32 LFO_AM; /* runtime LFO calculations helper */
+ INT32 LFO_PM; /* runtime LFO calculations helper */
- UINT32 lfo_cnt;
- UINT32 lfo_inc;
+ UINT32 lfo_cnt;
+ UINT32 lfo_inc;
- UINT32 lfo_freq[8]; /* LFO FREQ table */
+ UINT32 lfo_freq[8]; /* LFO FREQ table */
- INT32 m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */
- INT32 mem; /* one sample delay memory */
+ INT32 m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */
+ INT32 mem; /* one sample delay memory */
- INT32 out_fm[8]; /* outputs of working channels */
+ INT32 out_fm[8]; /* outputs of working channels */
#if (BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B)
- INT32 out_adpcm[4]; /* channel output NONE,LEFT,RIGHT or CENTER for YM2608/YM2610 ADPCM */
- INT32 out_delta[4]; /* channel output NONE,LEFT,RIGHT or CENTER for YM2608/YM2610 DELTAT*/
+ INT32 out_adpcm[4]; /* channel output NONE,LEFT,RIGHT or CENTER for YM2608/YM2610 ADPCM */
+ INT32 out_delta[4]; /* channel output NONE,LEFT,RIGHT or CENTER for YM2608/YM2610 DELTAT*/
#endif
};
@@ -757,7 +757,7 @@ INLINE void set_timers( FM_ST *ST, void *n, int v )
}
}
else
- { /* stop timer b */
+ { /* stop timer b */
if( ST->TBC != 0 )
{
ST->TBC = 0;
@@ -775,7 +775,7 @@ INLINE void set_timers( FM_ST *ST, void *n, int v )
}
}
else
- { /* stop timer a */
+ { /* stop timer a */
if( ST->TAC != 0 )
{
ST->TAC = 0;
@@ -809,23 +809,23 @@ INLINE void TimerBOver(FM_ST *ST)
/* ----- internal timer mode , update timer */
/* ---------- calculate timer A ---------- */
- #define INTERNAL_TIMER_A(ST,CSM_CH) \
- { \
- if( ST->TAC && (ST->timer_handler==0) ) \
- if( (ST->TAC -= (int)(ST->freqbase*4096)) <= 0 ) \
- { \
- TimerAOver( ST ); \
- /* CSM mode total level latch and auto key on */ \
- if( ST->mode & 0x80 ) \
- CSMKeyControll( CSM_CH ); \
- } \
+ #define INTERNAL_TIMER_A(ST,CSM_CH) \
+ { \
+ if( ST->TAC && (ST->timer_handler==0) ) \
+ if( (ST->TAC -= (int)(ST->freqbase*4096)) <= 0 ) \
+ { \
+ TimerAOver( ST ); \
+ /* CSM mode total level latch and auto key on */ \
+ if( ST->mode & 0x80 ) \
+ CSMKeyControll( CSM_CH ); \
+ } \
}
/* ---------- calculate timer B ---------- */
- #define INTERNAL_TIMER_B(ST,step) \
- { \
- if( ST->TBC && (ST->timer_handler==0) ) \
- if( (ST->TBC -= (int)(ST->freqbase*4096*step)) <= 0 ) \
- TimerBOver( ST ); \
+ #define INTERNAL_TIMER_B(ST,step) \
+ { \
+ if( ST->TBC && (ST->timer_handler==0) ) \
+ if( (ST->TBC -= (int)(ST->freqbase*4096*step)) <= 0 ) \
+ TimerBOver( ST ); \
}
#else /* FM_INTERNAL_TIMER */
/* external timer mode */
@@ -842,7 +842,7 @@ INLINE UINT8 FM_STATUS_FLAG(FM_ST *ST)
if( COMPARE_TIMES(ST->busy_expiry_time, UNDEFINED_TIME) != 0 )
{
if (COMPARE_TIMES(ST->busy_expiry_time, FM_GET_TIME_NOW(&ST->device->machine())) > 0)
- return ST->status | 0x80; /* with busy */
+ return ST->status | 0x80; /* with busy */
/* expire */
FM_BUSY_CLEAR(ST);
}
@@ -868,7 +868,7 @@ INLINE void FM_KEYON(UINT8 type, FM_CH *CH , int s )
if( !SLOT->key )
{
SLOT->key = 1;
- SLOT->phase = 0; /* restart Phase Generator */
+ SLOT->phase = 0; /* restart Phase Generator */
SLOT->ssgn = (SLOT->ssg & 0x04) >> 1;
SLOT->state = EG_ATT;
}
@@ -936,13 +936,13 @@ static void setup_connection( FM_OPN *OPN, FM_CH *CH, int ch )
*om1 = &OPN->c1;
*oc1 = carrier;
*om2 = &OPN->c2;
- *memc= &OPN->mem; /* store it anywhere where it will not be used */
+ *memc= &OPN->mem; /* store it anywhere where it will not be used */
break;
case 5:
/* +----C1----+ */
/* M1-+-MEM---M2-+-OUT */
/* +----C2----+ */
- *om1 = 0; /* special mark */
+ *om1 = 0; /* special mark */
*oc1 = carrier;
*om2 = carrier;
*memc= &OPN->m2;
@@ -955,7 +955,7 @@ static void setup_connection( FM_OPN *OPN, FM_CH *CH, int ch )
*om1 = &OPN->c1;
*oc1 = carrier;
*om2 = carrier;
- *memc= &OPN->mem; /* store it anywhere where it will not be used */
+ *memc= &OPN->mem; /* store it anywhere where it will not be used */
break;
case 7:
/* M1-+ */
@@ -966,7 +966,7 @@ static void setup_connection( FM_OPN *OPN, FM_CH *CH, int ch )
*om1 = carrier;
*oc1 = carrier;
*om2 = carrier;
- *memc= &OPN->mem; /* store it anywhere where it will not be used */
+ *memc= &OPN->mem; /* store it anywhere where it will not be used */
break;
}
@@ -1071,7 +1071,7 @@ INLINE void advance_lfo(FM_OPN *OPN)
{
UINT8 pos;
- if (OPN->lfo_inc) /* LFO enabled ? */
+ if (OPN->lfo_inc) /* LFO enabled ? */
{
OPN->lfo_cnt += OPN->lfo_inc;
@@ -1081,7 +1081,7 @@ INLINE void advance_lfo(FM_OPN *OPN)
/* update AM when LFO output changes */
/* actually I can't optimize is this way without rewriting chan_calc()
- to use chip->lfo_am instead of global lfo_am */
+ to use chip->lfo_am instead of global lfo_am */
{
/* triangle */
@@ -1124,12 +1124,12 @@ static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
switch(SLOT->state)
{
- case EG_ATT: /* attack phase */
+ case EG_ATT: /* attack phase */
if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_ar)-1) ) )
{
SLOT->volume += (~SLOT->volume *
- (eg_inc[SLOT->eg_sel_ar + ((OPN->eg_cnt>>SLOT->eg_sh_ar)&7)])
- ) >>4;
+ (eg_inc[SLOT->eg_sel_ar + ((OPN->eg_cnt>>SLOT->eg_sh_ar)&7)])
+ ) >>4;
if (SLOT->volume <= MIN_ATT_INDEX)
{
@@ -1139,9 +1139,9 @@ static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
}
break;
- case EG_DEC: /* decay phase */
+ case EG_DEC: /* decay phase */
{
- if (SLOT->ssg&0x08) /* SSG EG type envelope selected */
+ if (SLOT->ssg&0x08) /* SSG EG type envelope selected */
{
if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_d1r)-1) ) )
{
@@ -1164,8 +1164,8 @@ static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
}
break;
- case EG_SUS: /* sustain phase */
- if (SLOT->ssg&0x08) /* SSG EG type envelope selected */
+ case EG_SUS: /* sustain phase */
+ if (SLOT->ssg&0x08) /* SSG EG type envelope selected */
{
if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_d2r)-1) ) )
{
@@ -1176,9 +1176,9 @@ static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
{
SLOT->volume = MAX_ATT_INDEX;
- if (SLOT->ssg&0x01) /* bit 0 = hold */
+ if (SLOT->ssg&0x01) /* bit 0 = hold */
{
- if (SLOT->ssgn&1) /* have we swapped once ??? */
+ if (SLOT->ssgn&1) /* have we swapped once ??? */
{
/* yes, so do nothing, just hold current level */
}
@@ -1220,7 +1220,7 @@ static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
}
break;
- case EG_REL: /* release phase */
+ case EG_REL: /* release phase */
if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_rr)-1) ) )
{
/* SSG-EG affects Release phase also (Nemesis) */
@@ -1239,15 +1239,15 @@ static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
out = ((UINT32)SLOT->volume);
- /* negate output (changes come from alternate bit, init comes from attack bit) */
+ /* negate output (changes come from alternate bit, init comes from attack bit) */
if ((SLOT->ssg&0x08) && (SLOT->ssgn&2) && (SLOT->state > EG_REL))
out ^= MAX_ATT_INDEX;
/* we need to store the result here because we are going to change ssgn
- in next instruction */
+ in next instruction */
SLOT->vol_out = out + SLOT->tl;
- /* reverse SLOT inversion flag */
+ /* reverse SLOT inversion flag */
SLOT->ssgn ^= swap_flag;
SLOT++;
@@ -1303,19 +1303,19 @@ INLINE void update_phase_lfo_channel(FM_OPN *OPN, FM_CH *CH)
if (lfo_fn_table_index_offset) /* LFO phase modulation active */
{
- UINT8 blk;
- UINT32 fn;
+ UINT8 blk;
+ UINT32 fn;
int kc, fc, finc;
block_fnum = block_fnum*2 + lfo_fn_table_index_offset;
- blk = (block_fnum&0x7000) >> 12;
- fn = block_fnum & 0xfff;
+ blk = (block_fnum&0x7000) >> 12;
+ fn = block_fnum & 0xfff;
/* keyscale code */
- kc = (blk<<2) | opn_fktable[fn >> 8];
+ kc = (blk<<2) | opn_fktable[fn >> 8];
- /* phase increment counter */
+ /* phase increment counter */
fc = (OPN->fn_table[fn]>>(7-blk));
/* detects frequency overflow (credits to Nemesis) */
@@ -1338,10 +1338,10 @@ INLINE void update_phase_lfo_channel(FM_OPN *OPN, FM_CH *CH)
}
else /* LFO phase modulation = zero */
{
- CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
- CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
- CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
- CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
+ CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
+ CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
+ CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
+ CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
}
}
@@ -1354,7 +1354,7 @@ INLINE void chan_calc(FM_OPN *OPN, FM_CH *CH, int chnum)
OPN->m2 = OPN->c1 = OPN->c2 = OPN->mem = 0;
- *CH->mem_connect = CH->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
+ *CH->mem_connect = CH->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
eg_out = volume_calc(&CH->SLOT[SLOT1]);
{
@@ -1373,7 +1373,7 @@ INLINE void chan_calc(FM_OPN *OPN, FM_CH *CH, int chnum)
}
CH->op1_out[1] = 0;
- if( eg_out < ENV_QUIET ) /* SLOT 1 */
+ if( eg_out < ENV_QUIET ) /* SLOT 1 */
{
if (!CH->FB)
out=0;
@@ -1383,15 +1383,15 @@ INLINE void chan_calc(FM_OPN *OPN, FM_CH *CH, int chnum)
}
eg_out = volume_calc(&CH->SLOT[SLOT3]);
- if( eg_out < ENV_QUIET ) /* SLOT 3 */
+ if( eg_out < ENV_QUIET ) /* SLOT 3 */
*CH->connect3 += op_calc(CH->SLOT[SLOT3].phase, eg_out, OPN->m2);
eg_out = volume_calc(&CH->SLOT[SLOT2]);
- if( eg_out < ENV_QUIET ) /* SLOT 2 */
+ if( eg_out < ENV_QUIET ) /* SLOT 2 */
*CH->connect2 += op_calc(CH->SLOT[SLOT2].phase, eg_out, OPN->c1);
eg_out = volume_calc(&CH->SLOT[SLOT4]);
- if( eg_out < ENV_QUIET ) /* SLOT 4 */
+ if( eg_out < ENV_QUIET ) /* SLOT 4 */
*CH->connect4 += op_calc(CH->SLOT[SLOT4].phase, eg_out, OPN->c2);
@@ -1404,14 +1404,14 @@ INLINE void chan_calc(FM_OPN *OPN, FM_CH *CH, int chnum)
/* add support for 3 slot mode */
if ((OPN->ST.mode & 0xC0) && (chnum == 2))
{
- update_phase_lfo_slot(OPN, &CH->SLOT[SLOT1], CH->pms, OPN->SL3.block_fnum[1]);
- update_phase_lfo_slot(OPN, &CH->SLOT[SLOT2], CH->pms, OPN->SL3.block_fnum[2]);
- update_phase_lfo_slot(OPN, &CH->SLOT[SLOT3], CH->pms, OPN->SL3.block_fnum[0]);
- update_phase_lfo_slot(OPN, &CH->SLOT[SLOT4], CH->pms, CH->block_fnum);
+ update_phase_lfo_slot(OPN, &CH->SLOT[SLOT1], CH->pms, OPN->SL3.block_fnum[1]);
+ update_phase_lfo_slot(OPN, &CH->SLOT[SLOT2], CH->pms, OPN->SL3.block_fnum[2]);
+ update_phase_lfo_slot(OPN, &CH->SLOT[SLOT3], CH->pms, OPN->SL3.block_fnum[0]);
+ update_phase_lfo_slot(OPN, &CH->SLOT[SLOT4], CH->pms, CH->block_fnum);
}
else update_phase_lfo_channel(OPN, CH);
}
- else /* no LFO phase modulation */
+ else /* no LFO phase modulation */
{
CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
@@ -1482,7 +1482,7 @@ static void init_timetables( FM_ST *ST , const UINT8 *dttable )
#if 0
logerror("FM.C: samplerate=%8i chip clock=%8i freqbase=%f \n",
- ST->rate, ST->clock, ST->freqbase );
+ ST->rate, ST->clock, ST->freqbase );
#endif
/* DeTune table */
@@ -1506,7 +1506,7 @@ static void reset_channels( FM_ST *ST , FM_CH *CH , int num )
{
int c,s;
- ST->mode = 0; /* normal mode */
+ ST->mode = 0; /* normal mode */
ST->TA = 0;
ST->TAC = 0;
ST->TB = 0;
@@ -1541,14 +1541,14 @@ static int init_tables(void)
/* we never reach (1<<16) here due to the (x+1) */
/* result fits within 16 bits at maximum */
- n = (int)m; /* 16 bits here */
- n >>= 4; /* 12 bits here */
- if (n&1) /* round to nearest */
+ n = (int)m; /* 16 bits here */
+ n >>= 4; /* 12 bits here */
+ if (n&1) /* round to nearest */
n = (n>>1)+1;
else
n = n>>1;
/* 11 bits here (rounded) */
- n <<= 2; /* 13 bits here (as in real chip) */
+ n <<= 2; /* 13 bits here (as in real chip) */
tl_tab[ x*2 + 0 ] = n;
tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
@@ -1575,14 +1575,14 @@ static int init_tables(void)
/* we never reach zero here due to ((i*2)+1) */
if (m>0.0)
- o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */
+ o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */
else
- o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
+ o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
o = o / (ENV_STEP/4);
n = (int)(2.0*o);
- if (n&1) /* round to nearest */
+ if (n&1) /* round to nearest */
n = (n>>1)+1;
else
n = n>>1;
@@ -1751,7 +1751,7 @@ static void OPNSetPres(FM_OPN *OPN, int pres, int timer_prescaler, int SSGpres)
init_timetables( &OPN->ST, dt_tab );
/* there are 2048 FNUMs that can be generated using FNUM/BLK registers
- but LFO works with one more bit of a precision so we really need 4096 elements */
+ but LFO works with one more bit of a precision so we really need 4096 elements */
/* calculate fnumber -> increment counter table */
for(i = 0; i < 4096; i++)
{
@@ -1760,7 +1760,7 @@ static void OPNSetPres(FM_OPN *OPN, int pres, int timer_prescaler, int SSGpres)
OPN->fn_table[i] = (UINT32)( (double)i * 32 * OPN->ST.freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
#if 0
logerror("FM.C: fn_table[%4i] = %08x (dec=%8i)\n",
- i, OPN->fn_table[i]>>6,OPN->fn_table[i]>>6 );
+ i, OPN->fn_table[i]>>6,OPN->fn_table[i]>>6 );
#endif
}
@@ -1775,7 +1775,7 @@ static void OPNSetPres(FM_OPN *OPN, int pres, int timer_prescaler, int SSGpres)
OPN->lfo_freq[i] = (1.0 / lfo_samples_per_step[i]) * (1<<LFO_SH) * OPN->ST.freqbase;
#if 0
logerror("FM.C: lfo_freq[%i] = %08x (dec=%8i)\n",
- i, OPN->lfo_freq[i],OPN->lfo_freq[i] );
+ i, OPN->lfo_freq[i],OPN->lfo_freq[i] );
#endif
}
}
@@ -1790,9 +1790,9 @@ static void OPNWriteMode(FM_OPN *OPN, int r, int v)
switch(r)
{
- case 0x21: /* Test */
+ case 0x21: /* Test */
break;
- case 0x22: /* LFO FREQ (YM2608/YM2610/YM2610B/YM2612) */
+ case 0x22: /* LFO FREQ (YM2608/YM2610/YM2610B/YM2612) */
if( OPN->type & TYPE_LFOPAN )
{
if (v&0x08) /* LFO enabled ? */
@@ -1805,19 +1805,19 @@ static void OPNWriteMode(FM_OPN *OPN, int r, int v)
}
}
break;
- case 0x24: /* timer A High 8*/
+ case 0x24: /* timer A High 8*/
OPN->ST.TA = (OPN->ST.TA & 0x03)|(((int)v)<<2);
break;
- case 0x25: /* timer A Low 2*/
+ case 0x25: /* timer A Low 2*/
OPN->ST.TA = (OPN->ST.TA & 0x3fc)|(v&3);
break;
- case 0x26: /* timer B */
+ case 0x26: /* timer B */
OPN->ST.TB = v;
break;
- case 0x27: /* mode, timer control */
+ case 0x27: /* mode, timer control */
set_timers( &(OPN->ST),OPN->ST.param,v );
break;
- case 0x28: /* key on / off */
+ case 0x28: /* key on / off */
c = v & 0x03;
if( c == 3 ) break;
if( (v&0x04) && (OPN->type & TYPE_6CH) ) c+=3;
@@ -1850,19 +1850,19 @@ static void OPNWriteReg(FM_OPN *OPN, int r, int v)
switch( r & 0xf0 )
{
- case 0x30: /* DET , MUL */
+ case 0x30: /* DET , MUL */
set_det_mul(&OPN->ST,CH,SLOT,v);
break;
- case 0x40: /* TL */
+ case 0x40: /* TL */
set_tl(CH,SLOT,v);
break;
- case 0x50: /* KS, AR */
+ case 0x50: /* KS, AR */
set_ar_ksr(OPN->type,CH,SLOT,v);
break;
- case 0x60: /* bit7 = AM ENABLE, DR */
+ case 0x60: /* bit7 = AM ENABLE, DR */
set_dr(OPN->type, SLOT,v);
if(OPN->type & TYPE_LFOPAN) /* YM2608/2610/2610B/2612 */
@@ -1871,91 +1871,91 @@ static void OPNWriteReg(FM_OPN *OPN, int r, int v)
}
break;
- case 0x70: /* SR */
+ case 0x70: /* SR */
set_sr(OPN->type,SLOT,v);
break;
- case 0x80: /* SL, RR */
+ case 0x80: /* SL, RR */
set_sl_rr(OPN->type,SLOT,v);
break;
- case 0x90: /* SSG-EG */
+ case 0x90: /* SSG-EG */
SLOT->ssg = v&0x0f;
SLOT->ssgn = (v&0x04)>>1; /* bit 1 in ssgn = attack */
/* SSG-EG envelope shapes :
- E AtAlH
- 1 0 0 0 \\\\
+ E AtAlH
+ 1 0 0 0 \\\\
- 1 0 0 1 \___
+ 1 0 0 1 \___
- 1 0 1 0 \/\/
- ___
- 1 0 1 1 \
+ 1 0 1 0 \/\/
+ ___
+ 1 0 1 1 \
- 1 1 0 0 ////
- ___
- 1 1 0 1 /
+ 1 1 0 0 ////
+ ___
+ 1 1 0 1 /
- 1 1 1 0 /\/\
+ 1 1 1 0 /\/\
- 1 1 1 1 /___
+ 1 1 1 1 /___
- E = SSG-EG enable
+ E = SSG-EG enable
- The shapes are generated using Attack, Decay and Sustain phases.
+ The shapes are generated using Attack, Decay and Sustain phases.
- Each single character in the diagrams above represents this whole
- sequence:
+ Each single character in the diagrams above represents this whole
+ sequence:
- - when KEY-ON = 1, normal Attack phase is generated (*without* any
- difference when compared to normal mode),
+ - when KEY-ON = 1, normal Attack phase is generated (*without* any
+ difference when compared to normal mode),
- - later, when envelope level reaches minimum level (max volume),
- the EG switches to Decay phase (which works with bigger steps
- when compared to normal mode - see below),
+ - later, when envelope level reaches minimum level (max volume),
+ the EG switches to Decay phase (which works with bigger steps
+ when compared to normal mode - see below),
- - later when envelope level passes the SL level,
- the EG swithes to Sustain phase (which works with bigger steps
- when compared to normal mode - see below),
+ - later when envelope level passes the SL level,
+ the EG swithes to Sustain phase (which works with bigger steps
+ when compared to normal mode - see below),
- - finally when envelope level reaches maximum level (min volume),
- the EG switches to Attack phase again (depends on actual waveform).
+ - finally when envelope level reaches maximum level (min volume),
+ the EG switches to Attack phase again (depends on actual waveform).
- Important is that when switch to Attack phase occurs, the phase counter
- of that operator will be zeroed-out (as in normal KEY-ON) but not always.
- (I havent found the rule for that - perhaps only when the output level is low)
+ Important is that when switch to Attack phase occurs, the phase counter
+ of that operator will be zeroed-out (as in normal KEY-ON) but not always.
+ (I havent found the rule for that - perhaps only when the output level is low)
- The difference (when compared to normal Envelope Generator mode) is
- that the resolution in Decay and Sustain phases is 4 times lower;
- this results in only 256 steps instead of normal 1024.
- In other words:
- when SSG-EG is disabled, the step inside of the EG is one,
- when SSG-EG is enabled, the step is four (in Decay and Sustain phases).
+ The difference (when compared to normal Envelope Generator mode) is
+ that the resolution in Decay and Sustain phases is 4 times lower;
+ this results in only 256 steps instead of normal 1024.
+ In other words:
+ when SSG-EG is disabled, the step inside of the EG is one,
+ when SSG-EG is enabled, the step is four (in Decay and Sustain phases).
- Times between the level changes are the same in both modes.
+ Times between the level changes are the same in both modes.
- Important:
- Decay 1 Level (so called SL) is compared to actual SSG-EG output, so
- it is the same in both SSG and no-SSG modes, with this exception:
+ Important:
+ Decay 1 Level (so called SL) is compared to actual SSG-EG output, so
+ it is the same in both SSG and no-SSG modes, with this exception:
- when the SSG-EG is enabled and is generating raising levels
- (when the EG output is inverted) the SL will be found at wrong level !!!
- For example, when SL=02:
- 0 -6 = -6dB in non-inverted EG output
- 96-6 = -90dB in inverted EG output
- Which means that EG compares its level to SL as usual, and that the
- output is simply inverted afterall.
+ when the SSG-EG is enabled and is generating raising levels
+ (when the EG output is inverted) the SL will be found at wrong level !!!
+ For example, when SL=02:
+ 0 -6 = -6dB in non-inverted EG output
+ 96-6 = -90dB in inverted EG output
+ Which means that EG compares its level to SL as usual, and that the
+ output is simply inverted afterall.
- The Yamaha's manuals say that AR should be set to 0x1f (max speed).
- That is not necessary, but then EG will be generating Attack phase.
+ The Yamaha's manuals say that AR should be set to 0x1f (max speed).
+ That is not necessary, but then EG will be generating Attack phase.
- */
+ */
break;
@@ -1963,7 +1963,7 @@ static void OPNWriteReg(FM_OPN *OPN, int r, int v)
case 0xa0:
switch( OPN_SLOT(r) )
{
- case 0: /* 0xa0-0xa2 : FNUM1 */
+ case 0: /* 0xa0-0xa2 : FNUM1 */
{
UINT32 fn = (((UINT32)( (OPN->ST.fn_h)&7))<<8) + v;
UINT8 blk = OPN->ST.fn_h>>3;
@@ -1978,10 +1978,10 @@ static void OPNWriteReg(FM_OPN *OPN, int r, int v)
CH->SLOT[SLOT1].Incr=-1;
}
break;
- case 1: /* 0xa4-0xa6 : FNUM2,BLK */
+ case 1: /* 0xa4-0xa6 : FNUM2,BLK */
OPN->ST.fn_h = v&0x3f;
break;
- case 2: /* 0xa8-0xaa : 3CH FNUM1 */
+ case 2: /* 0xa8-0xaa : 3CH FNUM1 */
if(r < 0x100)
{
UINT32 fn = (((UINT32)(OPN->SL3.fn_h&7))<<8) + v;
@@ -1994,7 +1994,7 @@ static void OPNWriteReg(FM_OPN *OPN, int r, int v)
(OPN->P_CH)[2].SLOT[SLOT1].Incr=-1;
}
break;
- case 3: /* 0xac-0xae : 3CH FNUM2,BLK */
+ case 3: /* 0xac-0xae : 3CH FNUM2,BLK */
if(r < 0x100)
OPN->SL3.fn_h = v&0x3f;
break;
@@ -2004,7 +2004,7 @@ static void OPNWriteReg(FM_OPN *OPN, int r, int v)
case 0xb0:
switch( OPN_SLOT(r) )
{
- case 0: /* 0xb0-0xb2 : FB,ALGO */
+ case 0: /* 0xb0-0xb2 : FB,ALGO */
{
int feedback = (v>>3)&7;
CH->ALGO = v&7;
@@ -2012,7 +2012,7 @@ static void OPNWriteReg(FM_OPN *OPN, int r, int v)
setup_connection( OPN, CH, c );
}
break;
- case 1: /* 0xb4-0xb6 : L , R , AMS , PMS (YM2612/YM2610B/YM2610/YM2608) */
+ case 1: /* 0xb4-0xb6 : L , R , AMS , PMS (YM2612/YM2610B/YM2610/YM2608) */
if( OPN->type & TYPE_LFOPAN)
{
/* b0-2 PMS */
@@ -2060,24 +2060,24 @@ static void OPNPrescaler_w(FM_OPN *OPN , int addr, int pre_divider)
switch(addr)
{
- case 0: /* when reset */
+ case 0: /* when reset */
OPN->ST.prescaler_sel = 2;
break;
- case 1: /* when postload */
+ case 1: /* when postload */
break;
- case 0x2d: /* divider sel : select 1/1 for 1/3line */
+ case 0x2d: /* divider sel : select 1/1 for 1/3line */
OPN->ST.prescaler_sel |= 0x02;
break;
- case 0x2e: /* divider sel , select 1/3line for output */
+ case 0x2e: /* divider sel , select 1/3line for output */
OPN->ST.prescaler_sel |= 0x01;
break;
- case 0x2f: /* divider sel , clear both selector to 1/2,1/2 */
+ case 0x2f: /* divider sel , clear both selector to 1/2,1/2 */
OPN->ST.prescaler_sel = 0;
break;
}
sel = OPN->ST.prescaler_sel & 3;
/* update prescaler */
- OPNSetPres( OPN, opn_pres[sel]*pre_divider,
+ OPNSetPres( OPN, opn_pres[sel]*pre_divider,
opn_pres[sel]*pre_divider,
ssg_pres[sel]*pre_divider );
}
@@ -2091,9 +2091,9 @@ static void OPNPrescaler_w(FM_OPN *OPN , int addr, int pre_divider)
/* here's the virtual YM2203(OPN) */
struct YM2203
{
- UINT8 REGS[256]; /* registers */
- FM_OPN OPN; /* OPN state */
- FM_CH CH[3]; /* channel state */
+ UINT8 REGS[256]; /* registers */
+ FM_OPN OPN; /* OPN state */
+ FM_CH CH[3]; /* channel state */
};
/* Generate samples for one of the YM2203s */
@@ -2103,7 +2103,7 @@ void ym2203_update_one(void *chip, FMSAMPLE *buffer, int length)
FM_OPN *OPN = &F2203->OPN;
int i;
FMSAMPLE *buf = buffer;
- FM_CH *cch[3];
+ FM_CH *cch[3];
cch[0] = &F2203->CH[0];
cch[1] = &F2203->CH[1];
@@ -2259,7 +2259,7 @@ static void YM2203_save_state(YM2203 *F2203, device_t *device)
'rate' is sampling rate
*/
void * ym2203_init(void *param, device_t *device, int clock, int rate,
- FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler, const ssg_callbacks *ssg)
+ FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler, const ssg_callbacks *ssg)
{
YM2203 *F2203;
@@ -2305,7 +2305,7 @@ int ym2203_write(void *chip,int a,UINT8 v)
FM_OPN *OPN = &F2203->OPN;
if( !(a&1) )
- { /* address port */
+ { /* address port */
OPN->ST.address = (v &= 0xff);
/* Write register to SSG emulator */
@@ -2316,21 +2316,21 @@ int ym2203_write(void *chip,int a,UINT8 v)
OPNPrescaler_w(OPN , v , 1);
}
else
- { /* data port */
+ { /* data port */
int addr = OPN->ST.address;
F2203->REGS[addr] = v;
switch( addr & 0xf0 )
{
- case 0x00: /* 0x00-0x0f : SSG section */
+ case 0x00: /* 0x00-0x0f : SSG section */
/* Write data to SSG emulator */
(*OPN->ST.SSG->write)(OPN->ST.param,a,v);
break;
- case 0x20: /* 0x20-0x2f : Mode section */
+ case 0x20: /* 0x20-0x2f : Mode section */
ym2203_update_req(OPN->ST.param);
/* write register */
OPNWriteMode(OPN,addr,v);
break;
- default: /* 0x30-0xff : OPN section */
+ default: /* 0x30-0xff : OPN section */
ym2203_update_req(OPN->ST.param);
/* write register */
OPNWriteReg(OPN,addr,v);
@@ -2347,11 +2347,11 @@ UINT8 ym2203_read(void *chip,int a)
UINT8 ret = 0;
if( !(a&1) )
- { /* status port */
+ { /* status port */
ret = FM_STATUS_FLAG(&F2203->OPN.ST);
}
else
- { /* data port (only SSG) */
+ { /* data port (only SSG) */
if( addr < 16 ) ret = (*F2203->OPN.ST.SSG->read)(F2203->OPN.ST.param);
}
return ret;
@@ -2362,17 +2362,17 @@ int ym2203_timer_over(void *chip,int c)
YM2203 *F2203 = (YM2203 *)chip;
if( c )
- { /* Timer B */
+ { /* Timer B */
TimerBOver( &(F2203->OPN.ST) );
}
else
- { /* Timer A */
+ { /* Timer A */
ym2203_update_req(F2203->OPN.ST.param);
/* timer update */
TimerAOver( &(F2203->OPN.ST) );
/* CSM mode key,TL control */
if( F2203->OPN.ST.mode & 0x80 )
- { /* CSM mode auto key on */
+ { /* CSM mode auto key on */
CSMKeyControll( F2203->OPN.type, &(F2203->CH[2]) );
}
}
@@ -2387,42 +2387,42 @@ int ym2203_timer_over(void *chip,int c)
/* ADPCM type A channel struct */
struct ADPCM_CH
{
- UINT8 flag; /* port state */
- UINT8 flagMask; /* arrived flag mask */
- UINT8 now_data; /* current ROM data */
- UINT32 now_addr; /* current ROM address */
- UINT32 now_step;
- UINT32 step;
- UINT32 start; /* sample data start address*/
- UINT32 end; /* sample data end address */
- UINT8 IL; /* Instrument Level */
- INT32 adpcm_acc; /* accumulator */
- INT32 adpcm_step; /* step */
- INT32 adpcm_out; /* (speedup) hiro-shi!! */
- INT8 vol_mul; /* volume in "0.75dB" steps */
- UINT8 vol_shift; /* volume in "-6dB" steps */
- INT32 *pan; /* &out_adpcm[OPN_xxxx] */
+ UINT8 flag; /* port state */
+ UINT8 flagMask; /* arrived flag mask */
+ UINT8 now_data; /* current ROM data */
+ UINT32 now_addr; /* current ROM address */
+ UINT32 now_step;
+ UINT32 step;
+ UINT32 start; /* sample data start address*/
+ UINT32 end; /* sample data end address */
+ UINT8 IL; /* Instrument Level */
+ INT32 adpcm_acc; /* accumulator */
+ INT32 adpcm_step; /* step */
+ INT32 adpcm_out; /* (speedup) hiro-shi!! */
+ INT8 vol_mul; /* volume in "0.75dB" steps */
+ UINT8 vol_shift; /* volume in "-6dB" steps */
+ INT32 *pan; /* &out_adpcm[OPN_xxxx] */
};
/* here's the virtual YM2610 */
struct YM2610
{
- UINT8 REGS[512]; /* registers */
- FM_OPN OPN; /* OPN state */
- FM_CH CH[6]; /* channel state */
- UINT8 addr_A1; /* address line A1 */
+ UINT8 REGS[512]; /* registers */
+ FM_OPN OPN; /* OPN state */
+ FM_CH CH[6]; /* channel state */
+ UINT8 addr_A1; /* address line A1 */
/* ADPCM-A unit */
- const UINT8 *pcmbuf; /* pcm rom buffer */
- UINT32 pcm_size; /* size of pcm rom */
- UINT8 adpcmTL; /* adpcmA total level */
- ADPCM_CH adpcm[6]; /* adpcm channels */
- UINT32 adpcmreg[0x30]; /* registers */
- UINT8 adpcm_arrivedEndAddress;
- YM_DELTAT deltaT; /* Delta-T ADPCM unit */
-
- UINT8 flagmask; /* YM2608 only */
- UINT8 irqmask; /* YM2608 only */
+ const UINT8 *pcmbuf; /* pcm rom buffer */
+ UINT32 pcm_size; /* size of pcm rom */
+ UINT8 adpcmTL; /* adpcmA total level */
+ ADPCM_CH adpcm[6]; /* adpcm channels */
+ UINT32 adpcmreg[0x30]; /* registers */
+ UINT8 adpcm_arrivedEndAddress;
+ YM_DELTAT deltaT; /* Delta-T ADPCM unit */
+
+ UINT8 flagmask; /* YM2608 only */
+ UINT8 irqmask; /* YM2608 only */
};
/* here is the virtual YM2608 */
@@ -2438,9 +2438,9 @@ typedef YM2610 YM2608;
/* usual ADPCM table (16 * 1.1^N) */
static const int steps[49] =
{
- 16, 17, 19, 21, 23, 25, 28,
- 31, 34, 37, 41, 45, 50, 55,
- 60, 66, 73, 80, 88, 97, 107,
+ 16, 17, 19, 21, 23, 25, 28,
+ 31, 34, 37, 41, 45, 50, 55,
+ 60, 66, 73, 80, 88, 97, 107,
118, 130, 143, 157, 173, 190, 209,
230, 253, 279, 307, 337, 371, 408,
449, 494, 544, 598, 658, 724, 796,
@@ -2487,7 +2487,7 @@ INLINE void ADPCMA_calc_chan( YM2610 *F2610, ADPCM_CH *ch )
/* YM2610 checks lower 20 bits only, the 4 MSB bits are sample bank */
/* Here we use 1<<21 to compensate for nibble calculations */
- if ( (ch->now_addr & ((1<<21)-1)) == ((ch->end<<1) & ((1<<21)-1)) )
+ if ( (ch->now_addr & ((1<<21)-1)) == ((ch->end<<1) & ((1<<21)-1)) )
{
ch->flag = 0;
F2610->adpcm_arrivedEndAddress |= ch->flagMask;
@@ -2524,7 +2524,7 @@ INLINE void ADPCMA_calc_chan( YM2610 *F2610, ADPCM_CH *ch )
}while(--step);
/* calc pcm * volume data */
- ch->adpcm_out = ((ch->adpcm_acc * ch->vol_mul) >> ch->vol_shift) & ~3; /* multiply, shift and mask out 2 LSB bits */
+ ch->adpcm_out = ((ch->adpcm_acc * ch->vol_mul) >> ch->vol_shift) & ~3; /* multiply, shift and mask out 2 LSB bits */
}
/* output for work of output channels (out_adpcm[OPNxxxx])*/
@@ -2558,18 +2558,18 @@ static void FM_ADPCMAWrite(YM2610 *F2610,int r,int v)
adpcm[c].flag = 1;
if(F2610->pcmbuf==NULL)
- { /* Check ROM Mapped */
+ { /* Check ROM Mapped */
logerror("YM2608-YM2610: ADPCM-A rom not mapped\n");
adpcm[c].flag = 0;
}
else
{
if(adpcm[c].end >= F2610->pcm_size)
- { /* Check End in Range */
+ { /* Check End in Range */
logerror("YM2610: ADPCM-A end out of range: $%08x\n",adpcm[c].end);
/*adpcm[c].end = F2610->pcm_size-1;*/ /* JB: DO NOT uncomment this, otherwise you will break the comparison in the ADPCM_CALC_CHA() */
}
- if(adpcm[c].start >= F2610->pcm_size) /* Check Start in Range */
+ if(adpcm[c].start >= F2610->pcm_size) /* Check Start in Range */
{
logerror("YM2608-YM2610: ADPCM-A start out of range: $%08x\n",adpcm[c].start);
adpcm[c].flag = 0;
@@ -2586,25 +2586,25 @@ static void FM_ADPCMAWrite(YM2610 *F2610,int r,int v)
adpcm[c].flag = 0;
}
break;
- case 0x01: /* B0-5 = TL */
+ case 0x01: /* B0-5 = TL */
F2610->adpcmTL = (v & 0x3f) ^ 0x3f;
for( c = 0; c < 6; c++ )
{
int volume = F2610->adpcmTL + adpcm[c].IL;
- if ( volume >= 63 ) /* This is correct, 63 = quiet */
+ if ( volume >= 63 ) /* This is correct, 63 = quiet */
{
adpcm[c].vol_mul = 0;
adpcm[c].vol_shift = 0;
}
else
{
- adpcm[c].vol_mul = 15 - (volume & 7); /* so called 0.75 dB */
- adpcm[c].vol_shift = 1 + (volume >> 3); /* Yamaha engineers used the approximation: each -6 dB is close to divide by two (shift right) */
+ adpcm[c].vol_mul = 15 - (volume & 7); /* so called 0.75 dB */
+ adpcm[c].vol_shift = 1 + (volume >> 3); /* Yamaha engineers used the approximation: each -6 dB is close to divide by two (shift right) */
}
/* calc pcm * volume data */
- adpcm[c].adpcm_out = ((adpcm[c].adpcm_acc * adpcm[c].vol_mul) >> adpcm[c].vol_shift) & ~3; /* multiply, shift and mask out low 2 bits */
+ adpcm[c].adpcm_out = ((adpcm[c].adpcm_acc * adpcm[c].vol_mul) >> adpcm[c].vol_shift) & ~3; /* multiply, shift and mask out low 2 bits */
}
break;
default:
@@ -2612,7 +2612,7 @@ static void FM_ADPCMAWrite(YM2610 *F2610,int r,int v)
if( c >= 0x06 ) return;
switch( r&0x38 )
{
- case 0x08: /* B7=L,B6=R, B4-0=IL */
+ case 0x08: /* B7=L,B6=R, B4-0=IL */
{
int volume;
@@ -2620,21 +2620,21 @@ static void FM_ADPCMAWrite(YM2610 *F2610,int r,int v)
volume = F2610->adpcmTL + adpcm[c].IL;
- if ( volume >= 63 ) /* This is correct, 63 = quiet */
+ if ( volume >= 63 ) /* This is correct, 63 = quiet */
{
adpcm[c].vol_mul = 0;
adpcm[c].vol_shift = 0;
}
else
{
- adpcm[c].vol_mul = 15 - (volume & 7); /* so called 0.75 dB */
- adpcm[c].vol_shift = 1 + (volume >> 3); /* Yamaha engineers used the approximation: each -6 dB is close to divide by two (shift right) */
+ adpcm[c].vol_mul = 15 - (volume & 7); /* so called 0.75 dB */
+ adpcm[c].vol_shift = 1 + (volume >> 3); /* Yamaha engineers used the approximation: each -6 dB is close to divide by two (shift right) */
}
adpcm[c].pan = &F2610->OPN.out_adpcm[(v>>6)&0x03];
/* calc pcm * volume data */
- adpcm[c].adpcm_out = ((adpcm[c].adpcm_acc * adpcm[c].vol_mul) >> adpcm[c].vol_shift) & ~3; /* multiply, shift and mask out low 2 bits */
+ adpcm[c].adpcm_out = ((adpcm[c].adpcm_acc * adpcm[c].vol_mul) >> adpcm[c].vol_shift) & ~3; /* multiply, shift and mask out low 2 bits */
}
break;
case 0x10:
@@ -3239,11 +3239,11 @@ static const unsigned char YM2608_ADPCM_ROM[0x2000] = {
INLINE void YM2608IRQFlagWrite(FM_OPN *OPN, YM2608 *F2608, int v)
{
if( v & 0x80 )
- { /* Reset IRQ flag */
+ { /* Reset IRQ flag */
FM_STATUS_RESET(&OPN->ST, 0xf7); /* don't touch BUFRDY flag otherwise we'd have to call ymdeltat module to set the flag back */
}
else
- { /* Set status flag mask */
+ { /* Set status flag mask */
F2608->flagmask = (~(v&0x1f));
FM_IRQMASK_SET(&OPN->ST, (F2608->irqmask & F2608->flagmask) );
}
@@ -3256,9 +3256,9 @@ INLINE void YM2608IRQMaskWrite(FM_OPN *OPN, YM2608 *F2608, int v)
/* extend 3ch. enable/disable */
if(v&0x80)
- OPN->type |= TYPE_6CH; /* OPNA mode - 6 FM channels */
+ OPN->type |= TYPE_6CH; /* OPNA mode - 6 FM channels */
else
- OPN->type &= ~TYPE_6CH; /* OPN mode - 3 FM channels */
+ OPN->type &= ~TYPE_6CH; /* OPN mode - 3 FM channels */
/* IRQ MASK store and set */
F2608->irqmask = v&0x1f;
@@ -3273,7 +3273,7 @@ void ym2608_update_one(void *chip, FMSAMPLE **buffer, int length)
YM_DELTAT *DELTAT = &F2608->deltaT;
int i,j;
FMSAMPLE *bufL,*bufR;
- FM_CH *cch[6];
+ FM_CH *cch[6];
INT32 *out_fm = OPN->out_fm;
/* set bufer */
@@ -3367,7 +3367,7 @@ void ym2608_update_one(void *chip, FMSAMPLE **buffer, int length)
rt = OPN->out_adpcm[OUTD_RIGHT] + OPN->out_adpcm[OUTD_CENTER];
lt += (OPN->out_delta[OUTD_LEFT] + OPN->out_delta[OUTD_CENTER])>>9;
rt += (OPN->out_delta[OUTD_RIGHT] + OPN->out_delta[OUTD_CENTER])>>9;
- lt += ((out_fm[0]>>1) & OPN->pan[0]); /* shift right verified on real YM2608 */
+ lt += ((out_fm[0]>>1) & OPN->pan[0]); /* shift right verified on real YM2608 */
rt += ((out_fm[0]>>1) & OPN->pan[1]);
lt += ((out_fm[1]>>1) & OPN->pan[2]);
rt += ((out_fm[1]>>1) & OPN->pan[3]);
@@ -3481,8 +3481,8 @@ static void YM2608_deltat_status_reset(void *chip, UINT8 changebits)
}
/* YM2608(OPNA) */
void * ym2608_init(void *param, device_t *device, int clock, int rate,
- void *pcmrom,int pcmsize,
- FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler, const ssg_callbacks *ssg)
+ void *pcmrom,int pcmsize,
+ FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler, const ssg_callbacks *ssg)
{
YM2608 *F2608;
@@ -3511,15 +3511,15 @@ void * ym2608_init(void *param, device_t *device, int clock, int rate,
F2608->deltaT.memory = (UINT8 *)pcmrom;
F2608->deltaT.memory_size = pcmsize;
- /*F2608->deltaT.write_time = 20.0 / clock;*/ /* a single byte write takes 20 cycles of main clock */
- /*F2608->deltaT.read_time = 18.0 / clock;*/ /* a single byte read takes 18 cycles of main clock */
+ /*F2608->deltaT.write_time = 20.0 / clock;*/ /* a single byte write takes 20 cycles of main clock */
+ /*F2608->deltaT.read_time = 18.0 / clock;*/ /* a single byte read takes 18 cycles of main clock */
F2608->deltaT.status_set_handler = YM2608_deltat_status_set;
F2608->deltaT.status_reset_handler = YM2608_deltat_status_reset;
F2608->deltaT.status_change_which_chip = F2608;
- F2608->deltaT.status_change_EOS_bit = 0x04; /* status flag: set bit2 on End Of Sample */
- F2608->deltaT.status_change_BRDY_bit = 0x08; /* status flag: set bit3 on BRDY */
- F2608->deltaT.status_change_ZERO_bit = 0x10; /* status flag: set bit4 if silence continues for more than 290 miliseconds while recording the ADPCM */
+ F2608->deltaT.status_change_EOS_bit = 0x04; /* status flag: set bit2 on End Of Sample */
+ F2608->deltaT.status_change_BRDY_bit = 0x08; /* status flag: set bit3 on BRDY */
+ F2608->deltaT.status_change_ZERO_bit = 0x10; /* status flag: set bit4 if silence continues for more than 290 miliseconds while recording the ADPCM */
/* ADPCM Rhythm */
F2608->pcmbuf = YM2608_ADPCM_ROM;
@@ -3560,13 +3560,13 @@ void ym2608_reset_chip(void *chip)
FM_BUSY_CLEAR(&OPN->ST);
/* register 0x29 - default value after reset is:
- enable only 3 FM channels and enable all the status flags */
- YM2608IRQMaskWrite(OPN, F2608, 0x1f ); /* default value for D4-D0 is 1 */
+ enable only 3 FM channels and enable all the status flags */
+ YM2608IRQMaskWrite(OPN, F2608, 0x1f ); /* default value for D4-D0 is 1 */
/* register 0x10, A1=1 - default value is 1 for D4, D3, D2, 0 for the rest */
- YM2608IRQFlagWrite(OPN, F2608, 0x1c ); /* default: enable timer A and B, disable EOS, BRDY and ZERO */
+ YM2608IRQFlagWrite(OPN, F2608, 0x1c ); /* default: enable timer A and B, disable EOS, BRDY and ZERO */
- OPNWriteMode(OPN,0x27,0x30); /* mode 0 , timer reset */
+ OPNWriteMode(OPN,0x27,0x30); /* mode 0 , timer reset */
OPN->eg_timer = 0;
OPN->eg_cnt = 0;
@@ -3590,9 +3590,9 @@ void ym2608_reset_chip(void *chip)
/* ADPCM - percussion sounds */
for( i = 0; i < 6; i++ )
{
- if (i<=3) /* channels 0,1,2,3 */
+ if (i<=3) /* channels 0,1,2,3 */
F2608->adpcm[i].step = (UINT32)((float)(1<<ADPCM_SHIFT)*((float)F2608->OPN.ST.freqbase)/3.0);
- else /* channels 4 and 5 work with slower clock */
+ else /* channels 4 and 5 work with slower clock */
F2608->adpcm[i].step = (UINT32)((float)(1<<ADPCM_SHIFT)*((float)F2608->OPN.ST.freqbase)/6.0);
F2608->adpcm[i].start = YM2608_ADPCM_ROM_addr[i*2];
@@ -3616,7 +3616,7 @@ void ym2608_reset_chip(void *chip)
/* DELTA-T unit */
DELTAT->freqbase = OPN->ST.freqbase;
DELTAT->output_pointer = OPN->out_delta;
- DELTAT->portshift = 5; /* always 5bits shift */ /* ASG */
+ DELTAT->portshift = 5; /* always 5bits shift */ /* ASG */
DELTAT->output_range = 1<<23;
YM_DELTAT_ADPCM_Reset(DELTAT,OUTD_CENTER,YM_DELTAT_EMULATION_MODE_NORMAL);
}
@@ -3631,12 +3631,12 @@ int ym2608_write(void *chip, int a,UINT8 v)
FM_OPN *OPN = &F2608->OPN;
int addr;
- v &= 0xff; /*adjust to 8 bit bus */
+ v &= 0xff; /*adjust to 8 bit bus */
switch(a&3)
{
- case 0: /* address port 0 */
+ case 0: /* address port 0 */
OPN->ST.address = v;
F2608->addr_A1 = 0;
@@ -3650,26 +3650,26 @@ int ym2608_write(void *chip, int a,UINT8 v)
}
break;
- case 1: /* data port 0 */
+ case 1: /* data port 0 */
if (F2608->addr_A1 != 0)
- break; /* verified on real YM2608 */
+ break; /* verified on real YM2608 */
addr = OPN->ST.address;
F2608->REGS[addr] = v;
switch(addr & 0xf0)
{
- case 0x00: /* SSG section */
+ case 0x00: /* SSG section */
/* Write data to SSG emulator */
(*OPN->ST.SSG->write)(OPN->ST.param,a,v);
break;
- case 0x10: /* 0x10-0x1f : Rhythm section */
+ case 0x10: /* 0x10-0x1f : Rhythm section */
ym2608_update_req(OPN->ST.param);
FM_ADPCMAWrite(F2608,addr-0x10,v);
break;
- case 0x20: /* Mode Register */
+ case 0x20: /* Mode Register */
switch(addr)
{
- case 0x29: /* SCH,xx,xxx,EN_ZERO,EN_BRDY,EN_EOS,EN_TB,EN_TA */
+ case 0x29: /* SCH,xx,xxx,EN_ZERO,EN_BRDY,EN_EOS,EN_TB,EN_TA */
YM2608IRQMaskWrite(OPN, F2608, v);
break;
default:
@@ -3677,30 +3677,30 @@ int ym2608_write(void *chip, int a,UINT8 v)
OPNWriteMode(OPN,addr,v);
}
break;
- default: /* OPN section */
+ default: /* OPN section */
ym2608_update_req(OPN->ST.param);
OPNWriteReg(OPN,addr,v);
}
break;
- case 2: /* address port 1 */
+ case 2: /* address port 1 */
OPN->ST.address = v;
F2608->addr_A1 = 1;
break;
- case 3: /* data port 1 */
+ case 3: /* data port 1 */
if (F2608->addr_A1 != 1)
- break; /* verified on real YM2608 */
+ break; /* verified on real YM2608 */
addr = OPN->ST.address;
F2608->REGS[addr | 0x100] = v;
ym2608_update_req(OPN->ST.param);
switch( addr & 0xf0 )
{
- case 0x00: /* DELTAT PORT */
+ case 0x00: /* DELTAT PORT */
switch( addr )
{
- case 0x0e: /* DAC data */
+ case 0x0e: /* DAC data */
logerror("YM2608: write to DAC data (unimplemented) value=%02x\n",v);
break;
default:
@@ -3708,7 +3708,7 @@ int ym2608_write(void *chip, int a,UINT8 v)
YM_DELTAT_ADPCM_Write(&F2608->deltaT,addr,v);
}
break;
- case 0x10: /* IRQ Flag control */
+ case 0x10: /* IRQ Flag control */
if( addr == 0x10 )
{
YM2608IRQFlagWrite(OPN, F2608, v);
@@ -3729,17 +3729,17 @@ UINT8 ym2608_read(void *chip,int a)
switch( a&3 )
{
- case 0: /* status 0 : YM2203 compatible */
+ case 0: /* status 0 : YM2203 compatible */
/* BUSY:x:x:x:x:x:FLAGB:FLAGA */
ret = FM_STATUS_FLAG(&F2608->OPN.ST) & 0x83;
break;
- case 1: /* status 0, ID */
+ case 1: /* status 0, ID */
if( addr < 16 ) ret = (*F2608->OPN.ST.SSG->read)(F2608->OPN.ST.param);
else if(addr == 0xff) ret = 0x01; /* ID code */
break;
- case 2: /* status 1 : status 0 + ADPCM status */
+ case 2: /* status 1 : status 0 + ADPCM status */
/* BUSY : x : PCMBUSY : ZERO : BRDY : EOS : FLAGB : FLAGA */
ret = (FM_STATUS_FLAG(&F2608->OPN.ST) & (F2608->flagmask|0x80)) | ((F2608->deltaT.PCM_BSY & 1)<<5) ;
break;
@@ -3766,35 +3766,35 @@ int ym2608_timer_over(void *chip,int c)
{
YM2608 *F2608 = (YM2608 *)chip;
- switch(c)
+ switch(c)
{
#if 0
case 2:
- { /* BUFRDY flag */
+ { /* BUFRDY flag */
YM_DELTAT_BRDY_callback( &F2608->deltaT );
}
break;
#endif
case 1:
- { /* Timer B */
+ { /* Timer B */
TimerBOver( &(F2608->OPN.ST) );
}
break;
case 0:
- { /* Timer A */
+ { /* Timer A */
ym2608_update_req(F2608->OPN.ST.param);
/* timer update */
TimerAOver( &(F2608->OPN.ST) );
/* CSM mode key,TL controll */
if( F2608->OPN.ST.mode & 0x80 )
- { /* CSM mode total level latch and auto key on */
+ { /* CSM mode total level latch and auto key on */
CSMKeyControll( F2608->OPN.type, &(F2608->CH[2]) );
}
}
break;
default:
break;
- }
+ }
return F2608->OPN.ST.irq;
}
@@ -3814,7 +3814,7 @@ void ym2610_update_one(void *chip, FMSAMPLE **buffer, int length)
YM_DELTAT *DELTAT = &F2610->deltaT;
int i,j;
FMSAMPLE *bufL,*bufR;
- FM_CH *cch[4];
+ FM_CH *cch[4];
INT32 *out_fm = OPN->out_fm;
/* buffer setup */
@@ -3883,10 +3883,10 @@ void ym2610_update_one(void *chip, FMSAMPLE **buffer, int length)
}
/* calculate FM */
- chan_calc(OPN, cch[0], 1 ); /*remapped to 1*/
- chan_calc(OPN, cch[1], 2 ); /*remapped to 2*/
- chan_calc(OPN, cch[2], 4 ); /*remapped to 4*/
- chan_calc(OPN, cch[3], 5 ); /*remapped to 5*/
+ chan_calc(OPN, cch[0], 1 ); /*remapped to 1*/
+ chan_calc(OPN, cch[1], 2 ); /*remapped to 2*/
+ chan_calc(OPN, cch[2], 4 ); /*remapped to 4*/
+ chan_calc(OPN, cch[3], 5 ); /*remapped to 5*/
/* deltaT ADPCM */
if( DELTAT->portstate&0x80 )
@@ -3909,7 +3909,7 @@ void ym2610_update_one(void *chip, FMSAMPLE **buffer, int length)
rt += (OPN->out_delta[OUTD_RIGHT] + OPN->out_delta[OUTD_CENTER])>>9;
- lt += ((out_fm[1]>>1) & OPN->pan[2]); /* the shift right was verified on real chip */
+ lt += ((out_fm[1]>>1) & OPN->pan[2]); /* the shift right was verified on real chip */
rt += ((out_fm[1]>>1) & OPN->pan[3]);
lt += ((out_fm[2]>>1) & OPN->pan[4]);
rt += ((out_fm[2]>>1) & OPN->pan[5]);
@@ -3951,7 +3951,7 @@ void ym2610b_update_one(void *chip, FMSAMPLE **buffer, int length)
YM_DELTAT *DELTAT = &F2610->deltaT;
int i,j;
FMSAMPLE *bufL,*bufR;
- FM_CH *cch[6];
+ FM_CH *cch[6];
INT32 *out_fm = OPN->out_fm;
/* buffer setup */
@@ -4045,7 +4045,7 @@ void ym2610b_update_one(void *chip, FMSAMPLE **buffer, int length)
lt += (OPN->out_delta[OUTD_LEFT] + OPN->out_delta[OUTD_CENTER])>>9;
rt += (OPN->out_delta[OUTD_RIGHT] + OPN->out_delta[OUTD_CENTER])>>9;
- lt += ((out_fm[0]>>1) & OPN->pan[0]); /* the shift right is verified on YM2610 */
+ lt += ((out_fm[0]>>1) & OPN->pan[0]); /* the shift right is verified on YM2610 */
rt += ((out_fm[0]>>1) & OPN->pan[1]);
lt += ((out_fm[1]>>1) & OPN->pan[2]);
rt += ((out_fm[1]>>1) & OPN->pan[3]);
@@ -4163,8 +4163,8 @@ static void YM2610_deltat_status_reset(void *chip, UINT8 changebits)
}
void *ym2610_init(void *param, device_t *device, int clock, int rate,
- void *pcmroma,int pcmsizea,void *pcmromb,int pcmsizeb,
- FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler, const ssg_callbacks *ssg)
+ void *pcmroma,int pcmsizea,void *pcmromb,int pcmsizeb,
+ FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler, const ssg_callbacks *ssg)
{
YM2610 *F2610;
@@ -4199,7 +4199,7 @@ void *ym2610_init(void *param, device_t *device, int clock, int rate,
F2610->deltaT.status_set_handler = YM2610_deltat_status_set;
F2610->deltaT.status_reset_handler = YM2610_deltat_status_reset;
F2610->deltaT.status_change_which_chip = F2610;
- F2610->deltaT.status_change_EOS_bit = 0x80; /* status flag: set bit7 on End Of Sample */
+ F2610->deltaT.status_change_EOS_bit = 0x80; /* status flag: set bit7 on End Of Sample */
Init_ADPCMATable();
#ifdef __SAVE_H__
@@ -4293,7 +4293,7 @@ void ym2610_reset_chip(void *chip)
/* DELTA-T unit */
DELTAT->freqbase = OPN->ST.freqbase;
DELTAT->output_pointer = OPN->out_delta;
- DELTAT->portshift = 8; /* allways 8bits shift */
+ DELTAT->portshift = 8; /* allways 8bits shift */
DELTAT->output_range = 1<<23;
YM_DELTAT_ADPCM_Reset(DELTAT,OUTD_CENTER,YM_DELTAT_EMULATION_MODE_YM2610);
}
@@ -4309,11 +4309,11 @@ int ym2610_write(void *chip, int a, UINT8 v)
int addr;
int ch;
- v &= 0xff; /* adjust to 8 bit bus */
+ v &= 0xff; /* adjust to 8 bit bus */
switch( a&3 )
{
- case 0: /* address port 0 */
+ case 0: /* address port 0 */
OPN->ST.address = v;
F2610->addr_A1 = 0;
@@ -4321,15 +4321,15 @@ int ym2610_write(void *chip, int a, UINT8 v)
if( v < 16 ) (*OPN->ST.SSG->write)(OPN->ST.param,0,v);
break;
- case 1: /* data port 0 */
+ case 1: /* data port 0 */
if (F2610->addr_A1 != 0)
- break; /* verified on real YM2608 */
+ break; /* verified on real YM2608 */
addr = OPN->ST.address;
F2610->REGS[addr] = v;
switch(addr & 0xf0)
{
- case 0x00: /* SSG section */
+ case 0x00: /* SSG section */
/* Write data to SSG emulator */
(*OPN->ST.SSG->write)(OPN->ST.param,a,v);
break;
@@ -4338,16 +4338,16 @@ int ym2610_write(void *chip, int a, UINT8 v)
switch(addr)
{
- case 0x10: /* control 1 */
- case 0x11: /* control 2 */
- case 0x12: /* start address L */
- case 0x13: /* start address H */
- case 0x14: /* stop address L */
- case 0x15: /* stop address H */
-
- case 0x19: /* delta-n L */
- case 0x1a: /* delta-n H */
- case 0x1b: /* volume */
+ case 0x10: /* control 1 */
+ case 0x11: /* control 2 */
+ case 0x12: /* start address L */
+ case 0x13: /* start address H */
+ case 0x14: /* stop address L */
+ case 0x15: /* stop address H */
+
+ case 0x19: /* delta-n L */
+ case 0x1a: /* delta-n H */
+ case 0x1b: /* volume */
{
YM_DELTAT_ADPCM_Write(&F2610->deltaT,addr-0x10,v);
}
@@ -4360,7 +4360,7 @@ int ym2610_write(void *chip, int a, UINT8 v)
for(ch=0;ch<6;ch++)
F2610->adpcm[ch].flagMask = statusmask&(1<<ch);
- F2610->deltaT.status_change_EOS_bit = statusmask & 0x80; /* status flag: set bit7 on End Of Sample */
+ F2610->deltaT.status_change_EOS_bit = statusmask & 0x80; /* status flag: set bit7 on End Of Sample */
/* clear arrived flag */
F2610->adpcm_arrivedEndAddress &= statusmask;
@@ -4373,25 +4373,25 @@ int ym2610_write(void *chip, int a, UINT8 v)
}
break;
- case 0x20: /* Mode Register */
+ case 0x20: /* Mode Register */
ym2610_update_req(OPN->ST.param);
OPNWriteMode(OPN,addr,v);
break;
- default: /* OPN section */
+ default: /* OPN section */
ym2610_update_req(OPN->ST.param);
/* write register */
OPNWriteReg(OPN,addr,v);
}
break;
- case 2: /* address port 1 */
+ case 2: /* address port 1 */
OPN->ST.address = v;
F2610->addr_A1 = 1;
break;
- case 3: /* data port 1 */
+ case 3: /* data port 1 */
if (F2610->addr_A1 != 1)
- break; /* verified on real YM2608 */
+ break; /* verified on real YM2608 */
ym2610_update_req(OPN->ST.param);
addr = OPN->ST.address;
@@ -4413,14 +4413,14 @@ UINT8 ym2610_read(void *chip,int a)
switch( a&3)
{
- case 0: /* status 0 : YM2203 compatible */
+ case 0: /* status 0 : YM2203 compatible */
ret = FM_STATUS_FLAG(&F2610->OPN.ST) & 0x83;
break;
- case 1: /* data 0 */
+ case 1: /* data 0 */
if( addr < 16 ) ret = (*F2610->OPN.ST.SSG->read)(F2610->OPN.ST.param);
if( addr == 0xff ) ret = 0x01;
break;
- case 2: /* status 1 : ADPCM status */
+ case 2: /* status 1 : ADPCM status */
/* ADPCM STATUS (arrived End Address) */
/* B,--,A5,A4,A3,A2,A1,A0 */
/* B = ADPCM-B(DELTA-T) arrived end address */
@@ -4439,17 +4439,17 @@ int ym2610_timer_over(void *chip,int c)
YM2610 *F2610 = (YM2610 *)chip;
if( c )
- { /* Timer B */
+ { /* Timer B */
TimerBOver( &(F2610->OPN.ST) );
}
else
- { /* Timer A */
+ { /* Timer A */
ym2610_update_req(F2610->OPN.ST.param);
/* timer update */
TimerAOver( &(F2610->OPN.ST) );
/* CSM mode key,TL controll */
if( F2610->OPN.ST.mode & 0x80 )
- { /* CSM mode total level latch and auto key on */
+ { /* CSM mode total level latch and auto key on */
CSMKeyControll( F2610->OPN.type, &(F2610->CH[2]) );
}
}