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Diffstat (limited to 'src/emu/machine/z80sio.c')
-rw-r--r--src/emu/machine/z80sio.c210
1 files changed, 105 insertions, 105 deletions
diff --git a/src/emu/machine/z80sio.c b/src/emu/machine/z80sio.c
index 616b0a61aae..f254963e16d 100644
--- a/src/emu/machine/z80sio.c
+++ b/src/emu/machine/z80sio.c
@@ -21,7 +21,7 @@ const device_type Z80SIO = &device_creator<z80sio_device>;
// DEBUGGING
//**************************************************************************
-#define VERBOSE 0
+#define VERBOSE 0
#define VPRINTF(x) do { if (VERBOSE) logerror x; } while (0)
@@ -32,120 +32,120 @@ const device_type Z80SIO = &device_creator<z80sio_device>;
//**************************************************************************
// interrupt states
-const int INT_TRANSMIT = 0x00; // not confirmed
-const int INT_STATUS = 0x01;
-const int INT_RECEIVE = 0x02;
-const int INT_ERROR = 0x03;
-
-const int INT_CHB_TRANSMIT = 0 + INT_TRANSMIT;
-const int INT_CHB_STATUS = 0 + INT_STATUS;
-const int INT_CHB_RECEIVE = 0 + INT_RECEIVE;
-const int INT_CHB_ERROR = 0 + INT_ERROR;
-const int INT_CHA_TRANSMIT = 4 + INT_TRANSMIT;
-const int INT_CHA_STATUS = 4 + INT_STATUS;
-const int INT_CHA_RECEIVE = 4 + INT_RECEIVE;
-const int INT_CHA_ERROR = 4 + INT_ERROR;
+const int INT_TRANSMIT = 0x00; // not confirmed
+const int INT_STATUS = 0x01;
+const int INT_RECEIVE = 0x02;
+const int INT_ERROR = 0x03;
+
+const int INT_CHB_TRANSMIT = 0 + INT_TRANSMIT;
+const int INT_CHB_STATUS = 0 + INT_STATUS;
+const int INT_CHB_RECEIVE = 0 + INT_RECEIVE;
+const int INT_CHB_ERROR = 0 + INT_ERROR;
+const int INT_CHA_TRANSMIT = 4 + INT_TRANSMIT;
+const int INT_CHA_STATUS = 4 + INT_STATUS;
+const int INT_CHA_RECEIVE = 4 + INT_RECEIVE;
+const int INT_CHA_ERROR = 4 + INT_ERROR;
// SIO write register 0
-const int SIO_WR0_RESET_MASK = 0xc0; // D7-D6: Reset control
-const int SIO_WR0_RESET_NULL = 0x00; // 00 = NULL code
-const int SIO_WR0_RESET_RX_CRC = 0x40; // 01 = Reset Rx CRC checker
-const int SIO_WR0_RESET_TX_CRC = 0x80; // 10 = Reset Tx CRC generator
-const int SIO_WR0_RESET_TX_LATCH = 0xc0; // 11 = Reset Tx Underrun/EOM latch
-const int SIO_WR0_COMMAND_MASK = 0x38; // D5-D3: Command
-const int SIO_WR0_COMMAND_NULL = 0x00; // 000 = NULL code
-const int SIO_WR0_COMMAND_SET_ABORT = 0x08; // 001 = Set abort (SDLC)
-const int SIO_WR0_COMMAND_RES_STATUS_INT = 0x10; // 010 = reset ext/status interrupts
-const int SIO_WR0_COMMAND_CH_RESET = 0x18; // 011 = Channel reset
-const int SIO_WR0_COMMAND_ENA_RX_INT = 0x20; // 100 = Enable int on next Rx character
-const int SIO_WR0_COMMAND_RES_TX_INT = 0x28; // 101 = Reset Tx int pending
-const int SIO_WR0_COMMAND_RES_ERROR = 0x30; // 110 = Error reset
-const int SIO_WR0_COMMAND_RETI = 0x38; // 111 = Return from int (CH-A only)
-const int SIO_WR0_REGISTER_MASK = 0x07; // D2-D0: Register select (0-7)
+const int SIO_WR0_RESET_MASK = 0xc0; // D7-D6: Reset control
+const int SIO_WR0_RESET_NULL = 0x00; // 00 = NULL code
+const int SIO_WR0_RESET_RX_CRC = 0x40; // 01 = Reset Rx CRC checker
+const int SIO_WR0_RESET_TX_CRC = 0x80; // 10 = Reset Tx CRC generator
+const int SIO_WR0_RESET_TX_LATCH = 0xc0; // 11 = Reset Tx Underrun/EOM latch
+const int SIO_WR0_COMMAND_MASK = 0x38; // D5-D3: Command
+const int SIO_WR0_COMMAND_NULL = 0x00; // 000 = NULL code
+const int SIO_WR0_COMMAND_SET_ABORT = 0x08; // 001 = Set abort (SDLC)
+const int SIO_WR0_COMMAND_RES_STATUS_INT = 0x10; // 010 = reset ext/status interrupts
+const int SIO_WR0_COMMAND_CH_RESET = 0x18; // 011 = Channel reset
+const int SIO_WR0_COMMAND_ENA_RX_INT = 0x20; // 100 = Enable int on next Rx character
+const int SIO_WR0_COMMAND_RES_TX_INT = 0x28; // 101 = Reset Tx int pending
+const int SIO_WR0_COMMAND_RES_ERROR = 0x30; // 110 = Error reset
+const int SIO_WR0_COMMAND_RETI = 0x38; // 111 = Return from int (CH-A only)
+const int SIO_WR0_REGISTER_MASK = 0x07; // D2-D0: Register select (0-7)
// SIO write register 1
-const int SIO_WR1_READY_WAIT_ENA = 0x80; // D7 = READY/WAIT enable
-const int SIO_WR1_READY_WAIT_FUNCTION = 0x40; // D6 = READY/WAIT function
-const int SIO_WR1_READY_WAIT_ON_RT = 0x20; // D5 = READY/WAIT on R/T
-const int SIO_WR1_RXINT_MASK = 0x18; // D4-D3 = Rx int control
-const int SIO_WR1_RXINT_DISABLE = 0x00; // 00 = Rx int disable
-const int SIO_WR1_RXINT_FIRST = 0x08; // 01 = Rx int on first character
-const int SIO_WR1_RXINT_ALL_PARITY = 0x10; // 10 = int on all Rx characters (parity affects vector)
-const int SIO_WR1_RXINT_ALL_NOPARITY = 0x18; // 11 = int on all Rx characters (parity ignored)
-const int SIO_WR1_STATUS_AFFECTS_VECTOR = 0x04; // D2 = Status affects vector (CH-B only)
-const int SIO_WR1_TXINT_ENABLE = 0x02; // D1 = Tx int enable
-const int SIO_WR1_STATUSINT_ENABLE = 0x01; // D0 = Ext int enable
+const int SIO_WR1_READY_WAIT_ENA = 0x80; // D7 = READY/WAIT enable
+const int SIO_WR1_READY_WAIT_FUNCTION = 0x40; // D6 = READY/WAIT function
+const int SIO_WR1_READY_WAIT_ON_RT = 0x20; // D5 = READY/WAIT on R/T
+const int SIO_WR1_RXINT_MASK = 0x18; // D4-D3 = Rx int control
+const int SIO_WR1_RXINT_DISABLE = 0x00; // 00 = Rx int disable
+const int SIO_WR1_RXINT_FIRST = 0x08; // 01 = Rx int on first character
+const int SIO_WR1_RXINT_ALL_PARITY = 0x10; // 10 = int on all Rx characters (parity affects vector)
+const int SIO_WR1_RXINT_ALL_NOPARITY = 0x18; // 11 = int on all Rx characters (parity ignored)
+const int SIO_WR1_STATUS_AFFECTS_VECTOR = 0x04; // D2 = Status affects vector (CH-B only)
+const int SIO_WR1_TXINT_ENABLE = 0x02; // D1 = Tx int enable
+const int SIO_WR1_STATUSINT_ENABLE = 0x01; // D0 = Ext int enable
// SIO write register 2 (CH-B only)
-const int SIO_WR2_INT_VECTOR_MASK = 0xff; // D7-D0 = interrupt vector
+const int SIO_WR2_INT_VECTOR_MASK = 0xff; // D7-D0 = interrupt vector
// SIO write register 3
-const int SIO_WR3_RX_DATABITS_MASK = 0xc0; // D7-D6 = Rx Data bits
-const int SIO_WR3_RX_DATABITS_5 = 0x00; // 00 = Rx 5 bits/character
-const int SIO_WR3_RX_DATABITS_7 = 0x40; // 01 = Rx 7 bits/character
-const int SIO_WR3_RX_DATABITS_6 = 0x80; // 10 = Rx 6 bits/character
-const int SIO_WR3_RX_DATABITS_8 = 0xc0; // 11 = Rx 8 bits/character
-const int SIO_WR3_AUTO_ENABLES = 0x20; // D5 = Auto enables
-const int SIO_WR3_ENTER_HUNT_PHASE = 0x10; // D4 = Enter hunt phase
-const int SIO_WR3_RX_CRC_ENABLE = 0x08; // D3 = Rx CRC enable
-const int SIO_WR3_ADDR_SEARCH_MODE = 0x04; // D2 = Address search mode (SDLC)
-const int SIO_WR3_SYNC_LOAD_INHIBIT = 0x02; // D1 = Sync character load inhibit
-const int SIO_WR3_RX_ENABLE = 0x01; // D0 = Rx enable
+const int SIO_WR3_RX_DATABITS_MASK = 0xc0; // D7-D6 = Rx Data bits
+const int SIO_WR3_RX_DATABITS_5 = 0x00; // 00 = Rx 5 bits/character
+const int SIO_WR3_RX_DATABITS_7 = 0x40; // 01 = Rx 7 bits/character
+const int SIO_WR3_RX_DATABITS_6 = 0x80; // 10 = Rx 6 bits/character
+const int SIO_WR3_RX_DATABITS_8 = 0xc0; // 11 = Rx 8 bits/character
+const int SIO_WR3_AUTO_ENABLES = 0x20; // D5 = Auto enables
+const int SIO_WR3_ENTER_HUNT_PHASE = 0x10; // D4 = Enter hunt phase
+const int SIO_WR3_RX_CRC_ENABLE = 0x08; // D3 = Rx CRC enable
+const int SIO_WR3_ADDR_SEARCH_MODE = 0x04; // D2 = Address search mode (SDLC)
+const int SIO_WR3_SYNC_LOAD_INHIBIT = 0x02; // D1 = Sync character load inhibit
+const int SIO_WR3_RX_ENABLE = 0x01; // D0 = Rx enable
// SIO write register 4
-const int SIO_WR4_CLOCK_MODE_MASK = 0xc0; // D7-D6 = Clock mode
-const int SIO_WR4_CLOCK_MODE_x1 = 0x00; // 00 = x1 clock mode
-const int SIO_WR4_CLOCK_MODE_x16 = 0x40; // 01 = x16 clock mode
-const int SIO_WR4_CLOCK_MODE_x32 = 0x80; // 10 = x32 clock mode
-const int SIO_WR4_CLOCK_MODE_x64 = 0xc0; // 11 = x64 clock mode
-const int SIO_WR4_SYNC_MODE_MASK = 0x30; // D5-D4 = Sync mode
-const int SIO_WR4_SYNC_MODE_8BIT = 0x00; // 00 = 8 bit sync character
-const int SIO_WR4_SYNC_MODE_16BIT = 0x10; // 01 = 16 bit sync character
-const int SIO_WR4_SYNC_MODE_SDLC = 0x20; // 10 = SDLC mode (01111110 flag)
-const int SIO_WR4_SYNC_MODE_EXTERNAL = 0x30; // 11 = External sync mode
-const int SIO_WR4_STOPBITS_MASK = 0x0c; // D3-D2 = Stop bits
-const int SIO_WR4_STOPBITS_SYNC = 0x00; // 00 = Sync modes enable
-const int SIO_WR4_STOPBITS_1 = 0x04; // 01 = 1 stop bit/character
-const int SIO_WR4_STOPBITS_15 = 0x08; // 10 = 1.5 stop bits/character
-const int SIO_WR4_STOPBITS_2 = 0x0c; // 11 = 2 stop bits/character
-const int SIO_WR4_PARITY_EVEN = 0x02; // D1 = Parity even/odd
-const int SIO_WR4_PARITY_ENABLE = 0x01; // D0 = Parity enable
+const int SIO_WR4_CLOCK_MODE_MASK = 0xc0; // D7-D6 = Clock mode
+const int SIO_WR4_CLOCK_MODE_x1 = 0x00; // 00 = x1 clock mode
+const int SIO_WR4_CLOCK_MODE_x16 = 0x40; // 01 = x16 clock mode
+const int SIO_WR4_CLOCK_MODE_x32 = 0x80; // 10 = x32 clock mode
+const int SIO_WR4_CLOCK_MODE_x64 = 0xc0; // 11 = x64 clock mode
+const int SIO_WR4_SYNC_MODE_MASK = 0x30; // D5-D4 = Sync mode
+const int SIO_WR4_SYNC_MODE_8BIT = 0x00; // 00 = 8 bit sync character
+const int SIO_WR4_SYNC_MODE_16BIT = 0x10; // 01 = 16 bit sync character
+const int SIO_WR4_SYNC_MODE_SDLC = 0x20; // 10 = SDLC mode (01111110 flag)
+const int SIO_WR4_SYNC_MODE_EXTERNAL = 0x30; // 11 = External sync mode
+const int SIO_WR4_STOPBITS_MASK = 0x0c; // D3-D2 = Stop bits
+const int SIO_WR4_STOPBITS_SYNC = 0x00; // 00 = Sync modes enable
+const int SIO_WR4_STOPBITS_1 = 0x04; // 01 = 1 stop bit/character
+const int SIO_WR4_STOPBITS_15 = 0x08; // 10 = 1.5 stop bits/character
+const int SIO_WR4_STOPBITS_2 = 0x0c; // 11 = 2 stop bits/character
+const int SIO_WR4_PARITY_EVEN = 0x02; // D1 = Parity even/odd
+const int SIO_WR4_PARITY_ENABLE = 0x01; // D0 = Parity enable
// SIO write register 5
-const int SIO_WR5_DTR = 0x80; // D7 = DTR
-const int SIO_WR5_TX_DATABITS_MASK = 0x60; // D6-D5 = Tx Data bits
-const int SIO_WR5_TX_DATABITS_5 = 0x00; // 00 = Tx 5 bits/character
-const int SIO_WR5_TX_DATABITS_7 = 0x20; // 01 = Tx 7 bits/character
-const int SIO_WR5_TX_DATABITS_6 = 0x40; // 10 = Tx 6 bits/character
-const int SIO_WR5_TX_DATABITS_8 = 0x60; // 11 = Tx 8 bits/character
-const int SIO_WR5_SEND_BREAK = 0x10; // D4 = Send break
-const int SIO_WR5_TX_ENABLE = 0x08; // D3 = Tx Enable
-const int SIO_WR5_CRC16_SDLC = 0x04; // D2 = CRC-16/SDLC
-const int SIO_WR5_RTS = 0x02; // D1 = RTS
-const int SIO_WR5_TX_CRC_ENABLE = 0x01; // D0 = Tx CRC enable
+const int SIO_WR5_DTR = 0x80; // D7 = DTR
+const int SIO_WR5_TX_DATABITS_MASK = 0x60; // D6-D5 = Tx Data bits
+const int SIO_WR5_TX_DATABITS_5 = 0x00; // 00 = Tx 5 bits/character
+const int SIO_WR5_TX_DATABITS_7 = 0x20; // 01 = Tx 7 bits/character
+const int SIO_WR5_TX_DATABITS_6 = 0x40; // 10 = Tx 6 bits/character
+const int SIO_WR5_TX_DATABITS_8 = 0x60; // 11 = Tx 8 bits/character
+const int SIO_WR5_SEND_BREAK = 0x10; // D4 = Send break
+const int SIO_WR5_TX_ENABLE = 0x08; // D3 = Tx Enable
+const int SIO_WR5_CRC16_SDLC = 0x04; // D2 = CRC-16/SDLC
+const int SIO_WR5_RTS = 0x02; // D1 = RTS
+const int SIO_WR5_TX_CRC_ENABLE = 0x01; // D0 = Tx CRC enable
// SIO write register 6
-const int SIO_WR6_SYNC_7_0_MASK = 0xff; // D7-D0 = Sync bits 7-0
+const int SIO_WR6_SYNC_7_0_MASK = 0xff; // D7-D0 = Sync bits 7-0
// SIO write register 7
-const int SIO_WR7_SYNC_15_8_MASK = 0xff; // D7-D0 = Sync bits 15-8
+const int SIO_WR7_SYNC_15_8_MASK = 0xff; // D7-D0 = Sync bits 15-8
// SIO read register 0
-const int SIO_RR0_BREAK_ABORT = 0x80; // D7 = Break/abort
-const int SIO_RR0_TX_UNDERRUN = 0x40; // D6 = Tx underrun/EOM
-const int SIO_RR0_CTS = 0x20; // D5 = CTS
-const int SIO_RR0_SYNC_HUNT = 0x10; // D4 = Sync/hunt
-const int SIO_RR0_DCD = 0x08; // D3 = DCD
-const int SIO_RR0_TX_BUFFER_EMPTY = 0x04; // D2 = Tx buffer empty
-const int SIO_RR0_INT_PENDING = 0x02; // D1 = int pending (CH-A only)
-const int SIO_RR0_RX_CHAR_AVAILABLE = 0x01; // D0 = Rx character available
+const int SIO_RR0_BREAK_ABORT = 0x80; // D7 = Break/abort
+const int SIO_RR0_TX_UNDERRUN = 0x40; // D6 = Tx underrun/EOM
+const int SIO_RR0_CTS = 0x20; // D5 = CTS
+const int SIO_RR0_SYNC_HUNT = 0x10; // D4 = Sync/hunt
+const int SIO_RR0_DCD = 0x08; // D3 = DCD
+const int SIO_RR0_TX_BUFFER_EMPTY = 0x04; // D2 = Tx buffer empty
+const int SIO_RR0_INT_PENDING = 0x02; // D1 = int pending (CH-A only)
+const int SIO_RR0_RX_CHAR_AVAILABLE = 0x01; // D0 = Rx character available
// SIO read register 1
-const int SIO_RR1_END_OF_FRAME = 0x80; // D7 = End of frame (SDLC)
-const int SIO_RR1_CRC_FRAMING_ERROR = 0x40; // D6 = CRC/Framing error
-const int SIO_RR1_RX_OVERRUN_ERROR = 0x20; // D5 = Rx overrun error
-const int SIO_RR1_PARITY_ERROR = 0x10; // D4 = Parity error
-const int SIO_RR1_IFIELD_BITS_MASK = 0x0e; // D3-D1 = I field bits
+const int SIO_RR1_END_OF_FRAME = 0x80; // D7 = End of frame (SDLC)
+const int SIO_RR1_CRC_FRAMING_ERROR = 0x40; // D6 = CRC/Framing error
+const int SIO_RR1_RX_OVERRUN_ERROR = 0x20; // D5 = Rx overrun error
+const int SIO_RR1_PARITY_ERROR = 0x10; // D4 = Parity error
+const int SIO_RR1_IFIELD_BITS_MASK = 0x0e; // D3-D1 = I field bits
// 100 = 0 in prev, 3 in 2nd prev
// 010 = 0 in prev, 4 in 2nd prev
// 110 = 0 in prev, 5 in 2nd prev
@@ -154,10 +154,10 @@ const int SIO_RR1_IFIELD_BITS_MASK = 0x0e; // D3-D1 = I field bits
// 011 = 0 in prev, 8 in 2nd prev
// 111 = 1 in prev, 8 in 2nd prev
// 000 = 2 in prev, 8 in 2nd prev
-const int SIO_RR1_ALL_SENT = 0x01; // D0 = All sent
+const int SIO_RR1_ALL_SENT = 0x01; // D0 = All sent
// SIO read register 2 (CH-B only)
-const int SIO_RR2_VECTOR_MASK = 0xff; // D7-D0 = Interrupt vector
+const int SIO_RR2_VECTOR_MASK = 0xff; // D7-D0 = Interrupt vector
const UINT8 z80sio_device::k_int_priority[] =
@@ -299,7 +299,7 @@ inline attotime z80sio_device::sio_channel::compute_time_per_character()
z80sio_device::z80sio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, Z80SIO, "Zilog Z80 SIO", tag, owner, clock),
- device_z80daisy_interface(mconfig, *this)
+ device_z80daisy_interface(mconfig, *this)
{
for (int i = 0; i < 8; i++)
m_int_state[i] = 0;
@@ -455,13 +455,13 @@ void z80sio_device::z80daisy_irq_reti()
z80sio_device::sio_channel::sio_channel()
: m_device(NULL),
- m_index(0),
- m_inbuf(-1),
- m_outbuf(-1),
- m_int_on_next_rx(false),
- m_receive_timer(NULL),
- m_receive_inptr(0),
- m_receive_outptr(0)
+ m_index(0),
+ m_inbuf(-1),
+ m_outbuf(-1),
+ m_int_on_next_rx(false),
+ m_receive_timer(NULL),
+ m_receive_inptr(0),
+ m_receive_outptr(0)
{
memset(m_regs, 0, sizeof(m_regs));
memset(m_status, 0, sizeof(m_status));