diff options
Diffstat (limited to 'src/emu/machine/f3853.c')
-rw-r--r-- | src/emu/machine/f3853.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/emu/machine/f3853.c b/src/emu/machine/f3853.c index 8e689381296..3ee448e47bf 100644 --- a/src/emu/machine/f3853.c +++ b/src/emu/machine/f3853.c @@ -1,22 +1,22 @@ /********************************************************************** - Fairchild F3853 SRAM interface with integrated interrupt - controller and timer (SMI) + Fairchild F3853 SRAM interface with integrated interrupt + controller and timer (SMI) - This chip is a timer shift register, basically the same as in the - F3851. + This chip is a timer shift register, basically the same as in the + F3851. - Based on a datasheet obtained from www.freetradezone.com + Based on a datasheet obtained from www.freetradezone.com - The SMI does not have DC0 and DC1, only DC0; as a result, it does - not respond to the main CPU's DC0/DC1 swap instruction. This may - lead to two devices responding to the same DC0 address and - attempting to place their bytes on the data bus simultaneously! + The SMI does not have DC0 and DC1, only DC0; as a result, it does + not respond to the main CPU's DC0/DC1 swap instruction. This may + lead to two devices responding to the same DC0 address and + attempting to place their bytes on the data bus simultaneously! - 8-bit shift register: - Feedback in0 = !((out3 ^ out4) ^ (out5 ^ out7)) - Interrupts are at 0xfe - 0xff stops the register (0xfe is never reached) + 8-bit shift register: + Feedback in0 = !((out3 ^ out4) ^ (out5 ^ out7)) + Interrupts are at 0xfe + 0xff stops the register (0xfe is never reached) **********************************************************************/ |