diff options
Diffstat (limited to 'src/emu/cpu')
-rw-r--r-- | src/emu/cpu/am29000/am29ops.h | 4 | ||||
-rw-r--r-- | src/emu/cpu/i386/i386ops.c | 4 | ||||
-rw-r--r-- | src/emu/cpu/i86/instr286.c | 2 | ||||
-rw-r--r-- | src/emu/cpu/i86/instr86.c | 4 | ||||
-rw-r--r-- | src/emu/cpu/i86/table286.h | 16 | ||||
-rw-r--r-- | src/emu/cpu/konami/konamops.c | 2 | ||||
-rw-r--r-- | src/emu/cpu/m6800/6800ops.c | 2 | ||||
-rw-r--r-- | src/emu/cpu/m68000/m68kfpu.c | 6 | ||||
-rw-r--r-- | src/emu/cpu/m6805/6805ops.c | 2 | ||||
-rw-r--r-- | src/emu/cpu/m6809/6809ops.c | 2 | ||||
-rw-r--r-- | src/emu/cpu/minx/minx.c | 4 | ||||
-rw-r--r-- | src/emu/cpu/mips/mips3com.c | 4 |
12 files changed, 26 insertions, 26 deletions
diff --git a/src/emu/cpu/am29000/am29ops.h b/src/emu/cpu/am29000/am29ops.h index 9040379a901..f23189a043a 100644 --- a/src/emu/cpu/am29000/am29ops.h +++ b/src/emu/cpu/am29000/am29ops.h @@ -1059,7 +1059,7 @@ static void LOADM(am29000_state *am29000) static void STORE(am29000_state *am29000) { UINT32 addr = INST_M_BIT ? I8: GET_RB_VAL; -// UINT32 r; +// UINT32 r; if (INST_UA_BIT) fatalerror("Am29000: UA bit set on LOAD\n"); @@ -1067,7 +1067,7 @@ static void STORE(am29000_state *am29000) if (INST_CE_BIT) { logerror("Am29000: Attempting a co-processor LOAD!\n"); -// r = 0; +// r = 0; } else { diff --git a/src/emu/cpu/i386/i386ops.c b/src/emu/cpu/i386/i386ops.c index c851c8ca2eb..85f8eb4ad08 100644 --- a/src/emu/cpu/i386/i386ops.c +++ b/src/emu/cpu/i386/i386ops.c @@ -1018,7 +1018,7 @@ static void I386OP(repeat)(i386_state *cpustate, int invert_flag) UINT32 repeated_eip = cpustate->eip; UINT32 repeated_pc = cpustate->pc; UINT8 opcode; // = FETCH(cpustate); -// UINT32 eas, ead; +// UINT32 eas, ead; UINT32 count; INT32 cycle_base = 0, cycle_adjustment = 0; UINT8 prefix_flag=1; @@ -1070,7 +1070,7 @@ static void I386OP(repeat)(i386_state *cpustate, int invert_flag) // FIXME: the following does not work if both address override and segment override are used i386_translate(cpustate, cpustate->segment_override, cpustate->sreg[cpustate->segment_prefix].d ? REG32(ESI) : REG16(SI) ); } else { - //eas = + //eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); diff --git a/src/emu/cpu/i86/instr286.c b/src/emu/cpu/i86/instr286.c index bbf1e43f3f5..f25a446ba64 100644 --- a/src/emu/cpu/i86/instr286.c +++ b/src/emu/cpu/i86/instr286.c @@ -841,7 +841,7 @@ static void PREFIX286(_escape_7)(i8086_state *cpustate) /* Opcode 0xdf */ if ((cpustate->msw&8) || (cpustate->msw&4)) throw TRAP(FPU_UNAVAILABLE,-1); unsigned ModRM = FETCH; ICOUNT -= timing.nop; - GetRMByte(ModRM); + GetRMByte(ModRM); if (ModRM == 0xe0) cpustate->regs.w[AX] = 0xffff; // FPU not present } diff --git a/src/emu/cpu/i86/instr86.c b/src/emu/cpu/i86/instr86.c index 75ad21446c3..8d477125627 100644 --- a/src/emu/cpu/i86/instr86.c +++ b/src/emu/cpu/i86/instr86.c @@ -1177,8 +1177,8 @@ static void PREFIX86(_cmp_axd16)(i8086_state *cpustate) /* Opcode 0x3d */ static void PREFIX86(_aas)(i8086_state *cpustate) /* Opcode 0x3f */ { -// UINT8 ALcarry=1; -// if (cpustate->regs.b[AL]>0xf9) ALcarry=2; +// UINT8 ALcarry=1; +// if (cpustate->regs.b[AL]>0xf9) ALcarry=2; if (AF || ((cpustate->regs.b[AL] & 0xf) > 9)) { diff --git a/src/emu/cpu/i86/table286.h b/src/emu/cpu/i86/table286.h index 24b1b05215b..0ac2afa7570 100644 --- a/src/emu/cpu/i86/table286.h +++ b/src/emu/cpu/i86/table286.h @@ -221,14 +221,14 @@ static void (*const PREFIX286(_instruction)[256])(i8086_state *cpustate) = PREFIX86(_aad), /* 0xd5 */ PREFIX286(_invalid), PREFIX86(_xlat), /* 0xd7 */ - PREFIX286(_escape), /* 0xd8 */ - PREFIX286(_escape), /* 0xd9 */ - PREFIX286(_escape), /* 0xda */ - PREFIX286(_escape), /* 0xdb */ - PREFIX286(_escape), /* 0xdc */ - PREFIX286(_escape), /* 0xdd */ - PREFIX286(_escape), /* 0xde */ - PREFIX286(_escape_7), /* 0xdf */ + PREFIX286(_escape), /* 0xd8 */ + PREFIX286(_escape), /* 0xd9 */ + PREFIX286(_escape), /* 0xda */ + PREFIX286(_escape), /* 0xdb */ + PREFIX286(_escape), /* 0xdc */ + PREFIX286(_escape), /* 0xdd */ + PREFIX286(_escape), /* 0xde */ + PREFIX286(_escape_7), /* 0xdf */ PREFIX86(_loopne), /* 0xe0 */ PREFIX86(_loope), /* 0xe1 */ PREFIX86(_loop), /* 0xe2 */ diff --git a/src/emu/cpu/konami/konamops.c b/src/emu/cpu/konami/konamops.c index e04c2483311..1049e18e28e 100644 --- a/src/emu/cpu/konami/konamops.c +++ b/src/emu/cpu/konami/konamops.c @@ -300,7 +300,7 @@ INLINE void bra( konami_state *cpustate ) } /* $21 BRN relative ----- */ -static UINT8 konami_brn_t; // hack around GCC 4.6 error because we need the side effects of IMMBYTE +static UINT8 konami_brn_t; // hack around GCC 4.6 error because we need the side effects of IMMBYTE INLINE void brn( konami_state *cpustate ) { IMMBYTE(cpustate, konami_brn_t); diff --git a/src/emu/cpu/m6800/6800ops.c b/src/emu/cpu/m6800/6800ops.c index 1948e325888..97aab2f8dba 100644 --- a/src/emu/cpu/m6800/6800ops.c +++ b/src/emu/cpu/m6800/6800ops.c @@ -233,7 +233,7 @@ OP_HANDLER( bra ) } /* $21 BRN relative ----- */ -static UINT8 m6800_brn_t; // hack around GCC 4.6 error because we need the side effects of IMMBYTE +static UINT8 m6800_brn_t; // hack around GCC 4.6 error because we need the side effects of IMMBYTE OP_HANDLER( brn ) { IMMBYTE(m6800_brn_t); diff --git a/src/emu/cpu/m68000/m68kfpu.c b/src/emu/cpu/m68000/m68kfpu.c index 27bf7c73a3e..e75142a2ade 100644 --- a/src/emu/cpu/m68000/m68kfpu.c +++ b/src/emu/cpu/m68000/m68kfpu.c @@ -257,9 +257,9 @@ INLINE void store_pack_float80(m68ki_cpu_core *m68k, UINT32 ea, int k, floatx80 INLINE void SET_CONDITION_CODES(m68ki_cpu_core *m68k, floatx80 reg) { -// UINT64 *regi; +// UINT64 *regi; -// regi = (UINT64 *)® +// regi = (UINT64 *)® REG_FPSR &= ~(FPCC_N|FPCC_Z|FPCC_I|FPCC_NAN); @@ -1341,7 +1341,7 @@ static void fpgen_rm_reg(m68ki_cpu_core *m68k, UINT16 w2) } case 0x1e: // FGETEXP { -// floatx80 temp = source; +// floatx80 temp = source; INT16 temp2; temp2 = source.high; // get the exponent diff --git a/src/emu/cpu/m6805/6805ops.c b/src/emu/cpu/m6805/6805ops.c index 0cb9f6e3baf..fba19931e1f 100644 --- a/src/emu/cpu/m6805/6805ops.c +++ b/src/emu/cpu/m6805/6805ops.c @@ -77,7 +77,7 @@ OP_HANDLER( bra ) } /* $21 BRN relative ---- */ -static UINT8 m6805_brn_t; // hack around GCC 4.6 error because we need the side effects of IMMBYTE +static UINT8 m6805_brn_t; // hack around GCC 4.6 error because we need the side effects of IMMBYTE OP_HANDLER( brn ) { IMMBYTE(m6805_brn_t); diff --git a/src/emu/cpu/m6809/6809ops.c b/src/emu/cpu/m6809/6809ops.c index 924ea78795d..e9942d418ef 100644 --- a/src/emu/cpu/m6809/6809ops.c +++ b/src/emu/cpu/m6809/6809ops.c @@ -371,7 +371,7 @@ OP_HANDLER( bra ) } /* $21 BRN relative ----- */ -static UINT8 m6809_brn_t; // hack around GCC 4.6 error because we need the side effects of IMMBYTE +static UINT8 m6809_brn_t; // hack around GCC 4.6 error because we need the side effects of IMMBYTE OP_HANDLER( brn ) { IMMBYTE(m6809_brn_t); diff --git a/src/emu/cpu/minx/minx.c b/src/emu/cpu/minx/minx.c index d0bc3321b2b..59fa2138597 100644 --- a/src/emu/cpu/minx/minx.c +++ b/src/emu/cpu/minx/minx.c @@ -169,14 +169,14 @@ INLINE UINT16 rdop16( minx_state *minx ) static CPU_EXECUTE( minx ) { -// UINT32 oldpc; +// UINT32 oldpc; UINT8 op; minx_state *minx = get_safe_token(device); do { debugger_instruction_hook(device, GET_MINX_PC); -// oldpc = GET_MINX_PC; +// oldpc = GET_MINX_PC; if ( minx->interrupt_pending ) { diff --git a/src/emu/cpu/mips/mips3com.c b/src/emu/cpu/mips/mips3com.c index fca04f1c58d..e8327a440c3 100644 --- a/src/emu/cpu/mips/mips3com.c +++ b/src/emu/cpu/mips/mips3com.c @@ -312,7 +312,7 @@ void mips3com_tlbwr(mips3_state *mips) void mips3com_tlbp(mips3_state *mips) { UINT32 tlbindex; -// UINT64 vpn; +// UINT64 vpn; /* iterate over TLB entries */ for (tlbindex = 0; tlbindex < mips->tlbentries; tlbindex++) @@ -329,7 +329,7 @@ void mips3com_tlbp(mips3_state *mips) } /* validate that our tlb_table was in sync */ -// vpn = ((mips->cpr[0][COP0_EntryHi] >> 13) & 0x07ffffff) << 1; +// vpn = ((mips->cpr[0][COP0_EntryHi] >> 13) & 0x07ffffff) << 1; if (tlbindex != mips->tlbentries) mips->cpr[0][COP0_Index] = tlbindex; else |