diff options
Diffstat (limited to 'src/emu/cpu/z8/z8ops.c')
-rw-r--r-- | src/emu/cpu/z8/z8ops.c | 306 |
1 files changed, 153 insertions, 153 deletions
diff --git a/src/emu/cpu/z8/z8ops.c b/src/emu/cpu/z8/z8ops.c index 43ef894235e..5069b23230e 100644 --- a/src/emu/cpu/z8/z8ops.c +++ b/src/emu/cpu/z8/z8ops.c @@ -11,16 +11,16 @@ MACROS ***************************************************************************/ -#define read(_reg) register_read(cpustate, _reg) -#define r(_data) get_working_register(cpustate, _data) -#define Ir(_data) get_intermediate_register(cpustate, get_working_register(cpustate, _data)) -#define R get_register(cpustate, fetch(cpustate)) -#define IR get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate))) -#define RR get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate))) -#define IM fetch(cpustate) -#define flag(_flag) ((cpustate->r[Z8_REGISTER_FLAGS] & Z8_FLAGS##_##_flag) ? 1 : 0) - -#define mode_r1_r2(_func) \ +#define read(_reg) register_read(cpustate, _reg) +#define r(_data) get_working_register(cpustate, _data) +#define Ir(_data) get_intermediate_register(cpustate, get_working_register(cpustate, _data)) +#define R get_register(cpustate, fetch(cpustate)) +#define IR get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate))) +#define RR get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate))) +#define IM fetch(cpustate) +#define flag(_flag) ((cpustate->r[Z8_REGISTER_FLAGS] & Z8_FLAGS##_##_flag) ? 1 : 0) + +#define mode_r1_r2(_func) \ UINT8 dst_src = fetch(cpustate);\ UINT8 dst = r(dst_src >> 4);\ UINT8 src = read(r(dst_src & 0x0f));\ @@ -116,8 +116,8 @@ static void clear(z8_state *cpustate, UINT8 dst) register_write(cpustate, dst, 0); } -INSTRUCTION( clr_R1 ) { mode_R1(clear) } -INSTRUCTION( clr_IR1 ) { mode_IR1(clear) } +INSTRUCTION( clr_R1 ) { mode_R1(clear) } +INSTRUCTION( clr_IR1 ) { mode_IR1(clear) } static void load(z8_state *cpustate, UINT8 dst, UINT8 src) { @@ -125,20 +125,20 @@ static void load(z8_state *cpustate, UINT8 dst, UINT8 src) register_write(cpustate, dst, src); } -INSTRUCTION( ld_r1_IM ) { mode_r1_IM(load) } -INSTRUCTION( ld_r1_R2 ) { mode_r1_R2(load) } -INSTRUCTION( ld_r2_R1 ) { mode_r2_R1(load) } -INSTRUCTION( ld_Ir1_r2 ) { mode_Ir1_r2(load) } -INSTRUCTION( ld_R2_IR1 ) { mode_R2_IR1(load) } -INSTRUCTION( ld_r1_x_R2 ) { mode_r1_x_R2(load) } -INSTRUCTION( ld_r2_x_R1 ) { mode_r2_x_R1(load) } +INSTRUCTION( ld_r1_IM ) { mode_r1_IM(load) } +INSTRUCTION( ld_r1_R2 ) { mode_r1_R2(load) } +INSTRUCTION( ld_r2_R1 ) { mode_r2_R1(load) } +INSTRUCTION( ld_Ir1_r2 ) { mode_Ir1_r2(load) } +INSTRUCTION( ld_R2_IR1 ) { mode_R2_IR1(load) } +INSTRUCTION( ld_r1_x_R2 ) { mode_r1_x_R2(load) } +INSTRUCTION( ld_r2_x_R1 ) { mode_r2_x_R1(load) } -INSTRUCTION( ld_r1_r2 ) { mode_r1_r2(load) } -INSTRUCTION( ld_r1_Ir2 ) { mode_r1_Ir2(load) } -INSTRUCTION( ld_R2_R1 ) { mode_R2_R1(load) } -INSTRUCTION( ld_IR2_R1 ) { mode_IR2_R1(load) } -INSTRUCTION( ld_R1_IM ) { mode_R1_IM(load) } -INSTRUCTION( ld_IR1_IM ) { mode_IR1_IM(load) } +INSTRUCTION( ld_r1_r2 ) { mode_r1_r2(load) } +INSTRUCTION( ld_r1_Ir2 ) { mode_r1_Ir2(load) } +INSTRUCTION( ld_R2_R1 ) { mode_R2_R1(load) } +INSTRUCTION( ld_IR2_R1 ) { mode_IR2_R1(load) } +INSTRUCTION( ld_R1_IM ) { mode_R1_IM(load) } +INSTRUCTION( ld_IR1_IM ) { mode_IR1_IM(load) } static void load_from_memory(z8_state *cpustate, address_space *space) { @@ -196,34 +196,34 @@ static void load_to_memory_autoinc(z8_state *cpustate, address_space *space) register_write(cpustate, src, real_src + 1); } -INSTRUCTION( ldc_r1_Irr2 ) { load_from_memory(cpustate, cpustate->program); } -INSTRUCTION( ldc_r2_Irr1 ) { load_to_memory(cpustate, cpustate->program); } -INSTRUCTION( ldci_Ir1_Irr2 ) { load_from_memory_autoinc(cpustate, cpustate->program); } -INSTRUCTION( ldci_Ir2_Irr1 ) { load_to_memory_autoinc(cpustate, cpustate->program); } -INSTRUCTION( lde_r1_Irr2 ) { load_from_memory(cpustate, cpustate->data); } -INSTRUCTION( lde_r2_Irr1 ) { load_to_memory(cpustate, cpustate->data); } -INSTRUCTION( ldei_Ir1_Irr2 ) { load_from_memory_autoinc(cpustate, cpustate->data); } -INSTRUCTION( ldei_Ir2_Irr1 ) { load_to_memory_autoinc(cpustate, cpustate->data); } +INSTRUCTION( ldc_r1_Irr2 ) { load_from_memory(cpustate, cpustate->program); } +INSTRUCTION( ldc_r2_Irr1 ) { load_to_memory(cpustate, cpustate->program); } +INSTRUCTION( ldci_Ir1_Irr2 ) { load_from_memory_autoinc(cpustate, cpustate->program); } +INSTRUCTION( ldci_Ir2_Irr1 ) { load_to_memory_autoinc(cpustate, cpustate->program); } +INSTRUCTION( lde_r1_Irr2 ) { load_from_memory(cpustate, cpustate->data); } +INSTRUCTION( lde_r2_Irr1 ) { load_to_memory(cpustate, cpustate->data); } +INSTRUCTION( ldei_Ir1_Irr2 ) { load_from_memory_autoinc(cpustate, cpustate->data); } +INSTRUCTION( ldei_Ir2_Irr1 ) { load_to_memory_autoinc(cpustate, cpustate->data); } static void pop(z8_state *cpustate, UINT8 dst) { /* dst <- @SP - SP <- SP + 1 */ + SP <- SP + 1 */ register_write(cpustate, dst, stack_pop_byte(cpustate)); } -INSTRUCTION( pop_R1 ) { mode_R1(pop) } -INSTRUCTION( pop_IR1 ) { mode_IR1(pop) } +INSTRUCTION( pop_R1 ) { mode_R1(pop) } +INSTRUCTION( pop_IR1 ) { mode_IR1(pop) } static void push(z8_state *cpustate, UINT8 src) { /* SP <- SP - 1 - @SP <- src */ + @SP <- src */ stack_push_byte(cpustate, read(src)); } -INSTRUCTION( push_R2 ) { mode_R1(push) } -INSTRUCTION( push_IR2 ) { mode_IR1(push) } +INSTRUCTION( push_R2 ) { mode_R1(push) } +INSTRUCTION( push_IR2 ) { mode_IR1(push) } /*************************************************************************** ARITHMETIC INSTRUCTIONS @@ -245,12 +245,12 @@ static void add_carry(z8_state *cpustate, UINT8 dst, INT8 src) register_write(cpustate, dst, new_data & 0xff); } -INSTRUCTION( adc_r1_r2 ) { mode_r1_r2(add_carry) } -INSTRUCTION( adc_r1_Ir2 ) { mode_r1_Ir2(add_carry) } -INSTRUCTION( adc_R2_R1 ) { mode_R2_R1(add_carry) } -INSTRUCTION( adc_IR2_R1 ) { mode_IR2_R1(add_carry) } -INSTRUCTION( adc_R1_IM ) { mode_R1_IM(add_carry) } -INSTRUCTION( adc_IR1_IM ) { mode_IR1_IM(add_carry) } +INSTRUCTION( adc_r1_r2 ) { mode_r1_r2(add_carry) } +INSTRUCTION( adc_r1_Ir2 ) { mode_r1_Ir2(add_carry) } +INSTRUCTION( adc_R2_R1 ) { mode_R2_R1(add_carry) } +INSTRUCTION( adc_IR2_R1 ) { mode_IR2_R1(add_carry) } +INSTRUCTION( adc_R1_IM ) { mode_R1_IM(add_carry) } +INSTRUCTION( adc_IR1_IM ) { mode_IR1_IM(add_carry) } static void add(z8_state *cpustate, UINT8 dst, INT8 src) { @@ -268,12 +268,12 @@ static void add(z8_state *cpustate, UINT8 dst, INT8 src) register_write(cpustate, dst, new_data & 0xff); } -INSTRUCTION( add_r1_r2 ) { mode_r1_r2(add) } -INSTRUCTION( add_r1_Ir2 ) { mode_r1_Ir2(add) } -INSTRUCTION( add_R2_R1 ) { mode_R2_R1(add) } -INSTRUCTION( add_IR2_R1 ) { mode_IR2_R1(add) } -INSTRUCTION( add_R1_IM ) { mode_R1_IM(add) } -INSTRUCTION( add_IR1_IM ) { mode_IR1_IM(add) } +INSTRUCTION( add_r1_r2 ) { mode_r1_r2(add) } +INSTRUCTION( add_r1_Ir2 ) { mode_r1_Ir2(add) } +INSTRUCTION( add_R2_R1 ) { mode_R2_R1(add) } +INSTRUCTION( add_IR2_R1 ) { mode_IR2_R1(add) } +INSTRUCTION( add_R1_IM ) { mode_R1_IM(add) } +INSTRUCTION( add_IR1_IM ) { mode_IR1_IM(add) } static void compare(z8_state *cpustate, UINT8 dst, UINT8 src) { @@ -287,19 +287,19 @@ static void compare(z8_state *cpustate, UINT8 dst, UINT8 src) set_flag_v(((data & 0x80) != (src & 0x80)) && ((new_data & 0x80) == (src & 0x80))); } -INSTRUCTION( cp_r1_r2 ) { mode_r1_r2(compare) } -INSTRUCTION( cp_r1_Ir2 ) { mode_r1_Ir2(compare) } -INSTRUCTION( cp_R2_R1 ) { mode_R2_R1(compare) } -INSTRUCTION( cp_IR2_R1 ) { mode_IR2_R1(compare) } -INSTRUCTION( cp_R1_IM ) { mode_R1_IM(compare) } -INSTRUCTION( cp_IR1_IM ) { mode_IR1_IM(compare) } +INSTRUCTION( cp_r1_r2 ) { mode_r1_r2(compare) } +INSTRUCTION( cp_r1_Ir2 ) { mode_r1_Ir2(compare) } +INSTRUCTION( cp_R2_R1 ) { mode_R2_R1(compare) } +INSTRUCTION( cp_IR2_R1 ) { mode_IR2_R1(compare) } +INSTRUCTION( cp_R1_IM ) { mode_R1_IM(compare) } +INSTRUCTION( cp_IR1_IM ) { mode_IR1_IM(compare) } static void decimal_adjust(z8_state *cpustate, UINT8 dst) { } -INSTRUCTION( da_R1 ) { mode_R1(decimal_adjust) } -INSTRUCTION( da_IR1 ) { mode_IR1(decimal_adjust) } +INSTRUCTION( da_R1 ) { mode_R1(decimal_adjust) } +INSTRUCTION( da_IR1 ) { mode_IR1(decimal_adjust) } static void decrement(z8_state *cpustate, UINT8 dst) { @@ -313,8 +313,8 @@ static void decrement(z8_state *cpustate, UINT8 dst) register_write(cpustate, dst, data); } -INSTRUCTION( dec_R1 ) { mode_R1(decrement) } -INSTRUCTION( dec_IR1 ) { mode_IR1(decrement) } +INSTRUCTION( dec_R1 ) { mode_R1(decrement) } +INSTRUCTION( dec_IR1 ) { mode_IR1(decrement) } static void decrement_word(z8_state *cpustate, UINT8 dst) { @@ -328,8 +328,8 @@ static void decrement_word(z8_state *cpustate, UINT8 dst) register_pair_write(cpustate, dst, data); } -INSTRUCTION( decw_RR1 ) { mode_RR1(decrement_word) } -INSTRUCTION( decw_IR1 ) { mode_IR1(decrement_word) } +INSTRUCTION( decw_RR1 ) { mode_RR1(decrement_word) } +INSTRUCTION( decw_IR1 ) { mode_IR1(decrement_word) } static void increment(z8_state *cpustate, UINT8 dst) { @@ -343,9 +343,9 @@ static void increment(z8_state *cpustate, UINT8 dst) register_write(cpustate, dst, data); } -INSTRUCTION( inc_r1 ) { mode_r1(increment) } -INSTRUCTION( inc_R1 ) { mode_R1(increment) } -INSTRUCTION( inc_IR1 ) { mode_IR1(increment) } +INSTRUCTION( inc_r1 ) { mode_r1(increment) } +INSTRUCTION( inc_R1 ) { mode_R1(increment) } +INSTRUCTION( inc_IR1 ) { mode_IR1(increment) } static void increment_word(z8_state *cpustate, UINT8 dst) { @@ -359,8 +359,8 @@ static void increment_word(z8_state *cpustate, UINT8 dst) register_pair_write(cpustate, dst, data); } -INSTRUCTION( incw_RR1 ) { mode_RR1(increment_word) } -INSTRUCTION( incw_IR1 ) { mode_IR1(increment_word) } +INSTRUCTION( incw_RR1 ) { mode_RR1(increment_word) } +INSTRUCTION( incw_IR1 ) { mode_IR1(increment_word) } static void subtract_carry(z8_state *cpustate, UINT8 dst, UINT8 src) { @@ -378,12 +378,12 @@ static void subtract_carry(z8_state *cpustate, UINT8 dst, UINT8 src) register_write(cpustate, dst, new_data & 0xff); } -INSTRUCTION( sbc_r1_r2 ) { mode_r1_r2(subtract_carry) } -INSTRUCTION( sbc_r1_Ir2 ) { mode_r1_Ir2(subtract_carry) } -INSTRUCTION( sbc_R2_R1 ) { mode_R2_R1(subtract_carry) } -INSTRUCTION( sbc_IR2_R1 ) { mode_IR2_R1(subtract_carry) } -INSTRUCTION( sbc_R1_IM ) { mode_R1_IM(subtract_carry) } -INSTRUCTION( sbc_IR1_IM ) { mode_IR1_IM(subtract_carry) } +INSTRUCTION( sbc_r1_r2 ) { mode_r1_r2(subtract_carry) } +INSTRUCTION( sbc_r1_Ir2 ) { mode_r1_Ir2(subtract_carry) } +INSTRUCTION( sbc_R2_R1 ) { mode_R2_R1(subtract_carry) } +INSTRUCTION( sbc_IR2_R1 ) { mode_IR2_R1(subtract_carry) } +INSTRUCTION( sbc_R1_IM ) { mode_R1_IM(subtract_carry) } +INSTRUCTION( sbc_IR1_IM ) { mode_IR1_IM(subtract_carry) } static void subtract(z8_state *cpustate, UINT8 dst, UINT8 src) { @@ -401,12 +401,12 @@ static void subtract(z8_state *cpustate, UINT8 dst, UINT8 src) register_write(cpustate, dst, new_data & 0xff); } -INSTRUCTION( sub_r1_r2 ) { mode_r1_r2(subtract) } -INSTRUCTION( sub_r1_Ir2 ) { mode_r1_Ir2(subtract) } -INSTRUCTION( sub_R2_R1 ) { mode_R2_R1(subtract) } -INSTRUCTION( sub_IR2_R1 ) { mode_IR2_R1(subtract) } -INSTRUCTION( sub_R1_IM ) { mode_R1_IM(subtract) } -INSTRUCTION( sub_IR1_IM ) { mode_IR1_IM(subtract) } +INSTRUCTION( sub_r1_r2 ) { mode_r1_r2(subtract) } +INSTRUCTION( sub_r1_Ir2 ) { mode_r1_Ir2(subtract) } +INSTRUCTION( sub_R2_R1 ) { mode_R2_R1(subtract) } +INSTRUCTION( sub_IR2_R1 ) { mode_IR2_R1(subtract) } +INSTRUCTION( sub_R1_IM ) { mode_R1_IM(subtract) } +INSTRUCTION( sub_IR1_IM ) { mode_IR1_IM(subtract) } /*************************************************************************** LOGICAL INSTRUCTIONS @@ -423,12 +423,12 @@ static void _and(z8_state *cpustate, UINT8 dst, UINT8 src) set_flag_v(0); } -INSTRUCTION( and_r1_r2 ) { mode_r1_r2(_and) } -INSTRUCTION( and_r1_Ir2 ) { mode_r1_Ir2(_and) } -INSTRUCTION( and_R2_R1 ) { mode_R2_R1(_and) } -INSTRUCTION( and_IR2_R1 ) { mode_IR2_R1(_and) } -INSTRUCTION( and_R1_IM ) { mode_R1_IM(_and) } -INSTRUCTION( and_IR1_IM ) { mode_IR1_IM(_and) } +INSTRUCTION( and_r1_r2 ) { mode_r1_r2(_and) } +INSTRUCTION( and_r1_Ir2 ) { mode_r1_Ir2(_and) } +INSTRUCTION( and_R2_R1 ) { mode_R2_R1(_and) } +INSTRUCTION( and_IR2_R1 ) { mode_IR2_R1(_and) } +INSTRUCTION( and_R1_IM ) { mode_R1_IM(_and) } +INSTRUCTION( and_IR1_IM ) { mode_IR1_IM(_and) } static void complement(z8_state *cpustate, UINT8 dst) { @@ -441,8 +441,8 @@ static void complement(z8_state *cpustate, UINT8 dst) set_flag_v(0); } -INSTRUCTION( com_R1 ) { mode_R1(complement) } -INSTRUCTION( com_IR1 ) { mode_IR1(complement) } +INSTRUCTION( com_R1 ) { mode_R1(complement) } +INSTRUCTION( com_IR1 ) { mode_IR1(complement) } static void _or(z8_state *cpustate, UINT8 dst, UINT8 src) { @@ -455,12 +455,12 @@ static void _or(z8_state *cpustate, UINT8 dst, UINT8 src) set_flag_v(0); } -INSTRUCTION( or_r1_r2 ) { mode_r1_r2(_or) } -INSTRUCTION( or_r1_Ir2 ) { mode_r1_Ir2(_or) } -INSTRUCTION( or_R2_R1 ) { mode_R2_R1(_or) } -INSTRUCTION( or_IR2_R1 ) { mode_IR2_R1(_or) } -INSTRUCTION( or_R1_IM ) { mode_R1_IM(_or) } -INSTRUCTION( or_IR1_IM ) { mode_IR1_IM(_or) } +INSTRUCTION( or_r1_r2 ) { mode_r1_r2(_or) } +INSTRUCTION( or_r1_Ir2 ) { mode_r1_Ir2(_or) } +INSTRUCTION( or_R2_R1 ) { mode_R2_R1(_or) } +INSTRUCTION( or_IR2_R1 ) { mode_IR2_R1(_or) } +INSTRUCTION( or_R1_IM ) { mode_R1_IM(_or) } +INSTRUCTION( or_IR1_IM ) { mode_IR1_IM(_or) } static void _xor(z8_state *cpustate, UINT8 dst, UINT8 src) { @@ -473,12 +473,12 @@ static void _xor(z8_state *cpustate, UINT8 dst, UINT8 src) set_flag_v(0); } -INSTRUCTION( xor_r1_r2 ) { mode_r1_r2(_xor) } -INSTRUCTION( xor_r1_Ir2 ) { mode_r1_Ir2(_xor) } -INSTRUCTION( xor_R2_R1 ) { mode_R2_R1(_xor) } -INSTRUCTION( xor_IR2_R1 ) { mode_IR2_R1(_xor) } -INSTRUCTION( xor_R1_IM ) { mode_R1_IM(_xor) } -INSTRUCTION( xor_IR1_IM ) { mode_IR1_IM(_xor) } +INSTRUCTION( xor_r1_r2 ) { mode_r1_r2(_xor) } +INSTRUCTION( xor_r1_Ir2 ) { mode_r1_Ir2(_xor) } +INSTRUCTION( xor_R2_R1 ) { mode_R2_R1(_xor) } +INSTRUCTION( xor_IR2_R1 ) { mode_IR2_R1(_xor) } +INSTRUCTION( xor_R1_IM ) { mode_R1_IM(_xor) } +INSTRUCTION( xor_IR1_IM ) { mode_IR1_IM(_xor) } /*************************************************************************** PROGRAM CONTROL INSTRUCTIONS @@ -490,8 +490,8 @@ static void call(z8_state *cpustate, UINT16 dst) cpustate->pc = dst; } -INSTRUCTION( call_IRR1 ) { UINT16 dst = register_pair_read(cpustate, get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate)))); call(cpustate, dst); } -INSTRUCTION( call_DA ) { UINT16 dst = (fetch(cpustate) << 8) | fetch(cpustate); call(cpustate, dst); } +INSTRUCTION( call_IRR1 ) { UINT16 dst = register_pair_read(cpustate, get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate)))); call(cpustate, dst); } +INSTRUCTION( call_DA ) { UINT16 dst = (fetch(cpustate) << 8) | fetch(cpustate); call(cpustate, dst); } INSTRUCTION( djnz_r1_RA ) { @@ -513,11 +513,11 @@ INSTRUCTION( djnz_r1_RA ) INSTRUCTION( iret ) { /* FLAGS <- @SP - SP <- SP + 1 */ + SP <- SP + 1 */ register_write(cpustate, Z8_REGISTER_FLAGS, stack_pop_byte(cpustate)); /* PC <- @SP - SP <- SP + 2 */ + SP <- SP + 2 */ cpustate->pc = stack_pop_word(cpustate); /* IMR (7) <- 1 */ @@ -527,7 +527,7 @@ INSTRUCTION( iret ) INSTRUCTION( ret ) { /* PC <- @SP - SP <- SP + 2 */ + SP <- SP + 2 */ cpustate->pc = stack_pop_word(cpustate); } @@ -537,7 +537,7 @@ static void jump(z8_state *cpustate, UINT16 dst) cpustate->pc = dst; } -INSTRUCTION( jp_IRR1 ) { jump(cpustate, register_pair_read(cpustate, IR)); } +INSTRUCTION( jp_IRR1 ) { jump(cpustate, register_pair_read(cpustate, IR)); } static int check_condition_code(z8_state *cpustate, int cc) { @@ -545,22 +545,22 @@ static int check_condition_code(z8_state *cpustate, int cc) switch (cc) { - case CC_F: truth = 0; break; - case CC_LT: truth = flag(S) ^ flag(V); break; - case CC_LE: truth = (flag(Z) | (flag(S) ^ flag(V))); break; - case CC_ULE: truth = flag(C) | flag(Z); break; - case CC_OV: truth = flag(V); break; - case CC_MI: truth = flag(S); break; - case CC_Z: truth = flag(Z); break; - case CC_C: truth = flag(C); break; - case CC_T: truth = 1; break; - case CC_GE: truth = !(flag(S) ^ flag(V)); break; - case CC_GT: truth = !(flag(Z) | (flag(S) ^ flag(V))); break; - case CC_UGT: truth = ((!flag(C)) & (!flag(Z))); break; - case CC_NOV: truth = !flag(V); break; - case CC_PL: truth = !flag(S); break; - case CC_NZ: truth = !flag(Z); break; - case CC_NC: truth = !flag(C); break; + case CC_F: truth = 0; break; + case CC_LT: truth = flag(S) ^ flag(V); break; + case CC_LE: truth = (flag(Z) | (flag(S) ^ flag(V))); break; + case CC_ULE: truth = flag(C) | flag(Z); break; + case CC_OV: truth = flag(V); break; + case CC_MI: truth = flag(S); break; + case CC_Z: truth = flag(Z); break; + case CC_C: truth = flag(C); break; + case CC_T: truth = 1; break; + case CC_GE: truth = !(flag(S) ^ flag(V)); break; + case CC_GT: truth = !(flag(Z) | (flag(S) ^ flag(V))); break; + case CC_UGT: truth = ((!flag(C)) & (!flag(Z))); break; + case CC_NOV: truth = !flag(V); break; + case CC_PL: truth = !flag(S); break; + case CC_NZ: truth = !flag(Z); break; + case CC_NC: truth = !flag(C); break; } return truth; @@ -605,12 +605,12 @@ static void test_complement_under_mask(z8_state *cpustate, UINT8 dst, UINT8 src) set_flag_v(0); } -INSTRUCTION( tcm_r1_r2 ) { mode_r1_r2(test_complement_under_mask) } -INSTRUCTION( tcm_r1_Ir2 ) { mode_r1_Ir2(test_complement_under_mask) } -INSTRUCTION( tcm_R2_R1 ) { mode_R2_R1(test_complement_under_mask) } -INSTRUCTION( tcm_IR2_R1 ) { mode_IR2_R1(test_complement_under_mask) } -INSTRUCTION( tcm_R1_IM ) { mode_R1_IM(test_complement_under_mask) } -INSTRUCTION( tcm_IR1_IM ) { mode_IR1_IM(test_complement_under_mask) } +INSTRUCTION( tcm_r1_r2 ) { mode_r1_r2(test_complement_under_mask) } +INSTRUCTION( tcm_r1_Ir2 ) { mode_r1_Ir2(test_complement_under_mask) } +INSTRUCTION( tcm_R2_R1 ) { mode_R2_R1(test_complement_under_mask) } +INSTRUCTION( tcm_IR2_R1 ) { mode_IR2_R1(test_complement_under_mask) } +INSTRUCTION( tcm_R1_IM ) { mode_R1_IM(test_complement_under_mask) } +INSTRUCTION( tcm_IR1_IM ) { mode_IR1_IM(test_complement_under_mask) } static void test_under_mask(z8_state *cpustate, UINT8 dst, UINT8 src) { @@ -622,12 +622,12 @@ static void test_under_mask(z8_state *cpustate, UINT8 dst, UINT8 src) set_flag_v(0); } -INSTRUCTION( tm_r1_r2 ) { mode_r1_r2(test_under_mask) } -INSTRUCTION( tm_r1_Ir2 ) { mode_r1_Ir2(test_under_mask) } -INSTRUCTION( tm_R2_R1 ) { mode_R2_R1(test_under_mask) } -INSTRUCTION( tm_IR2_R1 ) { mode_IR2_R1(test_under_mask) } -INSTRUCTION( tm_R1_IM ) { mode_R1_IM(test_under_mask) } -INSTRUCTION( tm_IR1_IM ) { mode_IR1_IM(test_under_mask) } +INSTRUCTION( tm_r1_r2 ) { mode_r1_r2(test_under_mask) } +INSTRUCTION( tm_r1_Ir2 ) { mode_r1_Ir2(test_under_mask) } +INSTRUCTION( tm_R2_R1 ) { mode_R2_R1(test_under_mask) } +INSTRUCTION( tm_IR2_R1 ) { mode_IR2_R1(test_under_mask) } +INSTRUCTION( tm_R1_IM ) { mode_R1_IM(test_under_mask) } +INSTRUCTION( tm_IR1_IM ) { mode_IR1_IM(test_under_mask) } /*************************************************************************** ROTATE AND SHIFT INSTRUCTIONS @@ -647,8 +647,8 @@ static void rotate_left(z8_state *cpustate, UINT8 dst) register_write(cpustate, dst, new_data); } -INSTRUCTION( rl_R1 ) { mode_R1(rotate_left) } -INSTRUCTION( rl_IR1 ) { mode_IR1(rotate_left) } +INSTRUCTION( rl_R1 ) { mode_R1(rotate_left) } +INSTRUCTION( rl_IR1 ) { mode_IR1(rotate_left) } static void rotate_left_carry(z8_state *cpustate, UINT8 dst) { @@ -664,8 +664,8 @@ static void rotate_left_carry(z8_state *cpustate, UINT8 dst) register_write(cpustate, dst, new_data); } -INSTRUCTION( rlc_R1 ) { mode_R1(rotate_left_carry) } -INSTRUCTION( rlc_IR1 ) { mode_IR1(rotate_left_carry) } +INSTRUCTION( rlc_R1 ) { mode_R1(rotate_left_carry) } +INSTRUCTION( rlc_IR1 ) { mode_IR1(rotate_left_carry) } static void rotate_right(z8_state *cpustate, UINT8 dst) { @@ -681,8 +681,8 @@ static void rotate_right(z8_state *cpustate, UINT8 dst) register_write(cpustate, dst, new_data); } -INSTRUCTION( rr_R1 ) { mode_R1(rotate_right) } -INSTRUCTION( rr_IR1 ) { mode_IR1(rotate_right) } +INSTRUCTION( rr_R1 ) { mode_R1(rotate_right) } +INSTRUCTION( rr_IR1 ) { mode_IR1(rotate_right) } static void rotate_right_carry(z8_state *cpustate, UINT8 dst) { @@ -698,8 +698,8 @@ static void rotate_right_carry(z8_state *cpustate, UINT8 dst) register_write(cpustate, dst, new_data); } -INSTRUCTION( rrc_R1 ) { mode_R1(rotate_right_carry) } -INSTRUCTION( rrc_IR1 ) { mode_IR1(rotate_right_carry) } +INSTRUCTION( rrc_R1 ) { mode_R1(rotate_right_carry) } +INSTRUCTION( rrc_IR1 ) { mode_IR1(rotate_right_carry) } static void shift_right_arithmetic(z8_state *cpustate, UINT8 dst) { @@ -715,8 +715,8 @@ static void shift_right_arithmetic(z8_state *cpustate, UINT8 dst) register_write(cpustate, dst, new_data); } -INSTRUCTION( sra_R1 ) { mode_R1(shift_right_arithmetic) } -INSTRUCTION( sra_IR1 ) { mode_IR1(shift_right_arithmetic) } +INSTRUCTION( sra_R1 ) { mode_R1(shift_right_arithmetic) } +INSTRUCTION( sra_IR1 ) { mode_IR1(shift_right_arithmetic) } static void swap(z8_state *cpustate, UINT8 dst) { @@ -730,17 +730,17 @@ static void swap(z8_state *cpustate, UINT8 dst) // set_flag_v(0); undefined } -INSTRUCTION( swap_R1 ) { mode_R1(swap) } -INSTRUCTION( swap_IR1 ) { mode_IR1(swap) } +INSTRUCTION( swap_R1 ) { mode_R1(swap) } +INSTRUCTION( swap_IR1 ) { mode_IR1(swap) } /*************************************************************************** CPU CONTROL INSTRUCTIONS ***************************************************************************/ -INSTRUCTION( ccf ) { cpustate->r[Z8_REGISTER_FLAGS] ^= Z8_FLAGS_C; } -INSTRUCTION( di ) { cpustate->r[Z8_REGISTER_IMR] &= ~Z8_IMR_ENABLE; } -INSTRUCTION( ei ) { cpustate->r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE; } -INSTRUCTION( nop ) { /* no operation */ } -INSTRUCTION( rcf ) { set_flag_c(0); } -INSTRUCTION( scf ) { set_flag_c(1); } -INSTRUCTION( srp_IM ) { cpustate->r[Z8_REGISTER_RP] = fetch(cpustate); } +INSTRUCTION( ccf ) { cpustate->r[Z8_REGISTER_FLAGS] ^= Z8_FLAGS_C; } +INSTRUCTION( di ) { cpustate->r[Z8_REGISTER_IMR] &= ~Z8_IMR_ENABLE; } +INSTRUCTION( ei ) { cpustate->r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE; } +INSTRUCTION( nop ) { /* no operation */ } +INSTRUCTION( rcf ) { set_flag_c(0); } +INSTRUCTION( scf ) { set_flag_c(1); } +INSTRUCTION( srp_IM ) { cpustate->r[Z8_REGISTER_RP] = fetch(cpustate); } |