diff options
Diffstat (limited to 'src/emu/cpu/upd7810/upd7810.c')
-rw-r--r-- | src/emu/cpu/upd7810/upd7810.c | 1280 |
1 files changed, 640 insertions, 640 deletions
diff --git a/src/emu/cpu/upd7810/upd7810.c b/src/emu/cpu/upd7810/upd7810.c index cc563879bc6..014e62fba9f 100644 --- a/src/emu/cpu/upd7810/upd7810.c +++ b/src/emu/cpu/upd7810/upd7810.c @@ -410,84 +410,84 @@ STOP 01001000 10111011 12 stop struct upd7810_state { - PAIR ppc; /* previous program counter */ - PAIR pc; /* program counter */ - PAIR sp; /* stack pointer */ - UINT8 op; /* opcode */ - UINT8 op2; /* opcode part 2 */ - UINT8 iff; /* interrupt enable flip flop */ - UINT8 psw; /* processor status word */ - PAIR ea; /* extended accumulator */ - PAIR va; /* accumulator + vector register */ - PAIR bc; /* 8bit B and C registers / 16bit BC register */ - PAIR de; /* 8bit D and E registers / 16bit DE register */ - PAIR hl; /* 8bit H and L registers / 16bit HL register */ - PAIR ea2; /* alternate register set */ - PAIR va2; - PAIR bc2; - PAIR de2; - PAIR hl2; - PAIR cnt; /* 8 bit timer counter */ - PAIR tm; /* 8 bit timer 0/1 comparator inputs */ - PAIR ecnt; /* timer counter register / capture register */ - PAIR etm; /* timer 0/1 comparator inputs */ - UINT8 ma; /* port A input or output mask */ - UINT8 mb; /* port B input or output mask */ - UINT8 mcc; /* port C control/port select */ - UINT8 mc; /* port C input or output mask */ - UINT8 mm; /* memory mapping */ - UINT8 mf; /* port F input or output mask */ - UINT8 tmm; /* timer 0 and timer 1 operating parameters */ - UINT8 etmm; /* 16-bit multifunction timer/event counter */ - UINT8 eom; /* 16-bit timer/event counter output control */ - UINT8 sml; /* serial interface parameters low */ - UINT8 smh; /* -"- high */ - UINT8 anm; /* analog to digital converter operating parameters */ - UINT8 mkl; /* interrupt mask low */ - UINT8 mkh; /* -"- high */ - UINT8 zcm; /* bias circuitry for ac zero-cross detection */ - UINT8 pa_in; /* port A,B,C,D,F inputs */ - UINT8 pb_in; - UINT8 pc_in; - UINT8 pd_in; - UINT8 pf_in; - UINT8 pa_out; /* port A,B,C,D,F outputs */ - UINT8 pb_out; - UINT8 pc_out; - UINT8 pd_out; - UINT8 pf_out; - UINT8 cr0; /* analog digital conversion register 0 */ - UINT8 cr1; /* analog digital conversion register 1 */ - UINT8 cr2; /* analog digital conversion register 2 */ - UINT8 cr3; /* analog digital conversion register 3 */ - UINT8 txb; /* transmitter buffer */ - UINT8 rxb; /* receiver buffer */ - UINT8 txd; /* port C control line states */ - UINT8 rxd; - UINT8 sck; - UINT8 ti; - UINT8 to; - UINT8 ci; - UINT8 co0; - UINT8 co1; - UINT16 irr; /* interrupt request register */ - UINT16 itf; /* interrupt test flag register */ - int int1; /* keep track of current int1 state. Needed for 7801 irq checking. */ - int int2; /* keep track to current int2 state. Needed for 7801 irq checking. */ + PAIR ppc; /* previous program counter */ + PAIR pc; /* program counter */ + PAIR sp; /* stack pointer */ + UINT8 op; /* opcode */ + UINT8 op2; /* opcode part 2 */ + UINT8 iff; /* interrupt enable flip flop */ + UINT8 psw; /* processor status word */ + PAIR ea; /* extended accumulator */ + PAIR va; /* accumulator + vector register */ + PAIR bc; /* 8bit B and C registers / 16bit BC register */ + PAIR de; /* 8bit D and E registers / 16bit DE register */ + PAIR hl; /* 8bit H and L registers / 16bit HL register */ + PAIR ea2; /* alternate register set */ + PAIR va2; + PAIR bc2; + PAIR de2; + PAIR hl2; + PAIR cnt; /* 8 bit timer counter */ + PAIR tm; /* 8 bit timer 0/1 comparator inputs */ + PAIR ecnt; /* timer counter register / capture register */ + PAIR etm; /* timer 0/1 comparator inputs */ + UINT8 ma; /* port A input or output mask */ + UINT8 mb; /* port B input or output mask */ + UINT8 mcc; /* port C control/port select */ + UINT8 mc; /* port C input or output mask */ + UINT8 mm; /* memory mapping */ + UINT8 mf; /* port F input or output mask */ + UINT8 tmm; /* timer 0 and timer 1 operating parameters */ + UINT8 etmm; /* 16-bit multifunction timer/event counter */ + UINT8 eom; /* 16-bit timer/event counter output control */ + UINT8 sml; /* serial interface parameters low */ + UINT8 smh; /* -"- high */ + UINT8 anm; /* analog to digital converter operating parameters */ + UINT8 mkl; /* interrupt mask low */ + UINT8 mkh; /* -"- high */ + UINT8 zcm; /* bias circuitry for ac zero-cross detection */ + UINT8 pa_in; /* port A,B,C,D,F inputs */ + UINT8 pb_in; + UINT8 pc_in; + UINT8 pd_in; + UINT8 pf_in; + UINT8 pa_out; /* port A,B,C,D,F outputs */ + UINT8 pb_out; + UINT8 pc_out; + UINT8 pd_out; + UINT8 pf_out; + UINT8 cr0; /* analog digital conversion register 0 */ + UINT8 cr1; /* analog digital conversion register 1 */ + UINT8 cr2; /* analog digital conversion register 2 */ + UINT8 cr3; /* analog digital conversion register 3 */ + UINT8 txb; /* transmitter buffer */ + UINT8 rxb; /* receiver buffer */ + UINT8 txd; /* port C control line states */ + UINT8 rxd; + UINT8 sck; + UINT8 ti; + UINT8 to; + UINT8 ci; + UINT8 co0; + UINT8 co1; + UINT16 irr; /* interrupt request register */ + UINT16 itf; /* interrupt test flag register */ + int int1; /* keep track of current int1 state. Needed for 7801 irq checking. */ + int int2; /* keep track to current int2 state. Needed for 7801 irq checking. */ /* internal helper variables */ - UINT16 txs; /* transmitter shift register */ - UINT16 rxs; /* receiver shift register */ - UINT8 txcnt; /* transmitter shift register bit count */ - UINT8 rxcnt; /* receiver shift register bit count */ - UINT8 txbuf; /* transmitter buffer was written */ - INT32 ovc0; /* overflow counter for timer 0 (for clock div 12/384) */ - INT32 ovc1; /* overflow counter for timer 0 (for clock div 12/384) */ - INT32 ovce; /* overflow counter for ecnt */ - INT32 ovcf; /* overflow counter for fixed clock div 3 mode */ - INT32 ovcs; /* overflow counter for serial I/O */ - UINT8 edges; /* rising/falling edge flag for serial I/O */ - const struct opcode_s *opXX; /* opcode table */ + UINT16 txs; /* transmitter shift register */ + UINT16 rxs; /* receiver shift register */ + UINT8 txcnt; /* transmitter shift register bit count */ + UINT8 rxcnt; /* receiver shift register bit count */ + UINT8 txbuf; /* transmitter buffer was written */ + INT32 ovc0; /* overflow counter for timer 0 (for clock div 12/384) */ + INT32 ovc1; /* overflow counter for timer 0 (for clock div 12/384) */ + INT32 ovce; /* overflow counter for ecnt */ + INT32 ovcf; /* overflow counter for fixed clock div 3 mode */ + INT32 ovcs; /* overflow counter for serial I/O */ + UINT8 edges; /* rising/falling edge flag for serial I/O */ + const struct opcode_s *opXX; /* opcode table */ const struct opcode_s *op48; const struct opcode_s *op4C; const struct opcode_s *op4D; @@ -509,130 +509,130 @@ INLINE upd7810_state *get_safe_token(device_t *device) { assert(device != NULL); assert(device->type() == UPD7810 || - device->type() == UPD7807 || - device->type() == UPD7801 || - device->type() == UPD78C05 || - device->type() == UPD78C06); + device->type() == UPD7807 || + device->type() == UPD7801 || + device->type() == UPD78C05 || + device->type() == UPD78C06); return (upd7810_state *)downcast<legacy_cpu_device *>(device)->token(); } -#define CY 0x01 -#define F1 0x02 -#define L0 0x04 -#define L1 0x08 -#define HC 0x10 -#define SK 0x20 -#define Z 0x40 -#define F7 0x80 +#define CY 0x01 +#define F1 0x02 +#define L0 0x04 +#define L1 0x08 +#define HC 0x10 +#define SK 0x20 +#define Z 0x40 +#define F7 0x80 /* IRR flags */ -#define INTNMI 0x0001 -#define INTFT0 0x0002 -#define INTFT1 0x0004 -#define INTF1 0x0008 -#define INTF2 0x0010 -#define INTFE0 0x0020 -#define INTFE1 0x0040 +#define INTNMI 0x0001 +#define INTFT0 0x0002 +#define INTFT1 0x0004 +#define INTF1 0x0008 +#define INTF2 0x0010 +#define INTFE0 0x0020 +#define INTFE1 0x0040 #define INTFEIN 0x0080 -#define INTFAD 0x0100 -#define INTFSR 0x0200 -#define INTFST 0x0400 -#define INTER 0x0800 -#define INTOV 0x1000 -#define INTF0 0x2000 +#define INTFAD 0x0100 +#define INTFSR 0x0200 +#define INTFST 0x0400 +#define INTER 0x0800 +#define INTOV 0x1000 +#define INTF0 0x2000 /* ITF flags */ -#define INTAN4 0x0001 -#define INTAN5 0x0002 -#define INTAN6 0x0004 -#define INTAN7 0x0008 -#define INTSB 0x0010 - -#define PPC cpustate->ppc.w.l -#define PC cpustate->pc.w.l -#define PCL cpustate->pc.b.l -#define PCH cpustate->pc.b.h -#define PCD cpustate->pc.d -#define SP cpustate->sp.w.l -#define SPL cpustate->sp.b.l -#define SPH cpustate->sp.b.h -#define SPD cpustate->sp.d -#define PSW cpustate->psw -#define OP cpustate->op -#define OP2 cpustate->op2 -#define IFF cpustate->iff -#define EA cpustate->ea.w.l -#define EAL cpustate->ea.b.l -#define EAH cpustate->ea.b.h -#define VA cpustate->va.w.l -#define V cpustate->va.b.h -#define A cpustate->va.b.l -#define VAD cpustate->va.d -#define BC cpustate->bc.w.l -#define B cpustate->bc.b.h -#define C cpustate->bc.b.l -#define DE cpustate->de.w.l -#define D cpustate->de.b.h -#define E cpustate->de.b.l -#define HL cpustate->hl.w.l -#define H cpustate->hl.b.h -#define L cpustate->hl.b.l -#define EA2 cpustate->ea2.w.l -#define VA2 cpustate->va2.w.l -#define BC2 cpustate->bc2.w.l -#define DE2 cpustate->de2.w.l -#define HL2 cpustate->hl2.w.l - -#define OVC0 cpustate->ovc0 -#define OVC1 cpustate->ovc1 -#define OVCE cpustate->ovce -#define OVCF cpustate->ovcf -#define OVCS cpustate->ovcs -#define EDGES cpustate->edges - -#define CNT0 cpustate->cnt.b.l -#define CNT1 cpustate->cnt.b.h -#define TM0 cpustate->tm.b.l -#define TM1 cpustate->tm.b.h -#define ECNT cpustate->ecnt.w.l -#define ECPT cpustate->ecnt.w.h -#define ETM0 cpustate->etm.w.l -#define ETM1 cpustate->etm.w.h - -#define MA cpustate->ma -#define MB cpustate->mb -#define MCC cpustate->mcc -#define MC cpustate->mc -#define MM cpustate->mm -#define MF cpustate->mf -#define TMM cpustate->tmm -#define ETMM cpustate->etmm -#define EOM cpustate->eom -#define SML cpustate->sml -#define SMH cpustate->smh -#define ANM cpustate->anm -#define MKL cpustate->mkl -#define MKH cpustate->mkh -#define ZCM cpustate->zcm - -#define CR0 cpustate->cr0 -#define CR1 cpustate->cr1 -#define CR2 cpustate->cr2 -#define CR3 cpustate->cr3 -#define RXB cpustate->rxb -#define TXB cpustate->txb - -#define RXD cpustate->rxd -#define TXD cpustate->txd -#define SCK cpustate->sck -#define TI cpustate->ti -#define TO cpustate->to -#define CI cpustate->ci -#define CO0 cpustate->co0 -#define CO1 cpustate->co1 - -#define IRR cpustate->irr -#define ITF cpustate->itf +#define INTAN4 0x0001 +#define INTAN5 0x0002 +#define INTAN6 0x0004 +#define INTAN7 0x0008 +#define INTSB 0x0010 + +#define PPC cpustate->ppc.w.l +#define PC cpustate->pc.w.l +#define PCL cpustate->pc.b.l +#define PCH cpustate->pc.b.h +#define PCD cpustate->pc.d +#define SP cpustate->sp.w.l +#define SPL cpustate->sp.b.l +#define SPH cpustate->sp.b.h +#define SPD cpustate->sp.d +#define PSW cpustate->psw +#define OP cpustate->op +#define OP2 cpustate->op2 +#define IFF cpustate->iff +#define EA cpustate->ea.w.l +#define EAL cpustate->ea.b.l +#define EAH cpustate->ea.b.h +#define VA cpustate->va.w.l +#define V cpustate->va.b.h +#define A cpustate->va.b.l +#define VAD cpustate->va.d +#define BC cpustate->bc.w.l +#define B cpustate->bc.b.h +#define C cpustate->bc.b.l +#define DE cpustate->de.w.l +#define D cpustate->de.b.h +#define E cpustate->de.b.l +#define HL cpustate->hl.w.l +#define H cpustate->hl.b.h +#define L cpustate->hl.b.l +#define EA2 cpustate->ea2.w.l +#define VA2 cpustate->va2.w.l +#define BC2 cpustate->bc2.w.l +#define DE2 cpustate->de2.w.l +#define HL2 cpustate->hl2.w.l + +#define OVC0 cpustate->ovc0 +#define OVC1 cpustate->ovc1 +#define OVCE cpustate->ovce +#define OVCF cpustate->ovcf +#define OVCS cpustate->ovcs +#define EDGES cpustate->edges + +#define CNT0 cpustate->cnt.b.l +#define CNT1 cpustate->cnt.b.h +#define TM0 cpustate->tm.b.l +#define TM1 cpustate->tm.b.h +#define ECNT cpustate->ecnt.w.l +#define ECPT cpustate->ecnt.w.h +#define ETM0 cpustate->etm.w.l +#define ETM1 cpustate->etm.w.h + +#define MA cpustate->ma +#define MB cpustate->mb +#define MCC cpustate->mcc +#define MC cpustate->mc +#define MM cpustate->mm +#define MF cpustate->mf +#define TMM cpustate->tmm +#define ETMM cpustate->etmm +#define EOM cpustate->eom +#define SML cpustate->sml +#define SMH cpustate->smh +#define ANM cpustate->anm +#define MKL cpustate->mkl +#define MKH cpustate->mkh +#define ZCM cpustate->zcm + +#define CR0 cpustate->cr0 +#define CR1 cpustate->cr1 +#define CR2 cpustate->cr2 +#define CR3 cpustate->cr3 +#define RXB cpustate->rxb +#define TXB cpustate->txb + +#define RXD cpustate->rxd +#define TXD cpustate->txd +#define SCK cpustate->sck +#define TI cpustate->ti +#define TO cpustate->to +#define CI cpustate->ci +#define CO0 cpustate->co0 +#define CO1 cpustate->co1 + +#define IRR cpustate->irr +#define ITF cpustate->itf struct opcode_s { void (*opfunc)(upd7810_state *cpustate); @@ -642,42 +642,42 @@ struct opcode_s { UINT8 mask_l0_l1; }; -#define RDOP(O) O = cpustate->direct->read_decrypted_byte(PCD); PC++ -#define RDOPARG(A) A = cpustate->direct->read_raw_byte(PCD); PC++ -#define RM(A) cpustate->program->read_byte(A) -#define WM(A,V) cpustate->program->write_byte(A,V) +#define RDOP(O) O = cpustate->direct->read_decrypted_byte(PCD); PC++ +#define RDOPARG(A) A = cpustate->direct->read_raw_byte(PCD); PC++ +#define RM(A) cpustate->program->read_byte(A) +#define WM(A,V) cpustate->program->write_byte(A,V) -#define ZHC_ADD(after,before,carry) \ +#define ZHC_ADD(after,before,carry) \ if (after == 0) PSW |= Z; else PSW &= ~Z; \ if (after == before) \ PSW = (PSW&~CY) | (carry); \ - else if (after < before) \ - PSW |= CY; \ - else \ - PSW &= ~CY; \ - if ((after & 15) < (before & 15)) \ - PSW |= HC; \ - else \ - PSW &= ~HC; \ - -#define ZHC_SUB(after,before,carry) \ + else if (after < before) \ + PSW |= CY; \ + else \ + PSW &= ~CY; \ + if ((after & 15) < (before & 15)) \ + PSW |= HC; \ + else \ + PSW &= ~HC; \ + +#define ZHC_SUB(after,before,carry) \ if (after == 0) PSW |= Z; else PSW &= ~Z; \ - if (before == after) \ - PSW = (PSW & ~CY) | (carry); \ - else if (after > before) \ - PSW |= CY; \ - else \ - PSW &= ~CY; \ - if ((after & 15) > (before & 15)) \ - PSW |= HC; \ - else \ - PSW &= ~HC; \ - -#define SKIP_CY if (CY == (PSW & CY)) PSW |= SK -#define SKIP_NC if (0 == (PSW & CY)) PSW |= SK -#define SKIP_Z if (Z == (PSW & Z)) PSW |= SK -#define SKIP_NZ if (0 == (PSW & Z)) PSW |= SK -#define SET_Z(n) if (n) PSW &= ~Z; else PSW |= Z + if (before == after) \ + PSW = (PSW & ~CY) | (carry); \ + else if (after > before) \ + PSW |= CY; \ + else \ + PSW &= ~CY; \ + if ((after & 15) > (before & 15)) \ + PSW |= HC; \ + else \ + PSW &= ~HC; \ + +#define SKIP_CY if (CY == (PSW & CY)) PSW |= SK +#define SKIP_NC if (0 == (PSW & CY)) PSW |= SK +#define SKIP_Z if (Z == (PSW & Z)) PSW |= SK +#define SKIP_NZ if (0 == (PSW & Z)) PSW |= SK +#define SET_Z(n) if (n) PSW &= ~Z; else PSW |= Z static UINT8 RP(upd7810_state *cpustate, offs_t port) { @@ -685,48 +685,48 @@ static UINT8 RP(upd7810_state *cpustate, offs_t port) switch (port) { case UPD7810_PORTA: - if (cpustate->ma) // NS20031301 no need to read if the port is set as output + if (cpustate->ma) // NS20031301 no need to read if the port is set as output cpustate->pa_in = cpustate->io->read_byte(port); data = (cpustate->pa_in & cpustate->ma) | (cpustate->pa_out & ~cpustate->ma); break; case UPD7810_PORTB: - if (cpustate->mb) // NS20031301 no need to read if the port is set as output + if (cpustate->mb) // NS20031301 no need to read if the port is set as output cpustate->pb_in = cpustate->io->read_byte(port); data = (cpustate->pb_in & cpustate->mb) | (cpustate->pb_out & ~cpustate->mb); break; case UPD7810_PORTC: - if (cpustate->mc) // NS20031301 no need to read if the port is set as output + if (cpustate->mc) // NS20031301 no need to read if the port is set as output cpustate->pc_in = cpustate->io->read_byte(port); data = (cpustate->pc_in & cpustate->mc) | (cpustate->pc_out & ~cpustate->mc); - if (cpustate->mcc & 0x01) /* PC0 = TxD output */ + if (cpustate->mcc & 0x01) /* PC0 = TxD output */ data = (data & ~0x01) | (cpustate->txd & 1 ? 0x01 : 0x00); - if (cpustate->mcc & 0x02) /* PC1 = RxD input */ + if (cpustate->mcc & 0x02) /* PC1 = RxD input */ data = (data & ~0x02) | (cpustate->rxd & 1 ? 0x02 : 0x00); - if (cpustate->mcc & 0x04) /* PC2 = SCK input/output */ + if (cpustate->mcc & 0x04) /* PC2 = SCK input/output */ data = (data & ~0x04) | (cpustate->sck & 1 ? 0x04 : 0x00); - if (cpustate->mcc & 0x08) /* PC3 = TI input */ + if (cpustate->mcc & 0x08) /* PC3 = TI input */ data = (data & ~0x08) | (cpustate->ti & 1 ? 0x08 : 0x00); - if (cpustate->mcc & 0x10) /* PC4 = TO output */ + if (cpustate->mcc & 0x10) /* PC4 = TO output */ data = (data & ~0x10) | (cpustate->to & 1 ? 0x10 : 0x00); - if (cpustate->mcc & 0x20) /* PC5 = CI input */ + if (cpustate->mcc & 0x20) /* PC5 = CI input */ data = (data & ~0x20) | (cpustate->ci & 1 ? 0x20 : 0x00); - if (cpustate->mcc & 0x40) /* PC6 = CO0 output */ + if (cpustate->mcc & 0x40) /* PC6 = CO0 output */ data = (data & ~0x40) | (cpustate->co0 & 1 ? 0x40 : 0x00); - if (cpustate->mcc & 0x80) /* PC7 = CO1 output */ + if (cpustate->mcc & 0x80) /* PC7 = CO1 output */ data = (data & ~0x80) | (cpustate->co1 & 1 ? 0x80 : 0x00); break; case UPD7810_PORTD: cpustate->pd_in = cpustate->io->read_byte(port); switch (cpustate->mm & 0x07) { - case 0x00: /* PD input mode, PF port mode */ + case 0x00: /* PD input mode, PF port mode */ data = cpustate->pd_in; break; - case 0x01: /* PD output mode, PF port mode */ + case 0x01: /* PD output mode, PF port mode */ data = cpustate->pd_out; break; - default: /* PD extension mode, PF port/extension mode */ - data = 0xff; /* what do we see on the port here? */ + default: /* PD extension mode, PF port/extension mode */ + data = 0xff; /* what do we see on the port here? */ break; } break; @@ -734,23 +734,23 @@ static UINT8 RP(upd7810_state *cpustate, offs_t port) cpustate->pf_in = cpustate->io->read_byte(port); switch (cpustate->mm & 0x06) { - case 0x00: /* PD input/output mode, PF port mode */ + case 0x00: /* PD input/output mode, PF port mode */ data = (cpustate->pf_in & cpustate->mf) | (cpustate->pf_out & ~cpustate->mf); break; - case 0x02: /* PD extension mode, PF0-3 extension mode, PF4-7 port mode */ + case 0x02: /* PD extension mode, PF0-3 extension mode, PF4-7 port mode */ data = (cpustate->pf_in & cpustate->mf) | (cpustate->pf_out & ~cpustate->mf); - data |= 0x0f; /* what would we see on the lower bits here? */ + data |= 0x0f; /* what would we see on the lower bits here? */ break; - case 0x04: /* PD extension mode, PF0-5 extension mode, PF6-7 port mode */ + case 0x04: /* PD extension mode, PF0-5 extension mode, PF6-7 port mode */ data = (cpustate->pf_in & cpustate->mf) | (cpustate->pf_out & ~cpustate->mf); - data |= 0x3f; /* what would we see on the lower bits here? */ + data |= 0x3f; /* what would we see on the lower bits here? */ break; case 0x06: - data = 0xff; /* what would we see on the lower bits here? */ + data = 0xff; /* what would we see on the lower bits here? */ break; } break; - case UPD7807_PORTT: // NS20031301 partial implementation + case UPD7807_PORTT: // NS20031301 partial implementation data = cpustate->io->read_byte(port); break; default: @@ -766,34 +766,34 @@ static void WP(upd7810_state *cpustate, offs_t port, UINT8 data) case UPD7810_PORTA: cpustate->pa_out = data; // data = (data & ~cpustate->ma) | (cpustate->pa_in & cpustate->ma); - data = (data & ~cpustate->ma) | (cpustate->ma); // NS20031401 + data = (data & ~cpustate->ma) | (cpustate->ma); // NS20031401 cpustate->io->write_byte(port, data); break; case UPD7810_PORTB: cpustate->pb_out = data; // data = (data & ~cpustate->mb) | (cpustate->pb_in & cpustate->mb); - data = (data & ~cpustate->mb) | (cpustate->mb); // NS20031401 + data = (data & ~cpustate->mb) | (cpustate->mb); // NS20031401 cpustate->io->write_byte(port, data); break; case UPD7810_PORTC: cpustate->pc_out = data; // data = (data & ~cpustate->mc) | (cpustate->pc_in & cpustate->mc); - data = (data & ~cpustate->mc) | (cpustate->mc); // NS20031401 - if (cpustate->mcc & 0x01) /* PC0 = TxD output */ + data = (data & ~cpustate->mc) | (cpustate->mc); // NS20031401 + if (cpustate->mcc & 0x01) /* PC0 = TxD output */ data = (data & ~0x01) | (cpustate->txd & 1 ? 0x01 : 0x00); - if (cpustate->mcc & 0x02) /* PC1 = RxD input */ + if (cpustate->mcc & 0x02) /* PC1 = RxD input */ data = (data & ~0x02) | (cpustate->rxd & 1 ? 0x02 : 0x00); - if (cpustate->mcc & 0x04) /* PC2 = SCK input/output */ + if (cpustate->mcc & 0x04) /* PC2 = SCK input/output */ data = (data & ~0x04) | (cpustate->sck & 1 ? 0x04 : 0x00); - if (cpustate->mcc & 0x08) /* PC3 = TI input */ + if (cpustate->mcc & 0x08) /* PC3 = TI input */ data = (data & ~0x08) | (cpustate->ti & 1 ? 0x08 : 0x00); - if (cpustate->mcc & 0x10) /* PC4 = TO output */ + if (cpustate->mcc & 0x10) /* PC4 = TO output */ data = (data & ~0x10) | (cpustate->to & 1 ? 0x10 : 0x00); - if (cpustate->mcc & 0x20) /* PC5 = CI input */ + if (cpustate->mcc & 0x20) /* PC5 = CI input */ data = (data & ~0x20) | (cpustate->ci & 1 ? 0x20 : 0x00); - if (cpustate->mcc & 0x40) /* PC6 = CO0 output */ + if (cpustate->mcc & 0x40) /* PC6 = CO0 output */ data = (data & ~0x40) | (cpustate->co0 & 1 ? 0x40 : 0x00); - if (cpustate->mcc & 0x80) /* PC7 = CO1 output */ + if (cpustate->mcc & 0x80) /* PC7 = CO1 output */ data = (data & ~0x80) | (cpustate->co1 & 1 ? 0x80 : 0x00); cpustate->io->write_byte(port, data); break; @@ -801,13 +801,13 @@ static void WP(upd7810_state *cpustate, offs_t port, UINT8 data) cpustate->pd_out = data; switch (cpustate->mm & 0x07) { - case 0x00: /* PD input mode, PF port mode */ + case 0x00: /* PD input mode, PF port mode */ data = cpustate->pd_in; break; - case 0x01: /* PD output mode, PF port mode */ + case 0x01: /* PD output mode, PF port mode */ data = cpustate->pd_out; break; - default: /* PD extension mode, PF port/extension mode */ + default: /* PD extension mode, PF port/extension mode */ return; } cpustate->io->write_byte(port, data); @@ -817,16 +817,16 @@ static void WP(upd7810_state *cpustate, offs_t port, UINT8 data) data = (data & ~cpustate->mf) | (cpustate->pf_in & cpustate->mf); switch (cpustate->mm & 0x06) { - case 0x00: /* PD input/output mode, PF port mode */ + case 0x00: /* PD input/output mode, PF port mode */ break; - case 0x02: /* PD extension mode, PF0-3 extension mode, PF4-7 port mode */ - data |= 0x0f; /* what would come out for the lower bits here? */ + case 0x02: /* PD extension mode, PF0-3 extension mode, PF4-7 port mode */ + data |= 0x0f; /* what would come out for the lower bits here? */ break; - case 0x04: /* PD extension mode, PF0-5 extension mode, PF6-7 port mode */ - data |= 0x3f; /* what would come out for the lower bits here? */ + case 0x04: /* PD extension mode, PF0-5 extension mode, PF6-7 port mode */ + data |= 0x3f; /* what would come out for the lower bits here? */ break; case 0x06: - data |= 0xff; /* what would come out for the lower bits here? */ + data |= 0xff; /* what would come out for the lower bits here? */ break; } cpustate->io->write_byte(port, data); @@ -886,9 +886,9 @@ static void upd7810_take_irq(upd7810_state *cpustate) default: /* check the interrupts in priority sequence */ - if ((IRR & INTFT0) && 0 == (MKL & 0x02)) + if ((IRR & INTFT0) && 0 == (MKL & 0x02)) { - switch (cpustate->config.type) + switch (cpustate->config.type) { case TYPE_7810_GAMEMASTER: vector = 0xff2a; @@ -896,13 +896,13 @@ static void upd7810_take_irq(upd7810_state *cpustate) default: vector = 0x0008; } - if (!((IRR & INTFT1) && 0 == (MKL & 0x04))) + if (!((IRR & INTFT1) && 0 == (MKL & 0x04))) IRR&=~INTFT0; } else - if ((IRR & INTFT1) && 0 == (MKL & 0x04)) + if ((IRR & INTFT1) && 0 == (MKL & 0x04)) { - switch (cpustate->config.type) + switch (cpustate->config.type) { case TYPE_7810_GAMEMASTER: vector = 0xff2a; @@ -910,27 +910,27 @@ static void upd7810_take_irq(upd7810_state *cpustate) default: vector = 0x0008; } - IRR&=~INTFT1; + IRR&=~INTFT1; } else - if ((IRR & INTF1) && 0 == (MKL & 0x08)) + if ((IRR & INTF1) && 0 == (MKL & 0x08)) { irqline = UPD7810_INTF1; vector = 0x0010; - if (!((IRR & INTF2) && 0 == (MKL & 0x10))) - IRR&=~INTF1; + if (!((IRR & INTF2) && 0 == (MKL & 0x10))) + IRR&=~INTF1; } else - if ((IRR & INTF2) && 0 == (MKL & 0x10)) + if ((IRR & INTF2) && 0 == (MKL & 0x10)) { irqline = UPD7810_INTF2; vector = 0x0010; IRR&=~INTF2; } else - if ((IRR & INTFE0) && 0 == (MKL & 0x20)) + if ((IRR & INTFE0) && 0 == (MKL & 0x20)) { - switch (cpustate->config.type) + switch (cpustate->config.type) { case TYPE_7810_GAMEMASTER: vector = 0xff2d; @@ -938,21 +938,21 @@ static void upd7810_take_irq(upd7810_state *cpustate) default: vector = 0x0018; } - if (!((IRR & INTFE1) && 0 == (MKL & 0x40))) + if (!((IRR & INTFE1) && 0 == (MKL & 0x40))) IRR&=~INTFE0; } else - if ((IRR & INTFE1) && 0 == (MKL & 0x40)) + if ((IRR & INTFE1) && 0 == (MKL & 0x40)) { - switch (cpustate->config.type) + switch (cpustate->config.type) { - case TYPE_7810_GAMEMASTER: + case TYPE_7810_GAMEMASTER: vector = 0xff2d; break; - default: + default: vector = 0x0018; } - IRR&=~INTFE1; + IRR&=~INTFE1; } else if ((IRR & INTFEIN) && 0 == (MKL & 0x80)) @@ -960,21 +960,21 @@ static void upd7810_take_irq(upd7810_state *cpustate) vector = 0x0020; } else - if ((IRR & INTFAD) && 0 == (MKH & 0x01)) + if ((IRR & INTFAD) && 0 == (MKH & 0x01)) { vector = 0x0020; } else - if ((IRR & INTFSR) && 0 == (MKH & 0x02)) + if ((IRR & INTFSR) && 0 == (MKH & 0x02)) { vector = 0x0028; - IRR&=~INTFSR; + IRR&=~INTFSR; } else - if ((IRR & INTFST) && 0 == (MKH & 0x04)) + if ((IRR & INTFST) && 0 == (MKH & 0x04)) { vector = 0x0028; - IRR&=~INTFST; + IRR&=~INTFST; } break; } @@ -1002,13 +1002,13 @@ static void upd7810_write_EOM(upd7810_state *cpustate) { switch (EOM & 0x0e) { - case 0x02: /* toggle CO0 */ + case 0x02: /* toggle CO0 */ CO0 = (CO0 >> 1) | ((CO0 ^ 2) & 2); break; - case 0x04: /* reset CO0 */ + case 0x04: /* reset CO0 */ CO0 = 0; break; - case 0x08: /* set CO0 */ + case 0x08: /* set CO0 */ CO0 = 1; break; } @@ -1017,13 +1017,13 @@ static void upd7810_write_EOM(upd7810_state *cpustate) { switch (EOM & 0xe0) { - case 0x20: /* toggle CO1 */ + case 0x20: /* toggle CO1 */ CO1 = (CO1 >> 1) | ((CO1 ^ 2) & 2); break; - case 0x40: /* reset CO1 */ + case 0x40: /* reset CO1 */ CO1 = 0; break; - case 0x80: /* set CO1 */ + case 0x80: /* set CO1 */ CO1 = 1; break; } @@ -1049,80 +1049,80 @@ static void upd7810_sio_output(upd7810_state *cpustate) cpustate->txs >>= 1; cpustate->txcnt--; if (0 == cpustate->txcnt) - IRR |= INTFST; /* serial transfer completed */ + IRR |= INTFST; /* serial transfer completed */ } else if (SMH & 0x04) /* send enable ? */ { /* nothing written into the transmitter buffer ? */ - if (0 == cpustate->txbuf) + if (0 == cpustate->txbuf) return; - cpustate->txbuf = 0; + cpustate->txbuf = 0; - if (SML & 0x03) /* asynchronous mode ? */ + if (SML & 0x03) /* asynchronous mode ? */ { switch (SML & 0xfc) { - case 0x48: /* 7bits, no parity, 1 stop bit */ - case 0x68: /* 7bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ + case 0x48: /* 7bits, no parity, 1 stop bit */ + case 0x68: /* 7bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ /* insert start bit in bit0, stop bit int bit8 */ cpustate->txs = (TXB << 1) | (1 << 8); cpustate->txcnt = 9; break; - case 0x4c: /* 8bits, no parity, 1 stop bit */ - case 0x6c: /* 8bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ + case 0x4c: /* 8bits, no parity, 1 stop bit */ + case 0x6c: /* 8bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ /* insert start bit in bit0, stop bit int bit9 */ cpustate->txs = (TXB << 1) | (1 << 9); cpustate->txcnt = 10; break; - case 0x58: /* 7bits, odd parity, 1 stop bit */ + case 0x58: /* 7bits, odd parity, 1 stop bit */ /* insert start bit in bit0, parity in bit 8, stop bit in bit9 */ cpustate->txs = (TXB << 1) | (PAR7(TXB) << 8) | (1 << 9); cpustate->txcnt = 10; break; - case 0x5c: /* 8bits, odd parity, 1 stop bit */ + case 0x5c: /* 8bits, odd parity, 1 stop bit */ /* insert start bit in bit0, parity in bit 9, stop bit int bit10 */ cpustate->txs = (TXB << 1) | (PAR8(TXB) << 9) | (1 << 10); cpustate->txcnt = 11; break; - case 0x78: /* 7bits, even parity, 1 stop bit */ + case 0x78: /* 7bits, even parity, 1 stop bit */ /* insert start bit in bit0, parity in bit 8, stop bit in bit9 */ cpustate->txs = (TXB << 1) | ((PAR7(TXB) ^ 1) << 8) | (1 << 9); cpustate->txcnt = 10; break; - case 0x7c: /* 8bits, even parity, 1 stop bit */ + case 0x7c: /* 8bits, even parity, 1 stop bit */ /* insert start bit in bit0, parity in bit 9, stop bit int bit10 */ cpustate->txs = (TXB << 1) | ((PAR8(TXB) ^ 1) << 9) | (1 << 10); cpustate->txcnt = 11; break; - case 0xc8: /* 7bits, no parity, 2 stop bits */ - case 0xe8: /* 7bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ + case 0xc8: /* 7bits, no parity, 2 stop bits */ + case 0xe8: /* 7bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ /* insert start bit in bit0, stop bits int bit8+9 */ cpustate->txs = (TXB << 1) | (3 << 8); cpustate->txcnt = 10; break; - case 0xcc: /* 8bits, no parity, 2 stop bits */ - case 0xec: /* 8bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ + case 0xcc: /* 8bits, no parity, 2 stop bits */ + case 0xec: /* 8bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ /* insert start bit in bit0, stop bits in bits9+10 */ cpustate->txs = (TXB << 1) | (3 << 9); cpustate->txcnt = 11; break; - case 0xd8: /* 7bits, odd parity, 2 stop bits */ + case 0xd8: /* 7bits, odd parity, 2 stop bits */ /* insert start bit in bit0, parity in bit 8, stop bits in bits9+10 */ cpustate->txs = (TXB << 1) | (PAR7(TXB) << 8) | (3 << 9); cpustate->txcnt = 11; break; - case 0xdc: /* 8bits, odd parity, 2 stop bits */ + case 0xdc: /* 8bits, odd parity, 2 stop bits */ /* insert start bit in bit0, parity in bit 9, stop bits int bit10+11 */ cpustate->txs = (TXB << 1) | (PAR8(TXB) << 9) | (3 << 10); cpustate->txcnt = 12; break; - case 0xf8: /* 7bits, even parity, 2 stop bits */ + case 0xf8: /* 7bits, even parity, 2 stop bits */ /* insert start bit in bit0, parity in bit 8, stop bits in bit9+10 */ cpustate->txs = (TXB << 1) | ((PAR7(TXB) ^ 1) << 8) | (3 << 9); cpustate->txcnt = 11; break; - case 0xfc: /* 8bits, even parity, 2 stop bits */ + case 0xfc: /* 8bits, even parity, 2 stop bits */ /* insert start bit in bit0, parity in bit 9, stop bits int bits10+10 */ cpustate->txs = (TXB << 1) | ((PAR8(TXB) ^ 1) << 9) | (1 << 10); cpustate->txcnt = 12; @@ -1154,105 +1154,105 @@ static void upd7810_sio_input(upd7810_state *cpustate) /* serial receive completed interrupt */ IRR |= INTFSR; /* now extract the data from the shift register */ - if (SML & 0x03) /* asynchronous mode ? */ + if (SML & 0x03) /* asynchronous mode ? */ { switch (SML & 0xfc) { - case 0x48: /* 7bits, no parity, 1 stop bit */ - case 0x68: /* 7bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ + case 0x48: /* 7bits, no parity, 1 stop bit */ + case 0x68: /* 7bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ cpustate->rxs >>= 16 - 9; RXB = (cpustate->rxs >> 1) & 0x7f; if ((1 << 8) != (cpustate->rxs & (1 | (1 << 8)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ break; - case 0x4c: /* 8bits, no parity, 1 stop bit */ - case 0x6c: /* 8bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ + case 0x4c: /* 8bits, no parity, 1 stop bit */ + case 0x6c: /* 8bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ cpustate->rxs >>= 16 - 10; RXB = (cpustate->rxs >> 1) & 0xff; if ((1 << 9) != (cpustate->rxs & (1 | (1 << 9)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ break; - case 0x58: /* 7bits, odd parity, 1 stop bit */ + case 0x58: /* 7bits, odd parity, 1 stop bit */ cpustate->rxs >>= 16 - 10; RXB = (cpustate->rxs >> 1) & 0x7f; if ((1 << 9) != (cpustate->rxs & (1 | (1 << 9)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ if (PAR7(RXB) != ((cpustate->rxs >> 8) & 1)) - IRR |= INTER; /* parity error */ + IRR |= INTER; /* parity error */ break; - case 0x5c: /* 8bits, odd parity, 1 stop bit */ + case 0x5c: /* 8bits, odd parity, 1 stop bit */ cpustate->rxs >>= 16 - 11; RXB = (cpustate->rxs >> 1) & 0xff; if ((1 << 10) != (cpustate->rxs & (1 | (1 << 10)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ if (PAR8(RXB) != ((cpustate->rxs >> 9) & 1)) - IRR |= INTER; /* parity error */ + IRR |= INTER; /* parity error */ break; - case 0x78: /* 7bits, even parity, 1 stop bit */ + case 0x78: /* 7bits, even parity, 1 stop bit */ cpustate->rxs >>= 16 - 10; RXB = (cpustate->rxs >> 1) & 0x7f; if ((1 << 9) != (cpustate->rxs & (1 | (1 << 9)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ if (PAR7(RXB) != ((cpustate->rxs >> 8) & 1)) - IRR |= INTER; /* parity error */ + IRR |= INTER; /* parity error */ break; - case 0x7c: /* 8bits, even parity, 1 stop bit */ + case 0x7c: /* 8bits, even parity, 1 stop bit */ cpustate->rxs >>= 16 - 11; RXB = (cpustate->rxs >> 1) & 0xff; if ((1 << 10) != (cpustate->rxs & (1 | (1 << 10)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ if (PAR8(RXB) != ((cpustate->rxs >> 9) & 1)) - IRR |= INTER; /* parity error */ + IRR |= INTER; /* parity error */ break; - case 0xc8: /* 7bits, no parity, 2 stop bits */ - case 0xe8: /* 7bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ + case 0xc8: /* 7bits, no parity, 2 stop bits */ + case 0xe8: /* 7bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ cpustate->rxs >>= 16 - 10; RXB = (cpustate->rxs >> 1) & 0x7f; if ((3 << 9) != (cpustate->rxs & (1 | (3 << 9)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ if (PAR7(RXB) != ((cpustate->rxs >> 8) & 1)) - IRR |= INTER; /* parity error */ + IRR |= INTER; /* parity error */ break; - case 0xcc: /* 8bits, no parity, 2 stop bits */ - case 0xec: /* 8bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ + case 0xcc: /* 8bits, no parity, 2 stop bits */ + case 0xec: /* 8bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ cpustate->rxs >>= 16 - 11; RXB = (cpustate->rxs >> 1) & 0xff; if ((3 << 10) != (cpustate->rxs & (1 | (3 << 10)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ if (PAR8(RXB) != ((cpustate->rxs >> 9) & 1)) - IRR |= INTER; /* parity error */ + IRR |= INTER; /* parity error */ break; - case 0xd8: /* 7bits, odd parity, 2 stop bits */ + case 0xd8: /* 7bits, odd parity, 2 stop bits */ cpustate->rxs >>= 16 - 11; RXB = (cpustate->rxs >> 1) & 0x7f; if ((3 << 10) != (cpustate->rxs & (1 | (3 << 10)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ if (PAR7(RXB) != ((cpustate->rxs >> 8) & 1)) - IRR |= INTER; /* parity error */ + IRR |= INTER; /* parity error */ break; - case 0xdc: /* 8bits, odd parity, 2 stop bits */ + case 0xdc: /* 8bits, odd parity, 2 stop bits */ cpustate->rxs >>= 16 - 12; RXB = (cpustate->rxs >> 1) & 0xff; if ((3 << 11) != (cpustate->rxs & (1 | (3 << 11)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ if (PAR8(RXB) != ((cpustate->rxs >> 9) & 1)) - IRR |= INTER; /* parity error */ + IRR |= INTER; /* parity error */ break; - case 0xf8: /* 7bits, even parity, 2 stop bits */ + case 0xf8: /* 7bits, even parity, 2 stop bits */ cpustate->rxs >>= 16 - 11; RXB = (cpustate->rxs >> 1) & 0x7f; if ((3 << 10) != (cpustate->rxs & (1 | (3 << 10)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ if (PAR7(RXB) != ((cpustate->rxs >> 8) & 1)) - IRR |= INTER; /* parity error */ + IRR |= INTER; /* parity error */ break; - case 0xfc: /* 8bits, even parity, 2 stop bits */ + case 0xfc: /* 8bits, even parity, 2 stop bits */ cpustate->rxs >>= 16 - 12; RXB = (cpustate->rxs >> 1) & 0xff; if ((3 << 11) != (cpustate->rxs & (1 | (3 << 11)))) - IRR |= INTER; /* framing error */ + IRR |= INTER; /* framing error */ if (PAR8(RXB) != ((cpustate->rxs >> 9) & 1)) - IRR |= INTER; /* parity error */ + IRR |= INTER; /* parity error */ break; } } @@ -1267,48 +1267,48 @@ static void upd7810_sio_input(upd7810_state *cpustate) else if (SMH & 0x08) /* receive enable ? */ { - if (SML & 0x03) /* asynchronous mode ? */ + if (SML & 0x03) /* asynchronous mode ? */ { switch (SML & 0xfc) { - case 0x48: /* 7bits, no parity, 1 stop bit */ - case 0x68: /* 7bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ + case 0x48: /* 7bits, no parity, 1 stop bit */ + case 0x68: /* 7bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ cpustate->rxcnt = 9; break; - case 0x4c: /* 8bits, no parity, 1 stop bit */ - case 0x6c: /* 8bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ + case 0x4c: /* 8bits, no parity, 1 stop bit */ + case 0x6c: /* 8bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ cpustate->rxcnt = 10; break; - case 0x58: /* 7bits, odd parity, 1 stop bit */ + case 0x58: /* 7bits, odd parity, 1 stop bit */ cpustate->rxcnt = 10; break; - case 0x5c: /* 8bits, odd parity, 1 stop bit */ + case 0x5c: /* 8bits, odd parity, 1 stop bit */ cpustate->rxcnt = 11; break; - case 0x78: /* 7bits, even parity, 1 stop bit */ + case 0x78: /* 7bits, even parity, 1 stop bit */ cpustate->rxcnt = 10; break; - case 0x7c: /* 8bits, even parity, 1 stop bit */ + case 0x7c: /* 8bits, even parity, 1 stop bit */ cpustate->rxcnt = 11; break; - case 0xc8: /* 7bits, no parity, 2 stop bits */ - case 0xe8: /* 7bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ + case 0xc8: /* 7bits, no parity, 2 stop bits */ + case 0xe8: /* 7bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ cpustate->rxcnt = 10; break; - case 0xcc: /* 8bits, no parity, 2 stop bits */ - case 0xec: /* 8bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ + case 0xcc: /* 8bits, no parity, 2 stop bits */ + case 0xec: /* 8bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ cpustate->rxcnt = 11; break; - case 0xd8: /* 7bits, odd parity, 2 stop bits */ + case 0xd8: /* 7bits, odd parity, 2 stop bits */ cpustate->rxcnt = 11; break; - case 0xdc: /* 8bits, odd parity, 2 stop bits */ + case 0xdc: /* 8bits, odd parity, 2 stop bits */ cpustate->rxcnt = 12; break; - case 0xf8: /* 7bits, even parity, 2 stop bits */ + case 0xf8: /* 7bits, even parity, 2 stop bits */ cpustate->rxcnt = 11; break; - case 0xfc: /* 8bits, even parity, 2 stop bits */ + case 0xfc: /* 8bits, even parity, 2 stop bits */ cpustate->rxcnt = 12; break; } @@ -1325,13 +1325,13 @@ static void upd7810_sio_input(upd7810_state *cpustate) static void upd7810_timers(upd7810_state *cpustate, int cycles) { /**** TIMER 0 ****/ - if (TMM & 0x10) /* timer 0 upcounter reset ? */ + if (TMM & 0x10) /* timer 0 upcounter reset ? */ CNT0 = 0; else { switch (TMM & 0x0c) /* timer 0 clock source */ { - case 0x00: /* clock divided by 12 */ + case 0x00: /* clock divided by 12 */ OVC0 += cycles; while (OVC0 >= 12) { @@ -1368,7 +1368,7 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) } } break; - case 0x04: /* clock divided by 384 */ + case 0x04: /* clock divided by 384 */ OVC0 += cycles; while (OVC0 >= 384) { @@ -1405,21 +1405,21 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) } } break; - case 0x08: /* external signal at TI */ + case 0x08: /* external signal at TI */ break; - case 0x0c: /* disabled */ + case 0x0c: /* disabled */ break; } } /**** TIMER 1 ****/ - if (TMM & 0x80) /* timer 1 upcounter reset ? */ + if (TMM & 0x80) /* timer 1 upcounter reset ? */ CNT1 = 0; else { switch (TMM & 0x60) /* timer 1 clock source */ { - case 0x00: /* clock divided by 12 */ + case 0x00: /* clock divided by 12 */ OVC1 += cycles; while (OVC1 >= 12) { @@ -1439,7 +1439,7 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) } } break; - case 0x20: /* clock divided by 384 */ + case 0x20: /* clock divided by 384 */ OVC1 += cycles; while (OVC1 >= 384) { @@ -1459,9 +1459,9 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) } } break; - case 0x40: /* external signal at TI */ + case 0x40: /* external signal at TI */ break; - case 0x60: /* clocked with timer 0 */ + case 0x60: /* clocked with timer 0 */ break; } } @@ -1495,69 +1495,69 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) ECNT++; switch (ETMM & 0x0c) { - case 0x00: /* clear ECNT */ + case 0x00: /* clear ECNT */ break; - case 0x04: /* free running */ + case 0x04: /* free running */ if (0 == ECNT) - ITF |= INTOV; /* set overflow flag if counter wrapped */ + ITF |= INTOV; /* set overflow flag if counter wrapped */ break; - case 0x08: /* reset at falling edge of CI or TO */ + case 0x08: /* reset at falling edge of CI or TO */ break; - case 0x0c: /* reset if ECNT == ETM1 */ + case 0x0c: /* reset if ECNT == ETM1 */ if (ETM1 == ECNT) ECNT = 0; break; } switch (ETMM & 0x30) { - case 0x00: /* set CO0 if ECNT == ETM0 */ + case 0x00: /* set CO0 if ECNT == ETM0 */ if (ETM0 == ECNT) { switch (EOM & 0x0e) { - case 0x02: /* toggle CO0 */ + case 0x02: /* toggle CO0 */ CO0 = (CO0 >> 1) | ((CO0 ^ 2) & 2); break; - case 0x04: /* reset CO0 */ + case 0x04: /* reset CO0 */ CO0 = 0; break; - case 0x08: /* set CO0 */ + case 0x08: /* set CO0 */ CO0 = 1; break; } } break; - case 0x10: /* prohibited */ + case 0x10: /* prohibited */ break; - case 0x20: /* set CO0 if ECNT == ETM0 or at falling CI input */ + case 0x20: /* set CO0 if ECNT == ETM0 or at falling CI input */ if (ETM0 == ECNT) { switch (EOM & 0x0e) { - case 0x02: /* toggle CO0 */ + case 0x02: /* toggle CO0 */ CO0 = (CO0 >> 1) | ((CO0 ^ 2) & 2); break; - case 0x04: /* reset CO0 */ + case 0x04: /* reset CO0 */ CO0 = 0; break; - case 0x08: /* set CO0 */ + case 0x08: /* set CO0 */ CO0 = 1; break; } } break; - case 0x30: /* latch CO0 if ECNT == ETM0 or ECNT == ETM1 */ + case 0x30: /* latch CO0 if ECNT == ETM0 or ECNT == ETM1 */ if (ETM0 == ECNT || ETM1 == ECNT) { switch (EOM & 0x0e) { - case 0x02: /* toggle CO0 */ + case 0x02: /* toggle CO0 */ CO0 = (CO0 >> 1) | ((CO0 ^ 2) & 2); break; - case 0x04: /* reset CO0 */ + case 0x04: /* reset CO0 */ CO0 = 0; break; - case 0x08: /* set CO0 */ + case 0x08: /* set CO0 */ CO0 = 1; break; } @@ -1566,54 +1566,54 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) } switch (ETMM & 0xc0) { - case 0x00: /* lacth CO1 if ECNT == ETM1 */ + case 0x00: /* lacth CO1 if ECNT == ETM1 */ if (ETM1 == ECNT) { switch (EOM & 0xe0) { - case 0x20: /* toggle CO1 */ + case 0x20: /* toggle CO1 */ CO1 = (CO1 >> 1) | ((CO1 ^ 2) & 2); break; - case 0x40: /* reset CO1 */ + case 0x40: /* reset CO1 */ CO1 = 0; break; - case 0x80: /* set CO1 */ + case 0x80: /* set CO1 */ CO1 = 1; break; } } break; - case 0x40: /* prohibited */ + case 0x40: /* prohibited */ break; - case 0x80: /* latch CO1 if ECNT == ETM1 or falling edge of CI input */ + case 0x80: /* latch CO1 if ECNT == ETM1 or falling edge of CI input */ if (ETM1 == ECNT) { switch (EOM & 0xe0) { - case 0x20: /* toggle CO1 */ + case 0x20: /* toggle CO1 */ CO1 = (CO1 >> 1) | ((CO1 ^ 2) & 2); break; - case 0x40: /* reset CO1 */ + case 0x40: /* reset CO1 */ CO1 = 0; break; - case 0x80: /* set CO1 */ + case 0x80: /* set CO1 */ CO1 = 1; break; } } break; - case 0xc0: /* latch CO1 if ECNT == ETM0 or ECNT == ETM1 */ + case 0xc0: /* latch CO1 if ECNT == ETM0 or ECNT == ETM1 */ if (ETM0 == ECNT || ETM1 == ECNT) { switch (EOM & 0xe0) { - case 0x20: /* toggle CO1 */ + case 0x20: /* toggle CO1 */ CO1 = (CO1 >> 1) | ((CO1 ^ 2) & 2); break; - case 0x40: /* reset CO1 */ + case 0x40: /* reset CO1 */ CO1 = 0; break; - case 0x80: /* set CO1 */ + case 0x80: /* set CO1 */ CO1 = 1; break; } @@ -1626,9 +1626,9 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) /**** SIO ****/ switch (SMH & 0x03) { - case 0x00: /* interval timer F/F */ + case 0x00: /* interval timer F/F */ break; - case 0x01: /* internal clock divided by 384 */ + case 0x01: /* internal clock divided by 384 */ OVCS += cycles; while (OVCS >= 384) { @@ -1639,7 +1639,7 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) upd7810_sio_output(cpustate); } break; - case 0x02: /* internal clock divided by 24 */ + case 0x02: /* internal clock divided by 24 */ OVCS += cycles; while (OVCS >= 24) { @@ -1806,7 +1806,7 @@ static CPU_RESET( upd7810 ) switch (cpustate->config.type) { case TYPE_7810_GAMEMASTER: - // needed for lcd screen/ram selection; might be internal in cpu and therefor not needed; 0x10 written in some games + // needed for lcd screen/ram selection; might be internal in cpu and therefor not needed; 0x10 written in some games MC = 0xff&~0x7; WP( cpustate, UPD7810_PORTC, 1 ); //hyper space PCD=0x8000; @@ -1841,7 +1841,7 @@ static CPU_RESET( upd7801 ) cpustate->op74 = op74_7801; cpustate->opXX = opXX_7801; cpustate->handle_timers = upd7801_timers; - MA = 0; /* Port A is output port on the uPD7801 */ + MA = 0; /* Port A is output port on the uPD7801 */ cpustate->ovc0 = 0; } @@ -1857,11 +1857,11 @@ static CPU_RESET( upd78c05 ) cpustate->op70 = op70_78c05; cpustate->op74 = op74_78c05; cpustate->opXX = opXX_78c05; - MA = 0; /* All outputs */ - MC = 0xFF; /* All inputs */ - V = 0xFF; /* The vector register is always pointing to FF00 */ + MA = 0; /* All outputs */ + MC = 0xFF; /* All inputs */ + V = 0xFF; /* The vector register is always pointing to FF00 */ cpustate->handle_timers = upd78c05_timers; - TM0 = 0xFF; /* Timer seems to be running from boot */ + TM0 = 0xFF; /* Timer seems to be running from boot */ cpustate->ovc0 = ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0; } @@ -1897,10 +1897,10 @@ static CPU_EXECUTE( upd7810 ) RDOP(OP); /* - * clear L0 and/or L1 flags for all opcodes except - * L0 for "MVI L,xx" or "LXI H,xxxx" - * L1 for "MVI A,xx" - */ + * clear L0 and/or L1 flags for all opcodes except + * L0 for "MVI L,xx" or "LXI H,xxxx" + * L1 for "MVI A,xx" + */ PSW &= ~cpustate->opXX[OP].mask_l0_l1; /* skip flag set and not SOFTI opcode? */ @@ -2057,65 +2057,65 @@ static CPU_SET_INFO( upd7810 ) switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTF1: set_irq_line(cpustate, UPD7810_INTF1, info->i); break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTF2: set_irq_line(cpustate, UPD7810_INTF2, info->i); break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTFE1: set_irq_line(cpustate, UPD7810_INTFE1, info->i); break; + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; + case CPUINFO_INT_INPUT_STATE + UPD7810_INTF1: set_irq_line(cpustate, UPD7810_INTF1, info->i); break; + case CPUINFO_INT_INPUT_STATE + UPD7810_INTF2: set_irq_line(cpustate, UPD7810_INTF2, info->i); break; + case CPUINFO_INT_INPUT_STATE + UPD7810_INTFE1: set_irq_line(cpustate, UPD7810_INTFE1, info->i); break; - case CPUINFO_INT_PC: PC = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_PC: PC = info->i; break; + case CPUINFO_INT_PC: PC = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_PC: PC = info->i; break; case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + UPD7810_SP: SP = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_PSW: PSW = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_A: A = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_V: V = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_EA: EA = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_VA: VA = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_BC: BC = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_DE: DE = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_HL: HL = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_EA2: EA2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_VA2: VA2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_BC2: BC2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_DE2: DE2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_HL2: HL2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CNT0: CNT0 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CNT1: CNT1 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TM0: TM0 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TM1: TM1 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ECNT: ECNT = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ECPT: ECPT = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ETM0: ETM0 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ETM1: ETM1 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MA: MA = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MB: MB = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MCC: MCC = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MC: MC = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MM: MM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MF: MF = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TMM: TMM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ETMM: ETMM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_EOM: EOM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_SML: SML = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_SMH: SMH = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ANM: ANM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MKL: MKL = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MKH: MKH = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ZCM: ZCM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TXB: TXB = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_RXB: RXB = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CR0: CR0 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CR1: CR1 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CR2: CR2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CR3: CR3 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TXD: TXD = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_RXD: RXD = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_SCK: SCK = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TI: TI = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TO: TO = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CI: CI = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CO0: CO0 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CO1: CO1 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_SP: SP = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_PSW: PSW = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_A: A = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_V: V = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_EA: EA = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_VA: VA = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_BC: BC = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_DE: DE = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_HL: HL = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_EA2: EA2 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_VA2: VA2 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_BC2: BC2 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_DE2: DE2 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_HL2: HL2 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_CNT0: CNT0 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_CNT1: CNT1 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_TM0: TM0 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_TM1: TM1 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_ECNT: ECNT = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_ECPT: ECPT = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_ETM0: ETM0 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_ETM1: ETM1 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_MA: MA = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_MB: MB = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_MCC: MCC = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_MC: MC = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_MM: MM = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_MF: MF = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_TMM: TMM = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_ETMM: ETMM = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_EOM: EOM = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_SML: SML = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_SMH: SMH = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_ANM: ANM = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_MKL: MKL = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_MKH: MKH = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_ZCM: ZCM = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_TXB: TXB = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_RXB: RXB = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_CR0: CR0 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_CR1: CR1 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_CR2: CR2 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_CR3: CR3 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_TXD: TXD = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_RXD: RXD = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_SCK: SCK = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_TI: TI = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_TO: TO = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_CI: CI = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_CO0: CO0 = info->i; break; + case CPUINFO_INT_REGISTER + UPD7810_CO1: CO1 = info->i; break; } } @@ -2131,103 +2131,103 @@ CPU_GET_INFO( upd7810 ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(upd7810_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 2; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 40; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = (IRR & INTNMI) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTF1: info->i = (IRR & INTF1) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTF2: info->i = (IRR & INTF2) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTFE1: info->i = (IRR & INTFE1) ? ASSERT_LINE : CLEAR_LINE; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = PPC; break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(upd7810_state); break; + case CPUINFO_INT_INPUT_LINES: info->i = 2; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 40; break; + + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; + + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = (IRR & INTNMI) ? ASSERT_LINE : CLEAR_LINE; break; + case CPUINFO_INT_INPUT_STATE + UPD7810_INTF1: info->i = (IRR & INTF1) ? ASSERT_LINE : CLEAR_LINE; break; + case CPUINFO_INT_INPUT_STATE + UPD7810_INTF2: info->i = (IRR & INTF2) ? ASSERT_LINE : CLEAR_LINE; break; + case CPUINFO_INT_INPUT_STATE + UPD7810_INTFE1: info->i = (IRR & INTFE1) ? ASSERT_LINE : CLEAR_LINE; break; + + case CPUINFO_INT_PREVIOUSPC: info->i = PPC; break; case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + UPD7810_PC: info->i = PC; break; + case CPUINFO_INT_REGISTER + UPD7810_PC: info->i = PC; break; case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + UPD7810_SP: info->i = SP; break; - case CPUINFO_INT_REGISTER + UPD7810_PSW: info->i = PSW; break; - case CPUINFO_INT_REGISTER + UPD7810_EA: info->i = EA; break; - case CPUINFO_INT_REGISTER + UPD7810_VA: info->i = VA; break; - case CPUINFO_INT_REGISTER + UPD7810_BC: info->i = BC; break; - case CPUINFO_INT_REGISTER + UPD7810_DE: info->i = DE; break; - case CPUINFO_INT_REGISTER + UPD7810_HL: info->i = HL; break; - case CPUINFO_INT_REGISTER + UPD7810_EA2: info->i = EA2; break; - case CPUINFO_INT_REGISTER + UPD7810_VA2: info->i = VA2; break; - case CPUINFO_INT_REGISTER + UPD7810_BC2: info->i = BC2; break; - case CPUINFO_INT_REGISTER + UPD7810_DE2: info->i = DE2; break; - case CPUINFO_INT_REGISTER + UPD7810_HL2: info->i = HL2; break; - case CPUINFO_INT_REGISTER + UPD7810_CNT0: info->i = CNT0; break; - case CPUINFO_INT_REGISTER + UPD7810_CNT1: info->i = CNT1; break; - case CPUINFO_INT_REGISTER + UPD7810_TM0: info->i = TM0; break; - case CPUINFO_INT_REGISTER + UPD7810_TM1: info->i = TM1; break; - case CPUINFO_INT_REGISTER + UPD7810_ECNT: info->i = ECNT; break; - case CPUINFO_INT_REGISTER + UPD7810_ECPT: info->i = ECPT; break; - case CPUINFO_INT_REGISTER + UPD7810_ETM0: info->i = ETM0; break; - case CPUINFO_INT_REGISTER + UPD7810_ETM1: info->i = ETM1; break; - case CPUINFO_INT_REGISTER + UPD7810_MA: info->i = MA; break; - case CPUINFO_INT_REGISTER + UPD7810_MB: info->i = MB; break; - case CPUINFO_INT_REGISTER + UPD7810_MCC: info->i = MCC; break; - case CPUINFO_INT_REGISTER + UPD7810_MC: info->i = MC; break; - case CPUINFO_INT_REGISTER + UPD7810_MM: info->i = MM; break; - case CPUINFO_INT_REGISTER + UPD7810_MF: info->i = MF; break; - case CPUINFO_INT_REGISTER + UPD7810_TMM: info->i = TMM; break; - case CPUINFO_INT_REGISTER + UPD7810_ETMM: info->i = ETMM; break; - case CPUINFO_INT_REGISTER + UPD7810_EOM: info->i = EOM; break; - case CPUINFO_INT_REGISTER + UPD7810_SML: info->i = SML; break; - case CPUINFO_INT_REGISTER + UPD7810_SMH: info->i = SMH; break; - case CPUINFO_INT_REGISTER + UPD7810_ANM: info->i = ANM; break; - case CPUINFO_INT_REGISTER + UPD7810_MKL: info->i = MKL; break; - case CPUINFO_INT_REGISTER + UPD7810_MKH: info->i = MKH; break; - case CPUINFO_INT_REGISTER + UPD7810_ZCM: info->i = ZCM; break; - case CPUINFO_INT_REGISTER + UPD7810_TXB: info->i = TXB; break; - case CPUINFO_INT_REGISTER + UPD7810_RXB: info->i = RXB; break; - case CPUINFO_INT_REGISTER + UPD7810_CR0: info->i = CR0; break; - case CPUINFO_INT_REGISTER + UPD7810_CR1: info->i = CR1; break; - case CPUINFO_INT_REGISTER + UPD7810_CR2: info->i = CR2; break; - case CPUINFO_INT_REGISTER + UPD7810_CR3: info->i = CR3; break; - case CPUINFO_INT_REGISTER + UPD7810_TXD: info->i = TXD; break; - case CPUINFO_INT_REGISTER + UPD7810_RXD: info->i = RXD; break; - case CPUINFO_INT_REGISTER + UPD7810_SCK: info->i = SCK; break; - case CPUINFO_INT_REGISTER + UPD7810_TI: info->i = TI; break; - case CPUINFO_INT_REGISTER + UPD7810_TO: info->i = TO; break; - case CPUINFO_INT_REGISTER + UPD7810_CI: info->i = CI; break; - case CPUINFO_INT_REGISTER + UPD7810_CO0: info->i = CO0; break; - case CPUINFO_INT_REGISTER + UPD7810_CO1: info->i = CO1; break; + case CPUINFO_INT_REGISTER + UPD7810_SP: info->i = SP; break; + case CPUINFO_INT_REGISTER + UPD7810_PSW: info->i = PSW; break; + case CPUINFO_INT_REGISTER + UPD7810_EA: info->i = EA; break; + case CPUINFO_INT_REGISTER + UPD7810_VA: info->i = VA; break; + case CPUINFO_INT_REGISTER + UPD7810_BC: info->i = BC; break; + case CPUINFO_INT_REGISTER + UPD7810_DE: info->i = DE; break; + case CPUINFO_INT_REGISTER + UPD7810_HL: info->i = HL; break; + case CPUINFO_INT_REGISTER + UPD7810_EA2: info->i = EA2; break; + case CPUINFO_INT_REGISTER + UPD7810_VA2: info->i = VA2; break; + case CPUINFO_INT_REGISTER + UPD7810_BC2: info->i = BC2; break; + case CPUINFO_INT_REGISTER + UPD7810_DE2: info->i = DE2; break; + case CPUINFO_INT_REGISTER + UPD7810_HL2: info->i = HL2; break; + case CPUINFO_INT_REGISTER + UPD7810_CNT0: info->i = CNT0; break; + case CPUINFO_INT_REGISTER + UPD7810_CNT1: info->i = CNT1; break; + case CPUINFO_INT_REGISTER + UPD7810_TM0: info->i = TM0; break; + case CPUINFO_INT_REGISTER + UPD7810_TM1: info->i = TM1; break; + case CPUINFO_INT_REGISTER + UPD7810_ECNT: info->i = ECNT; break; + case CPUINFO_INT_REGISTER + UPD7810_ECPT: info->i = ECPT; break; + case CPUINFO_INT_REGISTER + UPD7810_ETM0: info->i = ETM0; break; + case CPUINFO_INT_REGISTER + UPD7810_ETM1: info->i = ETM1; break; + case CPUINFO_INT_REGISTER + UPD7810_MA: info->i = MA; break; + case CPUINFO_INT_REGISTER + UPD7810_MB: info->i = MB; break; + case CPUINFO_INT_REGISTER + UPD7810_MCC: info->i = MCC; break; + case CPUINFO_INT_REGISTER + UPD7810_MC: info->i = MC; break; + case CPUINFO_INT_REGISTER + UPD7810_MM: info->i = MM; break; + case CPUINFO_INT_REGISTER + UPD7810_MF: info->i = MF; break; + case CPUINFO_INT_REGISTER + UPD7810_TMM: info->i = TMM; break; + case CPUINFO_INT_REGISTER + UPD7810_ETMM: info->i = ETMM; break; + case CPUINFO_INT_REGISTER + UPD7810_EOM: info->i = EOM; break; + case CPUINFO_INT_REGISTER + UPD7810_SML: info->i = SML; break; + case CPUINFO_INT_REGISTER + UPD7810_SMH: info->i = SMH; break; + case CPUINFO_INT_REGISTER + UPD7810_ANM: info->i = ANM; break; + case CPUINFO_INT_REGISTER + UPD7810_MKL: info->i = MKL; break; + case CPUINFO_INT_REGISTER + UPD7810_MKH: info->i = MKH; break; + case CPUINFO_INT_REGISTER + UPD7810_ZCM: info->i = ZCM; break; + case CPUINFO_INT_REGISTER + UPD7810_TXB: info->i = TXB; break; + case CPUINFO_INT_REGISTER + UPD7810_RXB: info->i = RXB; break; + case CPUINFO_INT_REGISTER + UPD7810_CR0: info->i = CR0; break; + case CPUINFO_INT_REGISTER + UPD7810_CR1: info->i = CR1; break; + case CPUINFO_INT_REGISTER + UPD7810_CR2: info->i = CR2; break; + case CPUINFO_INT_REGISTER + UPD7810_CR3: info->i = CR3; break; + case CPUINFO_INT_REGISTER + UPD7810_TXD: info->i = TXD; break; + case CPUINFO_INT_REGISTER + UPD7810_RXD: info->i = RXD; break; + case CPUINFO_INT_REGISTER + UPD7810_SCK: info->i = SCK; break; + case CPUINFO_INT_REGISTER + UPD7810_TI: info->i = TI; break; + case CPUINFO_INT_REGISTER + UPD7810_TO: info->i = TO; break; + case CPUINFO_INT_REGISTER + UPD7810_CI: info->i = CI; break; + case CPUINFO_INT_REGISTER + UPD7810_CO0: info->i = CO0; break; + case CPUINFO_INT_REGISTER + UPD7810_CO1: info->i = CO1; break; /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(upd7810); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(upd7810); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd7810); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(upd7810); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(upd7810); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd7810); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(upd7810); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(upd7810); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd7810); break; + case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(upd7810); break; + case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(upd7810); break; + case CPUINFO_FCT_BURN: info->burn = NULL; break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd7810); break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "uPD7810"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "NEC uPD7810"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "0.3"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller, all rights reserved."); break; + case CPUINFO_STR_NAME: strcpy(info->s, "uPD7810"); break; + case CPUINFO_STR_FAMILY: strcpy(info->s, "NEC uPD7810"); break; + case CPUINFO_STR_VERSION: strcpy(info->s, "0.3"); break; + case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller, all rights reserved."); break; case CPUINFO_STR_FLAGS: sprintf(info->s, "%s:%s:%s:%s:%s:%s", @@ -2239,58 +2239,58 @@ CPU_GET_INFO( upd7810 ) cpustate->psw & 0x01 ? "CY":"--"); break; - case CPUINFO_STR_REGISTER + UPD7810_PC: sprintf(info->s, "PC :%04X", cpustate->pc.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_SP: sprintf(info->s, "SP :%04X", cpustate->sp.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_PSW: sprintf(info->s, "PSW :%02X", cpustate->psw); break; - case CPUINFO_STR_REGISTER + UPD7810_A: sprintf(info->s, "A :%02X", cpustate->va.b.l); break; - case CPUINFO_STR_REGISTER + UPD7810_V: sprintf(info->s, "V :%02X", cpustate->va.b.h); break; - case CPUINFO_STR_REGISTER + UPD7810_EA: sprintf(info->s, "EA :%04X", cpustate->ea.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_BC: sprintf(info->s, "BC :%04X", cpustate->bc.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_DE: sprintf(info->s, "DE :%04X", cpustate->de.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_HL: sprintf(info->s, "HL :%04X", cpustate->hl.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_A2: sprintf(info->s, "A' :%02X", cpustate->va2.b.l); break; - case CPUINFO_STR_REGISTER + UPD7810_V2: sprintf(info->s, "V' :%02X", cpustate->va2.b.h); break; - case CPUINFO_STR_REGISTER + UPD7810_EA2: sprintf(info->s, "EA' :%04X", cpustate->ea2.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_BC2: sprintf(info->s, "BC' :%04X", cpustate->bc2.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_DE2: sprintf(info->s, "DE' :%04X", cpustate->de2.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_HL2: sprintf(info->s, "HL' :%04X", cpustate->hl2.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_CNT0: sprintf(info->s, "CNT0:%02X", cpustate->cnt.b.l); break; - case CPUINFO_STR_REGISTER + UPD7810_CNT1: sprintf(info->s, "CNT1:%02X", cpustate->cnt.b.h); break; - case CPUINFO_STR_REGISTER + UPD7810_TM0: sprintf(info->s, "TM0 :%02X", cpustate->tm.b.l); break; - case CPUINFO_STR_REGISTER + UPD7810_TM1: sprintf(info->s, "TM1 :%02X", cpustate->tm.b.h); break; - case CPUINFO_STR_REGISTER + UPD7810_ECNT: sprintf(info->s, "ECNT:%04X", cpustate->ecnt.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_ECPT: sprintf(info->s, "ECPT:%04X", cpustate->ecnt.w.h); break; - case CPUINFO_STR_REGISTER + UPD7810_ETM0: sprintf(info->s, "ETM0:%04X", cpustate->etm.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_ETM1: sprintf(info->s, "ETM1:%04X", cpustate->etm.w.h); break; - case CPUINFO_STR_REGISTER + UPD7810_MA: sprintf(info->s, "MA :%02X", cpustate->ma); break; - case CPUINFO_STR_REGISTER + UPD7810_MB: sprintf(info->s, "MB :%02X", cpustate->mb); break; - case CPUINFO_STR_REGISTER + UPD7810_MCC: sprintf(info->s, "MCC :%02X", cpustate->mcc); break; - case CPUINFO_STR_REGISTER + UPD7810_MC: sprintf(info->s, "MC :%02X", cpustate->mc); break; - case CPUINFO_STR_REGISTER + UPD7810_MM: sprintf(info->s, "MM :%02X", cpustate->mm); break; - case CPUINFO_STR_REGISTER + UPD7810_MF: sprintf(info->s, "MF :%02X", cpustate->mf); break; - case CPUINFO_STR_REGISTER + UPD7810_TMM: sprintf(info->s, "TMM :%02X", cpustate->tmm); break; - case CPUINFO_STR_REGISTER + UPD7810_ETMM: sprintf(info->s, "ETMM:%02X", cpustate->etmm); break; - case CPUINFO_STR_REGISTER + UPD7810_EOM: sprintf(info->s, "EOM :%02X", cpustate->eom); break; - case CPUINFO_STR_REGISTER + UPD7810_SML: sprintf(info->s, "SML :%02X", cpustate->sml); break; - case CPUINFO_STR_REGISTER + UPD7810_SMH: sprintf(info->s, "SMH :%02X", cpustate->smh); break; - case CPUINFO_STR_REGISTER + UPD7810_ANM: sprintf(info->s, "ANM :%02X", cpustate->anm); break; - case CPUINFO_STR_REGISTER + UPD7810_MKL: sprintf(info->s, "MKL :%02X", cpustate->mkl); break; - case CPUINFO_STR_REGISTER + UPD7810_MKH: sprintf(info->s, "MKH :%02X", cpustate->mkh); break; - case CPUINFO_STR_REGISTER + UPD7810_ZCM: sprintf(info->s, "ZCM :%02X", cpustate->zcm); break; - case CPUINFO_STR_REGISTER + UPD7810_CR0: sprintf(info->s, "CR0 :%02X", cpustate->cr0); break; - case CPUINFO_STR_REGISTER + UPD7810_CR1: sprintf(info->s, "CR1 :%02X", cpustate->cr1); break; - case CPUINFO_STR_REGISTER + UPD7810_CR2: sprintf(info->s, "CR2 :%02X", cpustate->cr2); break; - case CPUINFO_STR_REGISTER + UPD7810_CR3: sprintf(info->s, "CR3 :%02X", cpustate->cr3); break; - case CPUINFO_STR_REGISTER + UPD7810_RXB: sprintf(info->s, "RXB :%02X", cpustate->rxb); break; - case CPUINFO_STR_REGISTER + UPD7810_TXB: sprintf(info->s, "TXB :%02X", cpustate->txb); break; - case CPUINFO_STR_REGISTER + UPD7810_TXD: sprintf(info->s, "TXD :%d", cpustate->txd); break; - case CPUINFO_STR_REGISTER + UPD7810_RXD: sprintf(info->s, "RXD :%d", cpustate->rxd); break; - case CPUINFO_STR_REGISTER + UPD7810_SCK: sprintf(info->s, "SCK :%d", cpustate->sck); break; - case CPUINFO_STR_REGISTER + UPD7810_TI: sprintf(info->s, "TI :%d", cpustate->ti); break; - case CPUINFO_STR_REGISTER + UPD7810_TO: sprintf(info->s, "TO :%d", cpustate->to); break; - case CPUINFO_STR_REGISTER + UPD7810_CI: sprintf(info->s, "CI :%d", cpustate->ci); break; - case CPUINFO_STR_REGISTER + UPD7810_CO0: sprintf(info->s, "CO0 :%d", cpustate->co0 & 1); break; - case CPUINFO_STR_REGISTER + UPD7810_CO1: sprintf(info->s, "CO1 :%d", cpustate->co1 & 1); break; + case CPUINFO_STR_REGISTER + UPD7810_PC: sprintf(info->s, "PC :%04X", cpustate->pc.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_SP: sprintf(info->s, "SP :%04X", cpustate->sp.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_PSW: sprintf(info->s, "PSW :%02X", cpustate->psw); break; + case CPUINFO_STR_REGISTER + UPD7810_A: sprintf(info->s, "A :%02X", cpustate->va.b.l); break; + case CPUINFO_STR_REGISTER + UPD7810_V: sprintf(info->s, "V :%02X", cpustate->va.b.h); break; + case CPUINFO_STR_REGISTER + UPD7810_EA: sprintf(info->s, "EA :%04X", cpustate->ea.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_BC: sprintf(info->s, "BC :%04X", cpustate->bc.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_DE: sprintf(info->s, "DE :%04X", cpustate->de.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_HL: sprintf(info->s, "HL :%04X", cpustate->hl.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_A2: sprintf(info->s, "A' :%02X", cpustate->va2.b.l); break; + case CPUINFO_STR_REGISTER + UPD7810_V2: sprintf(info->s, "V' :%02X", cpustate->va2.b.h); break; + case CPUINFO_STR_REGISTER + UPD7810_EA2: sprintf(info->s, "EA' :%04X", cpustate->ea2.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_BC2: sprintf(info->s, "BC' :%04X", cpustate->bc2.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_DE2: sprintf(info->s, "DE' :%04X", cpustate->de2.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_HL2: sprintf(info->s, "HL' :%04X", cpustate->hl2.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_CNT0: sprintf(info->s, "CNT0:%02X", cpustate->cnt.b.l); break; + case CPUINFO_STR_REGISTER + UPD7810_CNT1: sprintf(info->s, "CNT1:%02X", cpustate->cnt.b.h); break; + case CPUINFO_STR_REGISTER + UPD7810_TM0: sprintf(info->s, "TM0 :%02X", cpustate->tm.b.l); break; + case CPUINFO_STR_REGISTER + UPD7810_TM1: sprintf(info->s, "TM1 :%02X", cpustate->tm.b.h); break; + case CPUINFO_STR_REGISTER + UPD7810_ECNT: sprintf(info->s, "ECNT:%04X", cpustate->ecnt.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_ECPT: sprintf(info->s, "ECPT:%04X", cpustate->ecnt.w.h); break; + case CPUINFO_STR_REGISTER + UPD7810_ETM0: sprintf(info->s, "ETM0:%04X", cpustate->etm.w.l); break; + case CPUINFO_STR_REGISTER + UPD7810_ETM1: sprintf(info->s, "ETM1:%04X", cpustate->etm.w.h); break; + case CPUINFO_STR_REGISTER + UPD7810_MA: sprintf(info->s, "MA :%02X", cpustate->ma); break; + case CPUINFO_STR_REGISTER + UPD7810_MB: sprintf(info->s, "MB :%02X", cpustate->mb); break; + case CPUINFO_STR_REGISTER + UPD7810_MCC: sprintf(info->s, "MCC :%02X", cpustate->mcc); break; + case CPUINFO_STR_REGISTER + UPD7810_MC: sprintf(info->s, "MC :%02X", cpustate->mc); break; + case CPUINFO_STR_REGISTER + UPD7810_MM: sprintf(info->s, "MM :%02X", cpustate->mm); break; + case CPUINFO_STR_REGISTER + UPD7810_MF: sprintf(info->s, "MF :%02X", cpustate->mf); break; + case CPUINFO_STR_REGISTER + UPD7810_TMM: sprintf(info->s, "TMM :%02X", cpustate->tmm); break; + case CPUINFO_STR_REGISTER + UPD7810_ETMM: sprintf(info->s, "ETMM:%02X", cpustate->etmm); break; + case CPUINFO_STR_REGISTER + UPD7810_EOM: sprintf(info->s, "EOM :%02X", cpustate->eom); break; + case CPUINFO_STR_REGISTER + UPD7810_SML: sprintf(info->s, "SML :%02X", cpustate->sml); break; + case CPUINFO_STR_REGISTER + UPD7810_SMH: sprintf(info->s, "SMH :%02X", cpustate->smh); break; + case CPUINFO_STR_REGISTER + UPD7810_ANM: sprintf(info->s, "ANM :%02X", cpustate->anm); break; + case CPUINFO_STR_REGISTER + UPD7810_MKL: sprintf(info->s, "MKL :%02X", cpustate->mkl); break; + case CPUINFO_STR_REGISTER + UPD7810_MKH: sprintf(info->s, "MKH :%02X", cpustate->mkh); break; + case CPUINFO_STR_REGISTER + UPD7810_ZCM: sprintf(info->s, "ZCM :%02X", cpustate->zcm); break; + case CPUINFO_STR_REGISTER + UPD7810_CR0: sprintf(info->s, "CR0 :%02X", cpustate->cr0); break; + case CPUINFO_STR_REGISTER + UPD7810_CR1: sprintf(info->s, "CR1 :%02X", cpustate->cr1); break; + case CPUINFO_STR_REGISTER + UPD7810_CR2: sprintf(info->s, "CR2 :%02X", cpustate->cr2); break; + case CPUINFO_STR_REGISTER + UPD7810_CR3: sprintf(info->s, "CR3 :%02X", cpustate->cr3); break; + case CPUINFO_STR_REGISTER + UPD7810_RXB: sprintf(info->s, "RXB :%02X", cpustate->rxb); break; + case CPUINFO_STR_REGISTER + UPD7810_TXB: sprintf(info->s, "TXB :%02X", cpustate->txb); break; + case CPUINFO_STR_REGISTER + UPD7810_TXD: sprintf(info->s, "TXD :%d", cpustate->txd); break; + case CPUINFO_STR_REGISTER + UPD7810_RXD: sprintf(info->s, "RXD :%d", cpustate->rxd); break; + case CPUINFO_STR_REGISTER + UPD7810_SCK: sprintf(info->s, "SCK :%d", cpustate->sck); break; + case CPUINFO_STR_REGISTER + UPD7810_TI: sprintf(info->s, "TI :%d", cpustate->ti); break; + case CPUINFO_STR_REGISTER + UPD7810_TO: sprintf(info->s, "TO :%d", cpustate->to); break; + case CPUINFO_STR_REGISTER + UPD7810_CI: sprintf(info->s, "CI :%d", cpustate->ci); break; + case CPUINFO_STR_REGISTER + UPD7810_CO0: sprintf(info->s, "CO0 :%d", cpustate->co0 & 1); break; + case CPUINFO_STR_REGISTER + UPD7810_CO1: sprintf(info->s, "CO1 :%d", cpustate->co1 & 1); break; } } @@ -2304,35 +2304,35 @@ CPU_GET_INFO( upd7807 ) switch (state) { /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd7807); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd7807); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd7807); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd7807); break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "uPD7807"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "uPD7807"); break; - default: CPU_GET_INFO_CALL(upd7810); break; + default: CPU_GET_INFO_CALL(upd7810); break; } } CPU_GET_INFO( upd7801 ) { switch( state ) { - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd7801); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd7801); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd7801); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd7801); break; - case CPUINFO_STR_NAME: strcpy(info->s, "uPD7801"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "uPD7801"); break; - default: CPU_GET_INFO_CALL(upd7810); break; + default: CPU_GET_INFO_CALL(upd7810); break; } } CPU_GET_INFO( upd78c05 ) { switch ( state ) { - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 4; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 4; break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd78c05); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd78c05); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd78c05); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd78c05); break; - case CPUINFO_STR_NAME: strcpy(info->s, "uPD78C05"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "uPD78C05"); break; /* These registers are not present in the uPD78C05 cpu */ case CPUINFO_STR_REGISTER + UPD7810_A2: @@ -2366,19 +2366,19 @@ CPU_GET_INFO( upd78c05 ) { case CPUINFO_STR_REGISTER + UPD7810_TO: case CPUINFO_STR_REGISTER + UPD7810_CI: case CPUINFO_STR_REGISTER + UPD7810_CO0: - case CPUINFO_STR_REGISTER + UPD7810_CO1: break; + case CPUINFO_STR_REGISTER + UPD7810_CO1: break; - default: CPU_GET_INFO_CALL(upd7801); break; + default: CPU_GET_INFO_CALL(upd7801); break; } } CPU_GET_INFO( upd78c06 ) { switch ( state ) { - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd78c06); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd78c06); break; - case CPUINFO_STR_NAME: strcpy(info->s, "uPD78C06"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "uPD78C06"); break; - default: CPU_GET_INFO_CALL(upd78c05); break; + default: CPU_GET_INFO_CALL(upd78c05); break; } } |