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Diffstat (limited to 'src/emu/cpu/tms34010/tms34010.h')
-rw-r--r--src/emu/cpu/tms34010/tms34010.h86
1 files changed, 43 insertions, 43 deletions
diff --git a/src/emu/cpu/tms34010/tms34010.h b/src/emu/cpu/tms34010/tms34010.h
index 79147b9fe01..c93ddbd5609 100644
--- a/src/emu/cpu/tms34010/tms34010.h
+++ b/src/emu/cpu/tms34010/tms34010.h
@@ -107,30 +107,30 @@ enum
REG020_HSBLNK,
REG020_VTOTAL,
REG020_HTOTAL,
- REG020_DPYCTL, /* matches 010 */
- REG020_DPYSTRT, /* matches 010 */
- REG020_DPYINT, /* matches 010 */
- REG020_CONTROL, /* matches 010 */
- REG020_HSTDATA, /* matches 010 */
- REG020_HSTADRL, /* matches 010 */
- REG020_HSTADRH, /* matches 010 */
- REG020_HSTCTLL, /* matches 010 */
-
- REG020_HSTCTLH, /* matches 010 */
- REG020_INTENB, /* matches 010 */
- REG020_INTPEND, /* matches 010 */
- REG020_CONVSP, /* matches 010 */
- REG020_CONVDP, /* matches 010 */
- REG020_PSIZE, /* matches 010 */
+ REG020_DPYCTL, /* matches 010 */
+ REG020_DPYSTRT, /* matches 010 */
+ REG020_DPYINT, /* matches 010 */
+ REG020_CONTROL, /* matches 010 */
+ REG020_HSTDATA, /* matches 010 */
+ REG020_HSTADRL, /* matches 010 */
+ REG020_HSTADRH, /* matches 010 */
+ REG020_HSTCTLL, /* matches 010 */
+
+ REG020_HSTCTLH, /* matches 010 */
+ REG020_INTENB, /* matches 010 */
+ REG020_INTPEND, /* matches 010 */
+ REG020_CONVSP, /* matches 010 */
+ REG020_CONVDP, /* matches 010 */
+ REG020_PSIZE, /* matches 010 */
REG020_PMASKL,
REG020_PMASKH,
REG020_CONVMP,
REG020_CONTROL2,
REG020_CONFIG,
- REG020_DPYTAP, /* matches 010 */
+ REG020_DPYTAP, /* matches 010 */
REG020_VCOUNT,
REG020_HCOUNT,
- REG020_DPYADR, /* matches 010 */
+ REG020_DPYADR, /* matches 010 */
REG020_REFADR,
REG020_DPYSTL,
@@ -169,36 +169,36 @@ enum
};
/* Interrupts that are generated by the processor internally */
-#define TMS34010_INT1 0x0002 /* External Interrupt 1 */
-#define TMS34010_INT2 0x0004 /* External Interrupt 2 */
-#define TMS34010_HI 0x0200 /* Host Interrupt */
-#define TMS34010_DI 0x0400 /* Display Interrupt */
-#define TMS34010_WV 0x0800 /* Window Violation Interrupt */
+#define TMS34010_INT1 0x0002 /* External Interrupt 1 */
+#define TMS34010_INT2 0x0004 /* External Interrupt 2 */
+#define TMS34010_HI 0x0200 /* Host Interrupt */
+#define TMS34010_DI 0x0400 /* Display Interrupt */
+#define TMS34010_WV 0x0800 /* Window Violation Interrupt */
/* Configuration structure */
struct tms34010_display_params
{
- UINT16 vcount; /* most recent VCOUNT */
- UINT16 veblnk, vsblnk; /* start/end of VBLANK */
- UINT16 heblnk, hsblnk; /* start/end of HBLANK */
- UINT16 rowaddr, coladdr; /* row/column addresses */
- UINT8 yoffset; /* y offset from addresses */
- UINT8 enabled; /* video enabled */
+ UINT16 vcount; /* most recent VCOUNT */
+ UINT16 veblnk, vsblnk; /* start/end of VBLANK */
+ UINT16 heblnk, hsblnk; /* start/end of HBLANK */
+ UINT16 rowaddr, coladdr; /* row/column addresses */
+ UINT8 yoffset; /* y offset from addresses */
+ UINT8 enabled; /* video enabled */
};
struct tms34010_config
{
- UINT8 halt_on_reset; /* /HCS pin, which determines HALT state after reset */
- const char *screen_tag; /* the screen operated on */
- UINT32 pixclock; /* the pixel clock (0 means don't adjust screen size) */
- int pixperclock; /* pixels per clock */
- void (*scanline_callback_ind16)(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);
- void (*scanline_callback_rgb32)(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params);
- void (*output_int)(device_t *device, int state); /* output interrupt callback */
- void (*to_shiftreg)(address_space &space, offs_t, UINT16 *); /* shift register write */
- void (*from_shiftreg)(address_space &space, offs_t, UINT16 *); /* shift register read */
+ UINT8 halt_on_reset; /* /HCS pin, which determines HALT state after reset */
+ const char *screen_tag; /* the screen operated on */
+ UINT32 pixclock; /* the pixel clock (0 means don't adjust screen size) */
+ int pixperclock; /* pixels per clock */
+ void (*scanline_callback_ind16)(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);
+ void (*scanline_callback_rgb32)(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params);
+ void (*output_int)(device_t *device, int state); /* output interrupt callback */
+ void (*to_shiftreg)(address_space &space, offs_t, UINT16 *); /* shift register write */
+ void (*from_shiftreg)(address_space &space, offs_t, UINT16 *); /* shift register read */
};
@@ -212,13 +212,13 @@ DECLARE_LEGACY_CPU_DEVICE(TMS34020, tms34020);
/* Host control interface */
-#define TMS34010_HOST_ADDRESS_L 0
-#define TMS34010_HOST_ADDRESS_H 1
-#define TMS34010_HOST_DATA 2
-#define TMS34010_HOST_CONTROL 3
+#define TMS34010_HOST_ADDRESS_L 0
+#define TMS34010_HOST_ADDRESS_H 1
+#define TMS34010_HOST_DATA 2
+#define TMS34010_HOST_CONTROL 3
-void tms34010_host_w(device_t *cpu, int reg, int data);
-int tms34010_host_r(device_t *cpu, int reg);
+void tms34010_host_w(device_t *cpu, int reg, int data);
+int tms34010_host_r(device_t *cpu, int reg);
/* Reads & writes to the 34010 I/O registers; place at 0xc0000000 */