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Diffstat (limited to 'src/emu/cpu/tms32051/tms32051.c')
-rw-r--r--src/emu/cpu/tms32051/tms32051.c440
1 files changed, 220 insertions, 220 deletions
diff --git a/src/emu/cpu/tms32051/tms32051.c b/src/emu/cpu/tms32051/tms32051.c
index 9ae5294329e..de961c1c70f 100644
--- a/src/emu/cpu/tms32051/tms32051.c
+++ b/src/emu/cpu/tms32051/tms32051.c
@@ -8,15 +8,15 @@
#include "debugger.h"
#include "tms32051.h"
-#define INTERRUPT_INT1 0
-#define INTERRUPT_INT2 1
-#define INTERRUPT_INT3 2
-#define INTERRUPT_TINT 3
-#define INTERRUPT_RINT 4
-#define INTERRUPT_XINT 5
-#define INTERRUPT_TRNT 6
-#define INTERRUPT_TXNT 7
-#define INTERRUPT_INT4 8
+#define INTERRUPT_INT1 0
+#define INTERRUPT_INT2 1
+#define INTERRUPT_INT3 2
+#define INTERRUPT_TINT 3
+#define INTERRUPT_RINT 4
+#define INTERRUPT_XINT 5
+#define INTERRUPT_TRNT 6
+#define INTERRUPT_TXNT 7
+#define INTERRUPT_INT4 8
enum
{
@@ -162,9 +162,9 @@ static void restore_interrupt_context(tms32051_state *cpustate);
static void check_interrupts(tms32051_state *cpustate);
-#define CYCLES(x) (cpustate->icount -= x)
+#define CYCLES(x) (cpustate->icount -= x)
-#define ROPCODE(cpustate) cpustate->direct->read_decrypted_word((cpustate->pc++) << 1)
+#define ROPCODE(cpustate) cpustate->direct->read_decrypted_word((cpustate->pc++) << 1)
INLINE void CHANGE_PC(tms32051_state *cpustate, UINT16 new_pc)
{
@@ -235,31 +235,31 @@ static CPU_RESET( tms )
tms32051_state *cpustate = get_safe_token(device);
// reset registers
- cpustate->st0.intm = 1;
- cpustate->st0.ov = 0;
- cpustate->st1.c = 1;
- cpustate->st1.cnf = 0;
- cpustate->st1.hm = 1;
- cpustate->st1.pm = 0;
- cpustate->st1.sxm = 1;
- cpustate->st1.xf = 1;
- cpustate->pmst.avis = 0;
- cpustate->pmst.braf = 0;
- cpustate->pmst.iptr = 0;
- cpustate->pmst.ndx = 0;
- cpustate->pmst.ovly = 0;
- cpustate->pmst.ram = 0;
- cpustate->pmst.mpmc = 0; // TODO: this is set to logical pin state at reset
- cpustate->pmst.trm = 0;
- cpustate->ifr = 0;
- cpustate->cbcr = 0;
- cpustate->rptc = -1;
+ cpustate->st0.intm = 1;
+ cpustate->st0.ov = 0;
+ cpustate->st1.c = 1;
+ cpustate->st1.cnf = 0;
+ cpustate->st1.hm = 1;
+ cpustate->st1.pm = 0;
+ cpustate->st1.sxm = 1;
+ cpustate->st1.xf = 1;
+ cpustate->pmst.avis = 0;
+ cpustate->pmst.braf = 0;
+ cpustate->pmst.iptr = 0;
+ cpustate->pmst.ndx = 0;
+ cpustate->pmst.ovly = 0;
+ cpustate->pmst.ram = 0;
+ cpustate->pmst.mpmc = 0; // TODO: this is set to logical pin state at reset
+ cpustate->pmst.trm = 0;
+ cpustate->ifr = 0;
+ cpustate->cbcr = 0;
+ cpustate->rptc = -1;
// simulate internal rom boot loader (can be removed when the dsp rom(s) is dumped)
- cpustate->st0.intm = 1;
- cpustate->st1.cnf = 1;
- cpustate->pmst.ram = 1;
- cpustate->pmst.ovly = 0;
+ cpustate->st0.intm = 1;
+ cpustate->st1.cnf = 1;
+ cpustate->pmst.ram = 1;
+ cpustate->pmst.ovly = 0;
int i;
UINT16 src, dst, length;
@@ -303,14 +303,14 @@ static void check_interrupts(tms32051_state *cpustate)
static void save_interrupt_context(tms32051_state *cpustate)
{
- cpustate->shadow.acc = cpustate->acc;
- cpustate->shadow.accb = cpustate->accb;
- cpustate->shadow.arcr = cpustate->arcr;
- cpustate->shadow.indx = cpustate->indx;
- cpustate->shadow.preg = cpustate->preg;
- cpustate->shadow.treg0 = cpustate->treg0;
- cpustate->shadow.treg1 = cpustate->treg1;
- cpustate->shadow.treg2 = cpustate->treg2;
+ cpustate->shadow.acc = cpustate->acc;
+ cpustate->shadow.accb = cpustate->accb;
+ cpustate->shadow.arcr = cpustate->arcr;
+ cpustate->shadow.indx = cpustate->indx;
+ cpustate->shadow.preg = cpustate->preg;
+ cpustate->shadow.treg0 = cpustate->treg0;
+ cpustate->shadow.treg1 = cpustate->treg1;
+ cpustate->shadow.treg2 = cpustate->treg2;
memcpy(&cpustate->shadow.pmst, &cpustate->pmst, sizeof(PMST));
memcpy(&cpustate->shadow.st0, &cpustate->st0, sizeof(ST0));
memcpy(&cpustate->shadow.st1, &cpustate->st1, sizeof(ST1));
@@ -318,14 +318,14 @@ static void save_interrupt_context(tms32051_state *cpustate)
static void restore_interrupt_context(tms32051_state *cpustate)
{
- cpustate->acc = cpustate->shadow.acc;
- cpustate->accb = cpustate->shadow.accb;
- cpustate->arcr = cpustate->shadow.arcr;
- cpustate->indx = cpustate->shadow.indx;
- cpustate->preg = cpustate->shadow.preg;
- cpustate->treg0 = cpustate->shadow.treg0;
- cpustate->treg1 = cpustate->shadow.treg1;
- cpustate->treg2 = cpustate->shadow.treg2;
+ cpustate->acc = cpustate->shadow.acc;
+ cpustate->accb = cpustate->shadow.accb;
+ cpustate->arcr = cpustate->shadow.arcr;
+ cpustate->indx = cpustate->shadow.indx;
+ cpustate->preg = cpustate->shadow.preg;
+ cpustate->treg0 = cpustate->shadow.treg0;
+ cpustate->treg1 = cpustate->shadow.treg1;
+ cpustate->treg2 = cpustate->shadow.treg2;
memcpy(&cpustate->pmst, &cpustate->shadow.pmst, sizeof(PMST));
memcpy(&cpustate->st0, &cpustate->shadow.st0, sizeof(ST0));
memcpy(&cpustate->st1, &cpustate->shadow.st1, sizeof(ST1));
@@ -417,10 +417,10 @@ static READ16_HANDLER( cpuregs_r )
switch (offset)
{
- case 0x04: return cpustate->imr;
- case 0x06: return cpustate->ifr;
+ case 0x04: return cpustate->imr;
+ case 0x06: return cpustate->ifr;
- case 0x07: // PMST
+ case 0x07: // PMST
{
UINT16 r = 0;
r |= cpustate->pmst.iptr << 11;
@@ -434,21 +434,21 @@ static READ16_HANDLER( cpuregs_r )
return r;
}
- case 0x09: return cpustate->brcr;
- case 0x10: return cpustate->ar[0];
- case 0x11: return cpustate->ar[1];
- case 0x12: return cpustate->ar[2];
- case 0x13: return cpustate->ar[3];
- case 0x14: return cpustate->ar[4];
- case 0x15: return cpustate->ar[5];
- case 0x16: return cpustate->ar[6];
- case 0x17: return cpustate->ar[7];
- case 0x1e: return cpustate->cbcr;
- case 0x1f: return cpustate->bmar;
- case 0x24: return cpustate->timer.tim;
- case 0x25: return cpustate->timer.prd;
-
- case 0x26: // TCR
+ case 0x09: return cpustate->brcr;
+ case 0x10: return cpustate->ar[0];
+ case 0x11: return cpustate->ar[1];
+ case 0x12: return cpustate->ar[2];
+ case 0x13: return cpustate->ar[3];
+ case 0x14: return cpustate->ar[4];
+ case 0x15: return cpustate->ar[5];
+ case 0x16: return cpustate->ar[6];
+ case 0x17: return cpustate->ar[7];
+ case 0x1e: return cpustate->cbcr;
+ case 0x1f: return cpustate->bmar;
+ case 0x24: return cpustate->timer.tim;
+ case 0x25: return cpustate->timer.prd;
+
+ case 0x26: // TCR
{
UINT16 r = 0;
r |= (cpustate->timer.psc & 0xf) << 6;
@@ -456,7 +456,7 @@ static READ16_HANDLER( cpuregs_r )
return r;
}
- case 0x28: return 0; // PDWSR
+ case 0x28: return 0; // PDWSR
default:
if(!space.debugger_access())
fatalerror("32051: cpuregs_r: unimplemented memory-mapped register %02X at %04X\n", offset, cpustate->pc-1);
@@ -471,9 +471,9 @@ static WRITE16_HANDLER( cpuregs_w )
switch (offset)
{
- case 0x00: break;
- case 0x04: cpustate->imr = data; break;
- case 0x06: // IFR
+ case 0x00: break;
+ case 0x04: cpustate->imr = data; break;
+ case 0x06: // IFR
{
int i;
for (i=0; i < 16; i++)
@@ -486,7 +486,7 @@ static WRITE16_HANDLER( cpuregs_w )
break;
}
- case 0x07: // PMST
+ case 0x07: // PMST
{
cpustate->pmst.iptr = (data >> 11) & 0x1f;
cpustate->pmst.avis = (data & 0x80) ? 1 : 0;
@@ -499,29 +499,29 @@ static WRITE16_HANDLER( cpuregs_w )
break;
}
- case 0x09: cpustate->brcr = data; break;
- case 0x0e: cpustate->treg2 = data; break;
- case 0x0f: cpustate->dbmr = data; break;
- case 0x10: cpustate->ar[0] = data; break;
- case 0x11: cpustate->ar[1] = data; break;
- case 0x12: cpustate->ar[2] = data; break;
- case 0x13: cpustate->ar[3] = data; break;
- case 0x14: cpustate->ar[4] = data; break;
- case 0x15: cpustate->ar[5] = data; break;
- case 0x16: cpustate->ar[6] = data; break;
- case 0x17: cpustate->ar[7] = data; break;
- case 0x18: cpustate->indx = data; break;
- case 0x19: cpustate->arcr = data; break;
- case 0x1a: cpustate->cbsr1 = data; break;
- case 0x1b: cpustate->cber1 = data; break;
- case 0x1c: cpustate->cbsr2 = data; break;
- case 0x1d: cpustate->cber2 = data; break;
- case 0x1e: cpustate->cbcr = data; break;
- case 0x1f: cpustate->bmar = data; break;
- case 0x24: cpustate->timer.tim = data; break;
- case 0x25: cpustate->timer.prd = data; break;
-
- case 0x26: // TCR
+ case 0x09: cpustate->brcr = data; break;
+ case 0x0e: cpustate->treg2 = data; break;
+ case 0x0f: cpustate->dbmr = data; break;
+ case 0x10: cpustate->ar[0] = data; break;
+ case 0x11: cpustate->ar[1] = data; break;
+ case 0x12: cpustate->ar[2] = data; break;
+ case 0x13: cpustate->ar[3] = data; break;
+ case 0x14: cpustate->ar[4] = data; break;
+ case 0x15: cpustate->ar[5] = data; break;
+ case 0x16: cpustate->ar[6] = data; break;
+ case 0x17: cpustate->ar[7] = data; break;
+ case 0x18: cpustate->indx = data; break;
+ case 0x19: cpustate->arcr = data; break;
+ case 0x1a: cpustate->cbsr1 = data; break;
+ case 0x1b: cpustate->cber1 = data; break;
+ case 0x1c: cpustate->cbsr2 = data; break;
+ case 0x1d: cpustate->cber2 = data; break;
+ case 0x1e: cpustate->cbcr = data; break;
+ case 0x1f: cpustate->bmar = data; break;
+ case 0x24: cpustate->timer.tim = data; break;
+ case 0x25: cpustate->timer.prd = data; break;
+
+ case 0x26: // TCR
{
cpustate->timer.tddr = data & 0xf;
cpustate->timer.psc = (data >> 6) & 0xf;
@@ -534,7 +534,7 @@ static WRITE16_HANDLER( cpuregs_w )
break;
}
- case 0x28: break; // PDWSR
+ case 0x28: break; // PDWSR
default:
if(!space.debugger_access())
fatalerror("32051: cpuregs_w: unimplemented memory-mapped register %02X, data %04X at %04X\n", offset, data, cpustate->pc-1);
@@ -546,17 +546,17 @@ static WRITE16_HANDLER( cpuregs_w )
**************************************************************************/
static ADDRESS_MAP_START( internal_pgm, AS_PROGRAM, 16, legacy_cpu_device )
- AM_RANGE(0x0000, 0x1fff) AM_ROM // ROM TODO: is off-chip if MP/_MC = 0
- AM_RANGE(0x2000, 0x23ff) AM_RAM AM_SHARE("saram") // SARAM TODO: is off-chip if RAM bit = 0
- AM_RANGE(0xfe00, 0xffff) AM_RAM AM_SHARE("daram_b0") // DARAM B0 TODO: is off-chip if CNF = 0
+ AM_RANGE(0x0000, 0x1fff) AM_ROM // ROM TODO: is off-chip if MP/_MC = 0
+ AM_RANGE(0x2000, 0x23ff) AM_RAM AM_SHARE("saram") // SARAM TODO: is off-chip if RAM bit = 0
+ AM_RANGE(0xfe00, 0xffff) AM_RAM AM_SHARE("daram_b0") // DARAM B0 TODO: is off-chip if CNF = 0
ADDRESS_MAP_END
static ADDRESS_MAP_START( internal_data, AS_DATA, 16, legacy_cpu_device )
AM_RANGE(0x0000, 0x005f) AM_READWRITE_LEGACY(cpuregs_r, cpuregs_w)
- AM_RANGE(0x0060, 0x007f) AM_RAM // DARAM B2
- AM_RANGE(0x0100, 0x02ff) AM_RAM AM_SHARE("daram_b0") // DARAM B0 TODO: is unconnected if CNF = 1
- AM_RANGE(0x0300, 0x04ff) AM_RAM // DARAM B1
- AM_RANGE(0x0800, 0x0bff) AM_RAM AM_SHARE("saram") // SARAM TODO: is off-chip if OVLY = 0
+ AM_RANGE(0x0060, 0x007f) AM_RAM // DARAM B2
+ AM_RANGE(0x0100, 0x02ff) AM_RAM AM_SHARE("daram_b0") // DARAM B0 TODO: is unconnected if CNF = 1
+ AM_RANGE(0x0300, 0x04ff) AM_RAM // DARAM B1
+ AM_RANGE(0x0800, 0x0bff) AM_RAM AM_SHARE("saram") // SARAM TODO: is off-chip if OVLY = 0
ADDRESS_MAP_END
/**************************************************************************
@@ -570,7 +570,7 @@ static CPU_SET_INFO( tms )
switch (state)
{
case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + TMS32051_PC: cpustate->pc = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_PC: cpustate->pc = info->i; break;
}
}
@@ -596,101 +596,101 @@ static CPU_GET_INFO( tms )
switch(state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms32051_state); break;
- case CPUINFO_INT_INPUT_LINES: info->i = 6; break;
- case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
- case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
- case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
- case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
- case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
- case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
- case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
- case CPUINFO_INT_MAX_CYCLES: info->i = 5; break;
-
- case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -1; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 16; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 16; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = -1; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
-
- case CPUINFO_INT_INPUT_STATE: info->i = CLEAR_LINE; break;
-
- case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
+ case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms32051_state); break;
+ case CPUINFO_INT_INPUT_LINES: info->i = 6; break;
+ case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
+ case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
+ case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
+ case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
+ case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
+ case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
+ case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
+ case CPUINFO_INT_MAX_CYCLES: info->i = 5; break;
+
+ case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break;
+ case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
+ case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -1; break;
+ case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 16; break;
+ case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 16; break;
+ case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = -1; break;
+ case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
+ case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
+ case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
+
+ case CPUINFO_INT_INPUT_STATE: info->i = CLEAR_LINE; break;
+
+ case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + TMS32051_PC: info->i = cpustate->pc; break;
- case CPUINFO_INT_REGISTER + TMS32051_ACC: info->i = cpustate->acc; break;
- case CPUINFO_INT_REGISTER + TMS32051_ACCB: info->i = cpustate->accb; break;
- case CPUINFO_INT_REGISTER + TMS32051_PREG: info->i = cpustate->preg; break;
- case CPUINFO_INT_REGISTER + TMS32051_TREG0: info->i = cpustate->treg0; break;
- case CPUINFO_INT_REGISTER + TMS32051_TREG1: info->i = cpustate->treg1; break;
- case CPUINFO_INT_REGISTER + TMS32051_TREG2: info->i = cpustate->treg2; break;
- case CPUINFO_INT_REGISTER + TMS32051_BMAR: info->i = cpustate->bmar; break;
- case CPUINFO_INT_REGISTER + TMS32051_RPTC: info->i = cpustate->rptc; break;
- case CPUINFO_INT_REGISTER + TMS32051_BRCR: info->i = cpustate->brcr; break;
- case CPUINFO_INT_REGISTER + TMS32051_INDX: info->i = cpustate->indx; break;
- case CPUINFO_INT_REGISTER + TMS32051_DBMR: info->i = cpustate->dbmr; break;
- case CPUINFO_INT_REGISTER + TMS32051_ARCR: info->i = cpustate->arcr; break;
- case CPUINFO_INT_REGISTER + TMS32051_DP: info->i = cpustate->st0.dp; break;
- case CPUINFO_INT_REGISTER + TMS32051_ARP: info->i = cpustate->st0.arp; break;
- case CPUINFO_INT_REGISTER + TMS32051_ARB: info->i = cpustate->st1.arb; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR0: info->i = cpustate->ar[0]; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR1: info->i = cpustate->ar[1]; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR2: info->i = cpustate->ar[2]; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR3: info->i = cpustate->ar[3]; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR4: info->i = cpustate->ar[4]; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR5: info->i = cpustate->ar[5]; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR6: info->i = cpustate->ar[6]; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR7: info->i = cpustate->ar[7]; break;
+ case CPUINFO_INT_REGISTER + TMS32051_PC: info->i = cpustate->pc; break;
+ case CPUINFO_INT_REGISTER + TMS32051_ACC: info->i = cpustate->acc; break;
+ case CPUINFO_INT_REGISTER + TMS32051_ACCB: info->i = cpustate->accb; break;
+ case CPUINFO_INT_REGISTER + TMS32051_PREG: info->i = cpustate->preg; break;
+ case CPUINFO_INT_REGISTER + TMS32051_TREG0: info->i = cpustate->treg0; break;
+ case CPUINFO_INT_REGISTER + TMS32051_TREG1: info->i = cpustate->treg1; break;
+ case CPUINFO_INT_REGISTER + TMS32051_TREG2: info->i = cpustate->treg2; break;
+ case CPUINFO_INT_REGISTER + TMS32051_BMAR: info->i = cpustate->bmar; break;
+ case CPUINFO_INT_REGISTER + TMS32051_RPTC: info->i = cpustate->rptc; break;
+ case CPUINFO_INT_REGISTER + TMS32051_BRCR: info->i = cpustate->brcr; break;
+ case CPUINFO_INT_REGISTER + TMS32051_INDX: info->i = cpustate->indx; break;
+ case CPUINFO_INT_REGISTER + TMS32051_DBMR: info->i = cpustate->dbmr; break;
+ case CPUINFO_INT_REGISTER + TMS32051_ARCR: info->i = cpustate->arcr; break;
+ case CPUINFO_INT_REGISTER + TMS32051_DP: info->i = cpustate->st0.dp; break;
+ case CPUINFO_INT_REGISTER + TMS32051_ARP: info->i = cpustate->st0.arp; break;
+ case CPUINFO_INT_REGISTER + TMS32051_ARB: info->i = cpustate->st1.arb; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR0: info->i = cpustate->ar[0]; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR1: info->i = cpustate->ar[1]; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR2: info->i = cpustate->ar[2]; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR3: info->i = cpustate->ar[3]; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR4: info->i = cpustate->ar[4]; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR5: info->i = cpustate->ar[5]; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR6: info->i = cpustate->ar[6]; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR7: info->i = cpustate->ar[7]; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(tms); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(tms); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(tms); break;
- case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms); break;
- case CPUINFO_FCT_BURN: info->burn = NULL; break;
- case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms32051); break;
- case CPUINFO_FCT_READ: info->read = CPU_READ_NAME(tms); break;
- case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
+ case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(tms); break;
+ case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(tms); break;
+ case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(tms); break;
+ case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms); break;
+ case CPUINFO_FCT_BURN: info->burn = NULL; break;
+ case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms32051); break;
+ case CPUINFO_FCT_READ: info->read = CPU_READ_NAME(tms); break;
+ case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(internal_pgm); break;
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map16 = ADDRESS_MAP_NAME(internal_data); break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
- case CPUINFO_STR_FAMILY: strcpy(info->s, "TMS3205x"); break;
- case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
- case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
- case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde"); break;
-
- case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break;
-
- case CPUINFO_STR_REGISTER + TMS32051_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break;
- case CPUINFO_STR_REGISTER + TMS32051_ACC: sprintf(info->s, "ACC: %08X", cpustate->acc); break;
- case CPUINFO_STR_REGISTER + TMS32051_ACCB: sprintf(info->s, "ACCB: %08X", cpustate->accb); break;
- case CPUINFO_STR_REGISTER + TMS32051_PREG: sprintf(info->s, "PREG: %08X", cpustate->preg); break;
- case CPUINFO_STR_REGISTER + TMS32051_TREG0: sprintf(info->s, "TREG0: %04X", cpustate->treg0); break;
- case CPUINFO_STR_REGISTER + TMS32051_TREG1: sprintf(info->s, "TREG1: %04X", cpustate->treg1); break;
- case CPUINFO_STR_REGISTER + TMS32051_TREG2: sprintf(info->s, "TREG2: %04X", cpustate->treg2); break;
- case CPUINFO_STR_REGISTER + TMS32051_BMAR: sprintf(info->s, "BMAR: %08X", cpustate->bmar); break;
- case CPUINFO_STR_REGISTER + TMS32051_RPTC: sprintf(info->s, "RPTC: %08X", cpustate->rptc); break;
- case CPUINFO_STR_REGISTER + TMS32051_BRCR: sprintf(info->s, "BRCR: %08X", cpustate->brcr); break;
- case CPUINFO_STR_REGISTER + TMS32051_INDX: sprintf(info->s, "INDX: %04X", cpustate->indx); break;
- case CPUINFO_STR_REGISTER + TMS32051_DBMR: sprintf(info->s, "DBMR: %04X", cpustate->dbmr); break;
- case CPUINFO_STR_REGISTER + TMS32051_ARCR: sprintf(info->s, "ARCR: %04X", cpustate->arcr); break;
- case CPUINFO_STR_REGISTER + TMS32051_DP: sprintf(info->s, "DP: %04X", cpustate->st0.dp); break;
- case CPUINFO_STR_REGISTER + TMS32051_ARP: sprintf(info->s, "ARP: %04X", cpustate->st0.arp); break;
- case CPUINFO_STR_REGISTER + TMS32051_ARB: sprintf(info->s, "ARB: %04X", cpustate->st1.arb); break;
- case CPUINFO_STR_REGISTER + TMS32051_AR0: sprintf(info->s, "AR0: %04X", cpustate->ar[0]); break;
- case CPUINFO_STR_REGISTER + TMS32051_AR1: sprintf(info->s, "AR1: %04X", cpustate->ar[1]); break;
- case CPUINFO_STR_REGISTER + TMS32051_AR2: sprintf(info->s, "AR2: %04X", cpustate->ar[2]); break;
- case CPUINFO_STR_REGISTER + TMS32051_AR3: sprintf(info->s, "AR3: %04X", cpustate->ar[3]); break;
- case CPUINFO_STR_REGISTER + TMS32051_AR4: sprintf(info->s, "AR4: %04X", cpustate->ar[4]); break;
- case CPUINFO_STR_REGISTER + TMS32051_AR5: sprintf(info->s, "AR5: %04X", cpustate->ar[5]); break;
- case CPUINFO_STR_REGISTER + TMS32051_AR6: sprintf(info->s, "AR6: %04X", cpustate->ar[6]); break;
- case CPUINFO_STR_REGISTER + TMS32051_AR7: sprintf(info->s, "AR7: %04X", cpustate->ar[7]); break;
+ case CPUINFO_STR_FAMILY: strcpy(info->s, "TMS3205x"); break;
+ case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
+ case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
+ case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde"); break;
+
+ case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break;
+
+ case CPUINFO_STR_REGISTER + TMS32051_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break;
+ case CPUINFO_STR_REGISTER + TMS32051_ACC: sprintf(info->s, "ACC: %08X", cpustate->acc); break;
+ case CPUINFO_STR_REGISTER + TMS32051_ACCB: sprintf(info->s, "ACCB: %08X", cpustate->accb); break;
+ case CPUINFO_STR_REGISTER + TMS32051_PREG: sprintf(info->s, "PREG: %08X", cpustate->preg); break;
+ case CPUINFO_STR_REGISTER + TMS32051_TREG0: sprintf(info->s, "TREG0: %04X", cpustate->treg0); break;
+ case CPUINFO_STR_REGISTER + TMS32051_TREG1: sprintf(info->s, "TREG1: %04X", cpustate->treg1); break;
+ case CPUINFO_STR_REGISTER + TMS32051_TREG2: sprintf(info->s, "TREG2: %04X", cpustate->treg2); break;
+ case CPUINFO_STR_REGISTER + TMS32051_BMAR: sprintf(info->s, "BMAR: %08X", cpustate->bmar); break;
+ case CPUINFO_STR_REGISTER + TMS32051_RPTC: sprintf(info->s, "RPTC: %08X", cpustate->rptc); break;
+ case CPUINFO_STR_REGISTER + TMS32051_BRCR: sprintf(info->s, "BRCR: %08X", cpustate->brcr); break;
+ case CPUINFO_STR_REGISTER + TMS32051_INDX: sprintf(info->s, "INDX: %04X", cpustate->indx); break;
+ case CPUINFO_STR_REGISTER + TMS32051_DBMR: sprintf(info->s, "DBMR: %04X", cpustate->dbmr); break;
+ case CPUINFO_STR_REGISTER + TMS32051_ARCR: sprintf(info->s, "ARCR: %04X", cpustate->arcr); break;
+ case CPUINFO_STR_REGISTER + TMS32051_DP: sprintf(info->s, "DP: %04X", cpustate->st0.dp); break;
+ case CPUINFO_STR_REGISTER + TMS32051_ARP: sprintf(info->s, "ARP: %04X", cpustate->st0.arp); break;
+ case CPUINFO_STR_REGISTER + TMS32051_ARB: sprintf(info->s, "ARB: %04X", cpustate->st1.arb); break;
+ case CPUINFO_STR_REGISTER + TMS32051_AR0: sprintf(info->s, "AR0: %04X", cpustate->ar[0]); break;
+ case CPUINFO_STR_REGISTER + TMS32051_AR1: sprintf(info->s, "AR1: %04X", cpustate->ar[1]); break;
+ case CPUINFO_STR_REGISTER + TMS32051_AR2: sprintf(info->s, "AR2: %04X", cpustate->ar[2]); break;
+ case CPUINFO_STR_REGISTER + TMS32051_AR3: sprintf(info->s, "AR3: %04X", cpustate->ar[3]); break;
+ case CPUINFO_STR_REGISTER + TMS32051_AR4: sprintf(info->s, "AR4: %04X", cpustate->ar[4]); break;
+ case CPUINFO_STR_REGISTER + TMS32051_AR5: sprintf(info->s, "AR5: %04X", cpustate->ar[5]); break;
+ case CPUINFO_STR_REGISTER + TMS32051_AR6: sprintf(info->s, "AR6: %04X", cpustate->ar[6]); break;
+ case CPUINFO_STR_REGISTER + TMS32051_AR7: sprintf(info->s, "AR7: %04X", cpustate->ar[7]); break;
}
}
@@ -705,31 +705,31 @@ static CPU_SET_INFO( tms32051 )
switch(state)
{
case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + TMS32051_PC: cpustate->pc = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_ACC: cpustate->acc = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_ACCB: cpustate->accb = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_PREG: cpustate->preg = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_TREG0: cpustate->treg0 = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_TREG1: cpustate->treg1 = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_TREG2: cpustate->treg2 = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_BMAR: cpustate->bmar = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_BRCR: cpustate->brcr = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_INDX: cpustate->indx = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_DBMR: cpustate->dbmr = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_ARCR: cpustate->arcr = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_DP: cpustate->st0.dp = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_ARP: cpustate->st0.arp = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_ARB: cpustate->st1.arb = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR0: cpustate->ar[0] = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR1: cpustate->ar[1] = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR2: cpustate->ar[2] = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR3: cpustate->ar[3] = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR4: cpustate->ar[4] = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR5: cpustate->ar[5] = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR6: cpustate->ar[6] = info->i; break;
- case CPUINFO_INT_REGISTER + TMS32051_AR7: cpustate->ar[7] = info->i; break;
-
- default: CPU_SET_INFO_CALL(tms); break;
+ case CPUINFO_INT_REGISTER + TMS32051_PC: cpustate->pc = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_ACC: cpustate->acc = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_ACCB: cpustate->accb = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_PREG: cpustate->preg = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_TREG0: cpustate->treg0 = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_TREG1: cpustate->treg1 = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_TREG2: cpustate->treg2 = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_BMAR: cpustate->bmar = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_BRCR: cpustate->brcr = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_INDX: cpustate->indx = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_DBMR: cpustate->dbmr = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_ARCR: cpustate->arcr = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_DP: cpustate->st0.dp = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_ARP: cpustate->st0.arp = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_ARB: cpustate->st1.arb = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR0: cpustate->ar[0] = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR1: cpustate->ar[1] = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR2: cpustate->ar[2] = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR3: cpustate->ar[3] = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR4: cpustate->ar[4] = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR5: cpustate->ar[5] = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR6: cpustate->ar[6] = info->i; break;
+ case CPUINFO_INT_REGISTER + TMS32051_AR7: cpustate->ar[7] = info->i; break;
+
+ default: CPU_SET_INFO_CALL(tms); break;
}
}
@@ -738,12 +738,12 @@ CPU_GET_INFO( tms32051 )
switch(state)
{
/* --- the following bits of info are returned as pointers to data or functions --- */
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms32051); break;
+ case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms32051); break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
- case CPUINFO_STR_NAME: strcpy(info->s, "TMS32051"); break;
+ case CPUINFO_STR_NAME: strcpy(info->s, "TMS32051"); break;
- default: CPU_GET_INFO_CALL(tms); break;
+ default: CPU_GET_INFO_CALL(tms); break;
}
}