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Diffstat (limited to 'src/emu/cpu/sm8500/sm8500.c')
-rw-r--r--src/emu/cpu/sm8500/sm8500.c290
1 files changed, 145 insertions, 145 deletions
diff --git a/src/emu/cpu/sm8500/sm8500.c b/src/emu/cpu/sm8500/sm8500.c
index 574d7d56d90..b9af6319afc 100644
--- a/src/emu/cpu/sm8500/sm8500.c
+++ b/src/emu/cpu/sm8500/sm8500.c
@@ -21,14 +21,14 @@ they are internally.
#include "debugger.h"
#include "sm8500.h"
-#define FLAG_C 0x80
-#define FLAG_Z 0x40
-#define FLAG_S 0x20
-#define FLAG_V 0x10
-#define FLAG_D 0x08
-#define FLAG_H 0x04
-#define FLAG_B 0x02
-#define FLAG_I 0x01
+#define FLAG_C 0x80
+#define FLAG_Z 0x40
+#define FLAG_S 0x20
+#define FLAG_V 0x10
+#define FLAG_D 0x08
+#define FLAG_H 0x04
+#define FLAG_B 0x02
+#define FLAG_I 0x01
struct sm8500_state
{
@@ -63,7 +63,7 @@ INLINE sm8500_state *get_safe_token(device_t *device)
}
static const UINT8 sm8500_b2w[8] = {
- 0, 8, 2, 10, 4, 12, 6, 14
+ 0, 8, 2, 10, 4, 12, 6, 14
};
INLINE void sm8500_get_sp( sm8500_state *cpustate )
@@ -100,7 +100,7 @@ static void sm85cpu_mem_writebyte( sm8500_state *cpustate, UINT32 offset, UINT8
case 0x1c:
case 0x1d: sm8500_get_sp(cpustate); break;
case 0x1e: cpustate->PS0 = data;
- for (i = 0; i < 16; i++) // refresh register contents in debugger
+ for (i = 0; i < 16; i++) // refresh register contents in debugger
cpustate->program->write_byte(i, sm85cpu_mem_readbyte(cpustate, i)); break;
case 0x1f: cpustate->PS1 = data; break;
}
@@ -157,7 +157,7 @@ static CPU_EXIT( sm8500 )
{
}
-#define PUSH_BYTE(X) cpustate->SP--; \
+#define PUSH_BYTE(X) cpustate->SP--; \
if ( ( cpustate->SYS & 0x40 ) == 0 ) cpustate->SP &= 0xFF; \
sm85cpu_mem_writebyte( cpustate, cpustate->SP, X );
@@ -262,15 +262,15 @@ INLINE void sm8500_process_interrupts(sm8500_state *cpustate) {
static CPU_EXECUTE( sm8500 )
{
sm8500_state *cpustate = get_safe_token(device);
- UINT8 op;
- int mycycles;
+ UINT8 op;
+ int mycycles;
do
{
- UINT8 r1,r2;
- UINT16 s1,s2;
- UINT32 d1,d2;
- UINT32 res;
+ UINT8 r1,r2;
+ UINT16 s1,s2;
+ UINT32 d1,d2;
+ UINT32 res;
debugger_instruction_hook(device, cpustate->PC);
cpustate->oldpc = cpustate->PC;
@@ -288,7 +288,7 @@ static CPU_EXECUTE( sm8500 )
}
if (cpustate->SYS&0x40) cpustate->program->write_byte(0x1c,cpustate->SP>>8);
cpustate->program->write_byte(0x1d,cpustate->SP&0xFF);
- sm85cpu_mem_writebyte(cpustate,0x1e,cpustate->PS0); // need to update debugger
+ sm85cpu_mem_writebyte(cpustate,0x1e,cpustate->PS0); // need to update debugger
cpustate->program->write_byte(0x1f,cpustate->PS1);
} else {
mycycles = 4;
@@ -319,37 +319,37 @@ static unsigned sm8500_get_reg( sm8500_state *cpustate, int regnum )
switch( regnum )
{
case STATE_GENPC:
- case SM8500_PC: return cpustate->PC;
+ case SM8500_PC: return cpustate->PC;
case STATE_GENSP:
- case SM8500_SP: return cpustate->SP;
- case SM8500_PS: return sm85cpu_mem_readword( cpustate, 0x1e );
- case SM8500_SYS16: return cpustate->SYS;
- case SM8500_RR0: return sm85cpu_mem_readword( cpustate, 0x00 );
- case SM8500_RR2: return sm85cpu_mem_readword( cpustate, 0x02 );
- case SM8500_RR4: return sm85cpu_mem_readword( cpustate, 0x04 );
- case SM8500_RR6: return sm85cpu_mem_readword( cpustate, 0x06 );
- case SM8500_RR8: return sm85cpu_mem_readword( cpustate, 0x08 );
- case SM8500_RR10: return sm85cpu_mem_readword( cpustate, 0x0A );
- case SM8500_RR12: return sm85cpu_mem_readword( cpustate, 0x0C );
- case SM8500_RR14: return sm85cpu_mem_readword( cpustate, 0x0E );
- case SM8500_IE0: return sm85cpu_mem_readbyte( cpustate, 0x10 );
- case SM8500_IE1: return sm85cpu_mem_readbyte( cpustate, 0x11 );
- case SM8500_IR0: return sm85cpu_mem_readbyte( cpustate, 0x12 );
- case SM8500_IR1: return sm85cpu_mem_readbyte( cpustate, 0x13 );
- case SM8500_P0: return sm85cpu_mem_readbyte( cpustate, 0x14 );
- case SM8500_P1: return sm85cpu_mem_readbyte( cpustate, 0x15 );
- case SM8500_P2: return sm85cpu_mem_readbyte( cpustate, 0x16 );
- case SM8500_P3: return sm85cpu_mem_readbyte( cpustate, 0x17 );
- case SM8500_SYS: return sm85cpu_mem_readbyte( cpustate, 0x19 );
- case SM8500_CKC: return sm85cpu_mem_readbyte( cpustate, 0x1a );
- case SM8500_SPH: return sm85cpu_mem_readbyte( cpustate, 0x1c );
- case SM8500_SPL: return sm85cpu_mem_readbyte( cpustate, 0x1d );
- case SM8500_PS0: return sm85cpu_mem_readbyte( cpustate, 0x1e );
- case SM8500_PS1: return sm85cpu_mem_readbyte( cpustate, 0x1f );
- case SM8500_P0C: return sm85cpu_mem_readbyte( cpustate, 0x20 );
- case SM8500_P1C: return sm85cpu_mem_readbyte( cpustate, 0x21 );
- case SM8500_P2C: return sm85cpu_mem_readbyte( cpustate, 0x22 );
- case SM8500_P3C: return sm85cpu_mem_readbyte( cpustate, 0x23 );
+ case SM8500_SP: return cpustate->SP;
+ case SM8500_PS: return sm85cpu_mem_readword( cpustate, 0x1e );
+ case SM8500_SYS16: return cpustate->SYS;
+ case SM8500_RR0: return sm85cpu_mem_readword( cpustate, 0x00 );
+ case SM8500_RR2: return sm85cpu_mem_readword( cpustate, 0x02 );
+ case SM8500_RR4: return sm85cpu_mem_readword( cpustate, 0x04 );
+ case SM8500_RR6: return sm85cpu_mem_readword( cpustate, 0x06 );
+ case SM8500_RR8: return sm85cpu_mem_readword( cpustate, 0x08 );
+ case SM8500_RR10: return sm85cpu_mem_readword( cpustate, 0x0A );
+ case SM8500_RR12: return sm85cpu_mem_readword( cpustate, 0x0C );
+ case SM8500_RR14: return sm85cpu_mem_readword( cpustate, 0x0E );
+ case SM8500_IE0: return sm85cpu_mem_readbyte( cpustate, 0x10 );
+ case SM8500_IE1: return sm85cpu_mem_readbyte( cpustate, 0x11 );
+ case SM8500_IR0: return sm85cpu_mem_readbyte( cpustate, 0x12 );
+ case SM8500_IR1: return sm85cpu_mem_readbyte( cpustate, 0x13 );
+ case SM8500_P0: return sm85cpu_mem_readbyte( cpustate, 0x14 );
+ case SM8500_P1: return sm85cpu_mem_readbyte( cpustate, 0x15 );
+ case SM8500_P2: return sm85cpu_mem_readbyte( cpustate, 0x16 );
+ case SM8500_P3: return sm85cpu_mem_readbyte( cpustate, 0x17 );
+ case SM8500_SYS: return sm85cpu_mem_readbyte( cpustate, 0x19 );
+ case SM8500_CKC: return sm85cpu_mem_readbyte( cpustate, 0x1a );
+ case SM8500_SPH: return sm85cpu_mem_readbyte( cpustate, 0x1c );
+ case SM8500_SPL: return sm85cpu_mem_readbyte( cpustate, 0x1d );
+ case SM8500_PS0: return sm85cpu_mem_readbyte( cpustate, 0x1e );
+ case SM8500_PS1: return sm85cpu_mem_readbyte( cpustate, 0x1f );
+ case SM8500_P0C: return sm85cpu_mem_readbyte( cpustate, 0x20 );
+ case SM8500_P1C: return sm85cpu_mem_readbyte( cpustate, 0x21 );
+ case SM8500_P2C: return sm85cpu_mem_readbyte( cpustate, 0x22 );
+ case SM8500_P3C: return sm85cpu_mem_readbyte( cpustate, 0x23 );
}
return 0;
}
@@ -359,37 +359,37 @@ static void sm8500_set_reg( sm8500_state *cpustate, int regnum, unsigned val )
switch( regnum )
{
case STATE_GENPC:
- case SM8500_PC: cpustate->PC = val; break;
+ case SM8500_PC: cpustate->PC = val; break;
case STATE_GENSP:
- case SM8500_SP: cpustate->SP = val; cpustate->program->write_byte(0x1d, val&0xff); if (cpustate->SYS&0x40) cpustate->program->write_byte(0x1c, val>>8); break;
- case SM8500_PS: sm85cpu_mem_writeword( cpustate, 0x1e, val); break;
- case SM8500_SYS16: val&=0xff; sm85cpu_mem_writebyte( cpustate, 0x19, val); break;
- case SM8500_RR0: sm85cpu_mem_writeword( cpustate, 0x00, val); break;
- case SM8500_RR2: sm85cpu_mem_writeword( cpustate, 0x02, val); break;
- case SM8500_RR4: sm85cpu_mem_writeword( cpustate, 0x04, val); break;
- case SM8500_RR6: sm85cpu_mem_writeword( cpustate, 0x06, val); break;
- case SM8500_RR8: sm85cpu_mem_writeword( cpustate, 0x08, val); break;
- case SM8500_RR10: sm85cpu_mem_writeword( cpustate, 0x0A, val); break;
- case SM8500_RR12: sm85cpu_mem_writeword( cpustate, 0x0C, val); break;
- case SM8500_RR14: sm85cpu_mem_writeword( cpustate, 0x0E, val); break;
- case SM8500_IE0: sm85cpu_mem_writebyte( cpustate, 0x10, val); break;
- case SM8500_IE1: sm85cpu_mem_writebyte( cpustate, 0x11, val); break;
- case SM8500_IR0: sm85cpu_mem_writebyte( cpustate, 0x12, val); break;
- case SM8500_IR1: sm85cpu_mem_writebyte( cpustate, 0x13, val); break;
- case SM8500_P0: sm85cpu_mem_writebyte( cpustate, 0x14, val); break;
- case SM8500_P1: sm85cpu_mem_writebyte( cpustate, 0x15, val); break;
- case SM8500_P2: sm85cpu_mem_writebyte( cpustate, 0x16, val); break;
- case SM8500_P3: sm85cpu_mem_writebyte( cpustate, 0x17, val); break;
- case SM8500_SYS: sm85cpu_mem_writebyte( cpustate, 0x19, val); break;
- case SM8500_CKC: sm85cpu_mem_writebyte( cpustate, 0x1a, val); if ( val & 0x80 ) { cpustate->clock_changed = 1; }; break;
- case SM8500_SPH: sm85cpu_mem_writebyte( cpustate, 0x1c, val); break;
- case SM8500_SPL: sm85cpu_mem_writebyte( cpustate, 0x1d, val); break;
- case SM8500_PS0: sm85cpu_mem_writebyte( cpustate, 0x1e, val); break;
- case SM8500_PS1: sm85cpu_mem_writebyte( cpustate, 0x1f, val); break;
- case SM8500_P0C: sm85cpu_mem_writebyte( cpustate, 0x20, val); break;
- case SM8500_P1C: sm85cpu_mem_writebyte( cpustate, 0x21, val); break;
- case SM8500_P2C: sm85cpu_mem_writebyte( cpustate, 0x22, val); break;
- case SM8500_P3C: sm85cpu_mem_writebyte( cpustate, 0x23, val); break;
+ case SM8500_SP: cpustate->SP = val; cpustate->program->write_byte(0x1d, val&0xff); if (cpustate->SYS&0x40) cpustate->program->write_byte(0x1c, val>>8); break;
+ case SM8500_PS: sm85cpu_mem_writeword( cpustate, 0x1e, val); break;
+ case SM8500_SYS16: val&=0xff; sm85cpu_mem_writebyte( cpustate, 0x19, val); break;
+ case SM8500_RR0: sm85cpu_mem_writeword( cpustate, 0x00, val); break;
+ case SM8500_RR2: sm85cpu_mem_writeword( cpustate, 0x02, val); break;
+ case SM8500_RR4: sm85cpu_mem_writeword( cpustate, 0x04, val); break;
+ case SM8500_RR6: sm85cpu_mem_writeword( cpustate, 0x06, val); break;
+ case SM8500_RR8: sm85cpu_mem_writeword( cpustate, 0x08, val); break;
+ case SM8500_RR10: sm85cpu_mem_writeword( cpustate, 0x0A, val); break;
+ case SM8500_RR12: sm85cpu_mem_writeword( cpustate, 0x0C, val); break;
+ case SM8500_RR14: sm85cpu_mem_writeword( cpustate, 0x0E, val); break;
+ case SM8500_IE0: sm85cpu_mem_writebyte( cpustate, 0x10, val); break;
+ case SM8500_IE1: sm85cpu_mem_writebyte( cpustate, 0x11, val); break;
+ case SM8500_IR0: sm85cpu_mem_writebyte( cpustate, 0x12, val); break;
+ case SM8500_IR1: sm85cpu_mem_writebyte( cpustate, 0x13, val); break;
+ case SM8500_P0: sm85cpu_mem_writebyte( cpustate, 0x14, val); break;
+ case SM8500_P1: sm85cpu_mem_writebyte( cpustate, 0x15, val); break;
+ case SM8500_P2: sm85cpu_mem_writebyte( cpustate, 0x16, val); break;
+ case SM8500_P3: sm85cpu_mem_writebyte( cpustate, 0x17, val); break;
+ case SM8500_SYS: sm85cpu_mem_writebyte( cpustate, 0x19, val); break;
+ case SM8500_CKC: sm85cpu_mem_writebyte( cpustate, 0x1a, val); if ( val & 0x80 ) { cpustate->clock_changed = 1; }; break;
+ case SM8500_SPH: sm85cpu_mem_writebyte( cpustate, 0x1c, val); break;
+ case SM8500_SPL: sm85cpu_mem_writebyte( cpustate, 0x1d, val); break;
+ case SM8500_PS0: sm85cpu_mem_writebyte( cpustate, 0x1e, val); break;
+ case SM8500_PS1: sm85cpu_mem_writebyte( cpustate, 0x1f, val); break;
+ case SM8500_P0C: sm85cpu_mem_writebyte( cpustate, 0x20, val); break;
+ case SM8500_P1C: sm85cpu_mem_writebyte( cpustate, 0x21, val); break;
+ case SM8500_P2C: sm85cpu_mem_writebyte( cpustate, 0x22, val); break;
+ case SM8500_P3C: sm85cpu_mem_writebyte( cpustate, 0x23, val); break;
}
}
@@ -401,26 +401,26 @@ static void sm8500_set_irq_line( sm8500_state *cpustate, int irqline, int state
cpustate->IFLAGS |= ( 0x01 << irqline );
cpustate->CheckInterrupts = 1;
switch( irqline ) {
- case DMA_INT: cpustate->IR0 |= 0x80; break;
- case TIM0_INT: cpustate->IR0 |= 0x40; break;
- case EXT_INT: cpustate->IR0 |= 0x10; break;
- case UART_INT: cpustate->IR0 |= 0x08; break;
- case LCDC_INT: cpustate->IR0 |= 0x01; break;
- case TIM1_INT: cpustate->IR1 |= 0x40; break;
- case CK_INT: cpustate->IR1 |= 0x10; break;
- case PIO_INT: cpustate->IR1 |= 0x04; break;
+ case DMA_INT: cpustate->IR0 |= 0x80; break;
+ case TIM0_INT: cpustate->IR0 |= 0x40; break;
+ case EXT_INT: cpustate->IR0 |= 0x10; break;
+ case UART_INT: cpustate->IR0 |= 0x08; break;
+ case LCDC_INT: cpustate->IR0 |= 0x01; break;
+ case TIM1_INT: cpustate->IR1 |= 0x40; break;
+ case CK_INT: cpustate->IR1 |= 0x10; break;
+ case PIO_INT: cpustate->IR1 |= 0x04; break;
}
} else {
cpustate->IFLAGS &= ~( 0x01 << irqline );
switch( irqline ) {
- case DMA_INT: cpustate->IR0 &= ~0x80; break;
- case TIM0_INT: cpustate->IR0 &= ~0x40; break;
- case EXT_INT: cpustate->IR0 &= ~0x10; break;
- case UART_INT: cpustate->IR0 &= ~0x08; break;
- case LCDC_INT: cpustate->IR0 &= ~0x01; break;
- case TIM1_INT: cpustate->IR1 &= ~0x40; break;
- case CK_INT: cpustate->IR1 &= ~0x10; break;
- case PIO_INT: cpustate->IR1 &= ~0x04; break;
+ case DMA_INT: cpustate->IR0 &= ~0x80; break;
+ case TIM0_INT: cpustate->IR0 &= ~0x40; break;
+ case EXT_INT: cpustate->IR0 &= ~0x10; break;
+ case UART_INT: cpustate->IR0 &= ~0x08; break;
+ case LCDC_INT: cpustate->IR0 &= ~0x01; break;
+ case TIM1_INT: cpustate->IR1 &= ~0x40; break;
+ case CK_INT: cpustate->IR1 &= ~0x10; break;
+ case PIO_INT: cpustate->IR1 &= ~0x04; break;
}
if ( 0 == cpustate->IFLAGS ) {
cpustate->CheckInterrupts = 0;
@@ -490,25 +490,25 @@ CPU_GET_INFO( sm8500 )
switch(state)
{
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(sm8500_state); break;
- case CPUINFO_INT_INPUT_LINES: info->i = 8; break;
- case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
- case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
- case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
- case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
- case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
- case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break;
- case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
- case CPUINFO_INT_MAX_CYCLES: info->i = 16; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
+ case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(sm8500_state); break;
+ case CPUINFO_INT_INPUT_LINES: info->i = 8; break;
+ case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
+ case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
+ case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
+ case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
+ case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
+ case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break;
+ case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
+ case CPUINFO_INT_MAX_CYCLES: info->i = 16; break;
+ case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
+ case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
+ case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
+ case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
+ case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
+ case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
+ case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
+ case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
+ case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + 0:
case CPUINFO_INT_INPUT_STATE + 1:
case CPUINFO_INT_INPUT_STATE + 2:
@@ -519,7 +519,7 @@ CPU_GET_INFO( sm8500 )
case CPUINFO_INT_INPUT_STATE + 7:
case CPUINFO_INT_INPUT_STATE + 8:
case CPUINFO_INT_INPUT_STATE + 9:
- case CPUINFO_INT_INPUT_STATE + 10: info->i = cpustate->IFLAGS & ( 1 << (state - CPUINFO_INT_INPUT_STATE)); break;
+ case CPUINFO_INT_INPUT_STATE + 10: info->i = cpustate->IFLAGS & ( 1 << (state - CPUINFO_INT_INPUT_STATE)); break;
case CPUINFO_INT_REGISTER + SM8500_RR0:
case CPUINFO_INT_REGISTER + SM8500_RR2:
case CPUINFO_INT_REGISTER + SM8500_RR4:
@@ -551,25 +551,25 @@ CPU_GET_INFO( sm8500 )
case CPUINFO_INT_REGISTER + SM8500_P2C:
case CPUINFO_INT_REGISTER + SM8500_P3C:
info->i = sm8500_get_reg( cpustate, state - CPUINFO_INT_REGISTER ); break;
- case CPUINFO_INT_REGISTER + STATE_GENPC: info->i = sm8500_get_reg( cpustate, SM8500_PC ); break;
- case CPUINFO_INT_REGISTER + STATE_GENSP: info->i = sm8500_get_reg( cpustate, SM8500_SP ); break;
- case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->oldpc; break;
-
-
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(sm8500); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(sm8500); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sm8500); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(sm8500); break;
- case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(sm8500); break;
- case CPUINFO_FCT_BURN: info->burn = CPU_BURN_NAME(sm8500); break;
- case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sm8500); break;
- case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
-
- case CPUINFO_STR_NAME: strcpy( info->s, "sm8500" ); break;
- case CPUINFO_STR_FAMILY: strcpy( info->s, "Sharp SM8500" ); break;
- case CPUINFO_STR_VERSION: strcpy( info->s, "0.1" ); break;
- case CPUINFO_STR_SOURCE_FILE: strcpy( info->s, __FILE__ ); break;
- case CPUINFO_STR_CREDITS: strcpy( info->s, "Copyright The MESS Team." ); break;
+ case CPUINFO_INT_REGISTER + STATE_GENPC: info->i = sm8500_get_reg( cpustate, SM8500_PC ); break;
+ case CPUINFO_INT_REGISTER + STATE_GENSP: info->i = sm8500_get_reg( cpustate, SM8500_SP ); break;
+ case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->oldpc; break;
+
+
+ case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(sm8500); break;
+ case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(sm8500); break;
+ case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sm8500); break;
+ case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(sm8500); break;
+ case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(sm8500); break;
+ case CPUINFO_FCT_BURN: info->burn = CPU_BURN_NAME(sm8500); break;
+ case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sm8500); break;
+ case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
+
+ case CPUINFO_STR_NAME: strcpy( info->s, "sm8500" ); break;
+ case CPUINFO_STR_FAMILY: strcpy( info->s, "Sharp SM8500" ); break;
+ case CPUINFO_STR_VERSION: strcpy( info->s, "0.1" ); break;
+ case CPUINFO_STR_SOURCE_FILE: strcpy( info->s, __FILE__ ); break;
+ case CPUINFO_STR_CREDITS: strcpy( info->s, "Copyright The MESS Team." ); break;
case CPUINFO_STR_FLAGS:
sprintf( info->s, "%c%c%c%c%c%c%c%c",
cpustate->PS1 & FLAG_C ? 'C' : '.',
@@ -581,18 +581,18 @@ CPU_GET_INFO( sm8500 )
cpustate->PS1 & FLAG_B ? 'B' : '.',
cpustate->PS1 & FLAG_I ? 'I' : '.' );
break;
- case CPUINFO_STR_REGISTER + SM8500_RR0: sprintf(info->s, "RR0:%04X", sm85cpu_mem_readword( cpustate, 0x00 ) ); break;
- case CPUINFO_STR_REGISTER + SM8500_RR2: sprintf(info->s, "RR2:%04X", sm85cpu_mem_readword( cpustate, 0x02 ) ); break;
- case CPUINFO_STR_REGISTER + SM8500_RR4: sprintf(info->s, "RR4:%04X", sm85cpu_mem_readword( cpustate, 0x04 ) ); break;
- case CPUINFO_STR_REGISTER + SM8500_RR6: sprintf(info->s, "RR6:%04X", sm85cpu_mem_readword( cpustate, 0x06 ) ); break;
- case CPUINFO_STR_REGISTER + SM8500_RR8: sprintf(info->s, "RR8:%04X", sm85cpu_mem_readword( cpustate, 0x08 ) ); break;
- case CPUINFO_STR_REGISTER + SM8500_RR10: sprintf(info->s, "RR10:%04X", sm85cpu_mem_readword( cpustate, 0x0A ) ); break;
- case CPUINFO_STR_REGISTER + SM8500_RR12: sprintf(info->s, "RR12:%04X", sm85cpu_mem_readword( cpustate, 0x0C ) ); break;
- case CPUINFO_STR_REGISTER + SM8500_RR14: sprintf(info->s, "RR14:%04X", sm85cpu_mem_readword( cpustate, 0x0E ) ); break;
- case CPUINFO_STR_REGISTER + SM8500_PC: sprintf(info->s, "PC:%04X", cpustate->PC); break;
- case CPUINFO_STR_REGISTER + SM8500_SP: sprintf(info->s, "SP:%04X", cpustate->SP); break;
- case CPUINFO_STR_REGISTER + SM8500_PS: sprintf(info->s, "PS:%04X", ( cpustate->PS0 << 8 ) | cpustate->PS1 ); break;
- case CPUINFO_STR_REGISTER + SM8500_SYS16: sprintf(info->s, "SYS:%02X", cpustate->SYS ); break;
+ case CPUINFO_STR_REGISTER + SM8500_RR0: sprintf(info->s, "RR0:%04X", sm85cpu_mem_readword( cpustate, 0x00 ) ); break;
+ case CPUINFO_STR_REGISTER + SM8500_RR2: sprintf(info->s, "RR2:%04X", sm85cpu_mem_readword( cpustate, 0x02 ) ); break;
+ case CPUINFO_STR_REGISTER + SM8500_RR4: sprintf(info->s, "RR4:%04X", sm85cpu_mem_readword( cpustate, 0x04 ) ); break;
+ case CPUINFO_STR_REGISTER + SM8500_RR6: sprintf(info->s, "RR6:%04X", sm85cpu_mem_readword( cpustate, 0x06 ) ); break;
+ case CPUINFO_STR_REGISTER + SM8500_RR8: sprintf(info->s, "RR8:%04X", sm85cpu_mem_readword( cpustate, 0x08 ) ); break;
+ case CPUINFO_STR_REGISTER + SM8500_RR10: sprintf(info->s, "RR10:%04X", sm85cpu_mem_readword( cpustate, 0x0A ) ); break;
+ case CPUINFO_STR_REGISTER + SM8500_RR12: sprintf(info->s, "RR12:%04X", sm85cpu_mem_readword( cpustate, 0x0C ) ); break;
+ case CPUINFO_STR_REGISTER + SM8500_RR14: sprintf(info->s, "RR14:%04X", sm85cpu_mem_readword( cpustate, 0x0E ) ); break;
+ case CPUINFO_STR_REGISTER + SM8500_PC: sprintf(info->s, "PC:%04X", cpustate->PC); break;
+ case CPUINFO_STR_REGISTER + SM8500_SP: sprintf(info->s, "SP:%04X", cpustate->SP); break;
+ case CPUINFO_STR_REGISTER + SM8500_PS: sprintf(info->s, "PS:%04X", ( cpustate->PS0 << 8 ) | cpustate->PS1 ); break;
+ case CPUINFO_STR_REGISTER + SM8500_SYS16: sprintf(info->s, "SYS:%02X", cpustate->SYS ); break;
}
}