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Diffstat (limited to 'src/emu/cpu/sh2/sh2comn.h')
-rw-r--r--src/emu/cpu/sh2/sh2comn.h184
1 files changed, 92 insertions, 92 deletions
diff --git a/src/emu/cpu/sh2/sh2comn.h b/src/emu/cpu/sh2/sh2comn.h
index 88a9f17a6ce..4504ba01a69 100644
--- a/src/emu/cpu/sh2/sh2comn.h
+++ b/src/emu/cpu/sh2/sh2comn.h
@@ -24,7 +24,7 @@
class sh2_frontend;
#endif
-#define SH2_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(2,0))
+#define SH2_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(2,0))
struct irq_entry
{
@@ -40,99 +40,99 @@ enum
OVF = 0x00020000
};
-#define T 0x00000001
-#define S 0x00000002
-#define I 0x000000f0
-#define Q 0x00000100
-#define M 0x00000200
+#define T 0x00000001
+#define S 0x00000002
+#define I 0x000000f0
+#define Q 0x00000100
+#define M 0x00000200
-#define AM 0xc7ffffff
+#define AM 0xc7ffffff
-#define FLAGS (M|Q|I|S|T)
+#define FLAGS (M|Q|I|S|T)
-#define Rn ((opcode>>8)&15)
-#define Rm ((opcode>>4)&15)
+#define Rn ((opcode>>8)&15)
+#define Rm ((opcode>>4)&15)
-#define CPU_TYPE_SH1 (0)
-#define CPU_TYPE_SH2 (1)
+#define CPU_TYPE_SH1 (0)
+#define CPU_TYPE_SH2 (1)
#define REGFLAG_R(n) (1 << (n))
/* register flags 1 */
-#define REGFLAG_PR (1 << 0)
-#define REGFLAG_MACL (1 << 1)
-#define REGFLAG_MACH (1 << 2)
-#define REGFLAG_GBR (1 << 3)
-#define REGFLAG_VBR (1 << 4)
-#define REGFLAG_SR (1 << 5)
-
-#define CHECK_PENDING_IRQ(message) \
-do { \
- int irq = -1; \
- if (sh2->pending_irq & (1 << 0)) irq = 0; \
- if (sh2->pending_irq & (1 << 1)) irq = 1; \
- if (sh2->pending_irq & (1 << 2)) irq = 2; \
- if (sh2->pending_irq & (1 << 3)) irq = 3; \
- if (sh2->pending_irq & (1 << 4)) irq = 4; \
- if (sh2->pending_irq & (1 << 5)) irq = 5; \
- if (sh2->pending_irq & (1 << 6)) irq = 6; \
- if (sh2->pending_irq & (1 << 7)) irq = 7; \
- if (sh2->pending_irq & (1 << 8)) irq = 8; \
- if (sh2->pending_irq & (1 << 9)) irq = 9; \
- if (sh2->pending_irq & (1 << 10)) irq = 10; \
- if (sh2->pending_irq & (1 << 11)) irq = 11; \
- if (sh2->pending_irq & (1 << 12)) irq = 12; \
- if (sh2->pending_irq & (1 << 13)) irq = 13; \
- if (sh2->pending_irq & (1 << 14)) irq = 14; \
- if (sh2->pending_irq & (1 << 15)) irq = 15; \
+#define REGFLAG_PR (1 << 0)
+#define REGFLAG_MACL (1 << 1)
+#define REGFLAG_MACH (1 << 2)
+#define REGFLAG_GBR (1 << 3)
+#define REGFLAG_VBR (1 << 4)
+#define REGFLAG_SR (1 << 5)
+
+#define CHECK_PENDING_IRQ(message) \
+do { \
+ int irq = -1; \
+ if (sh2->pending_irq & (1 << 0)) irq = 0; \
+ if (sh2->pending_irq & (1 << 1)) irq = 1; \
+ if (sh2->pending_irq & (1 << 2)) irq = 2; \
+ if (sh2->pending_irq & (1 << 3)) irq = 3; \
+ if (sh2->pending_irq & (1 << 4)) irq = 4; \
+ if (sh2->pending_irq & (1 << 5)) irq = 5; \
+ if (sh2->pending_irq & (1 << 6)) irq = 6; \
+ if (sh2->pending_irq & (1 << 7)) irq = 7; \
+ if (sh2->pending_irq & (1 << 8)) irq = 8; \
+ if (sh2->pending_irq & (1 << 9)) irq = 9; \
+ if (sh2->pending_irq & (1 << 10)) irq = 10; \
+ if (sh2->pending_irq & (1 << 11)) irq = 11; \
+ if (sh2->pending_irq & (1 << 12)) irq = 12; \
+ if (sh2->pending_irq & (1 << 13)) irq = 13; \
+ if (sh2->pending_irq & (1 << 14)) irq = 14; \
+ if (sh2->pending_irq & (1 << 15)) irq = 15; \
if ((sh2->internal_irq_level != -1) && (sh2->internal_irq_level > irq)) irq = sh2->internal_irq_level; \
- if (irq >= 0) \
- sh2_exception(sh2,message,irq); \
+ if (irq >= 0) \
+ sh2_exception(sh2,message,irq); \
} while(0)
struct sh2_state
{
- UINT32 ppc;
- UINT32 pc;
- UINT32 pr;
- UINT32 sr;
- UINT32 gbr, vbr;
- UINT32 mach, macl;
- UINT32 r[16];
- UINT32 ea;
- UINT32 delay;
- UINT32 cpu_off;
- UINT32 dvsr, dvdnth, dvdntl, dvcr;
- UINT32 pending_irq;
- UINT32 test_irq;
- UINT32 pending_nmi;
+ UINT32 ppc;
+ UINT32 pc;
+ UINT32 pr;
+ UINT32 sr;
+ UINT32 gbr, vbr;
+ UINT32 mach, macl;
+ UINT32 r[16];
+ UINT32 ea;
+ UINT32 delay;
+ UINT32 cpu_off;
+ UINT32 dvsr, dvdnth, dvdntl, dvcr;
+ UINT32 pending_irq;
+ UINT32 test_irq;
+ UINT32 pending_nmi;
INT32 irqline;
- UINT32 evec; // exception vector for DRC
- UINT32 irqsr; // IRQ-time old SR for DRC
- UINT32 target; // target for jmp/jsr/etc so the delay slot can't kill it
+ UINT32 evec; // exception vector for DRC
+ UINT32 irqsr; // IRQ-time old SR for DRC
+ UINT32 target; // target for jmp/jsr/etc so the delay slot can't kill it
irq_entry irq_queue[16];
- int pcfsel; // last pcflush entry set
- int maxpcfsel; // highest valid pcflush entry
- UINT32 pcflushes[16]; // pcflush entries
+ int pcfsel; // last pcflush entry set
+ int maxpcfsel; // highest valid pcflush entry
+ UINT32 pcflushes[16]; // pcflush entries
- INT8 irq_line_state[17];
+ INT8 irq_line_state[17];
device_irq_acknowledge_callback irq_callback;
legacy_cpu_device *device;
address_space *program;
direct_read_data *direct;
address_space *internal;
- UINT32 *m;
+ UINT32 *m;
INT8 nmi_line_state;
- UINT16 frc;
- UINT16 ocra, ocrb, icr;
- UINT64 frc_base;
+ UINT16 frc;
+ UINT16 ocra, ocrb, icr;
+ UINT64 frc_base;
- int frt_input;
- int internal_irq_level;
- int internal_irq_vector;
- int icount;
+ int frt_input;
+ int internal_irq_level;
+ int internal_irq_vector;
+ int icount;
emu_timer *timer;
emu_timer *dma_current_active_timer[2];
@@ -150,37 +150,37 @@ struct sh2_state
int (*dma_callback_kludge)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
int (*dma_callback_fifo_data_available)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
- void (*ftcsr_read_callback)(UINT32 data);
+ void (*ftcsr_read_callback)(UINT32 data);
#ifdef USE_SH2DRC
- drc_cache * cache; /* pointer to the DRC code cache */
- drcuml_state * drcuml; /* DRC UML generator state */
- sh2_frontend * drcfe; /* pointer to the DRC front-end state */
- UINT32 drcoptions; /* configurable DRC options */
+ drc_cache * cache; /* pointer to the DRC code cache */
+ drcuml_state * drcuml; /* DRC UML generator state */
+ sh2_frontend * drcfe; /* pointer to the DRC front-end state */
+ UINT32 drcoptions; /* configurable DRC options */
/* internal stuff */
- UINT8 cache_dirty; /* true if we need to flush the cache */
+ UINT8 cache_dirty; /* true if we need to flush the cache */
/* parameters for subroutines */
- UINT64 numcycles; /* return value from gettotalcycles */
- UINT32 arg0; /* print_debug argument 1 */
- UINT32 arg1; /* print_debug argument 2 */
- UINT32 irq; /* irq we're taking */
+ UINT64 numcycles; /* return value from gettotalcycles */
+ UINT32 arg0; /* print_debug argument 1 */
+ UINT32 arg1; /* print_debug argument 2 */
+ UINT32 irq; /* irq we're taking */
/* register mappings */
- uml::parameter regmap[16]; /* parameter to register mappings for all 16 integer registers */
-
- uml::code_handle * entry; /* entry point */
- uml::code_handle * read8; /* read byte */
- uml::code_handle * write8; /* write byte */
- uml::code_handle * read16; /* read half */
- uml::code_handle * write16; /* write half */
- uml::code_handle * read32; /* read word */
- uml::code_handle * write32; /* write word */
-
- uml::code_handle * interrupt; /* interrupt */
- uml::code_handle * nocode; /* nocode */
- uml::code_handle * out_of_cycles; /* out of cycles exception handler */
+ uml::parameter regmap[16]; /* parameter to register mappings for all 16 integer registers */
+
+ uml::code_handle * entry; /* entry point */
+ uml::code_handle * read8; /* read byte */
+ uml::code_handle * write8; /* write byte */
+ uml::code_handle * read16; /* read half */
+ uml::code_handle * write16; /* write half */
+ uml::code_handle * read32; /* read word */
+ uml::code_handle * write32; /* write word */
+
+ uml::code_handle * interrupt; /* interrupt */
+ uml::code_handle * nocode; /* nocode */
+ uml::code_handle * out_of_cycles; /* out of cycles exception handler */
#endif
};