diff options
Diffstat (limited to 'src/emu/cpu/powerpc/ppc.h')
| -rw-r--r-- | src/emu/cpu/powerpc/ppc.h | 96 |
1 files changed, 42 insertions, 54 deletions
diff --git a/src/emu/cpu/powerpc/ppc.h b/src/emu/cpu/powerpc/ppc.h index 009e2118e20..f21b6a78046 100644 --- a/src/emu/cpu/powerpc/ppc.h +++ b/src/emu/cpu/powerpc/ppc.h @@ -159,24 +159,12 @@ enum #define PPCDRC_COMPATIBLE_OPTIONS (PPCDRC_STRICT_VERIFY | PPCDRC_FLUSH_PC | PPCDRC_ACCURATE_SINGLES) #define PPCDRC_FASTEST_OPTIONS (0) - - -/*************************************************************************** - STRUCTURES AND TYPEDEFS -***************************************************************************/ - -typedef void (*ppc4xx_spu_tx_handler)(device_t *device, UINT8 data); - - -typedef void (*ppc_dcstore_handler)(device_t *device, UINT32 address); -typedef UINT32 (*ppc4xx_dma_read_handler)(device_t *device, int width); -typedef void (*ppc4xx_dma_write_handler)(device_t *device, int width, UINT32 data); - - -/*************************************************************************** - PUBLIC FUNCTIONS -***************************************************************************/ - +
+
+/***************************************************************************
+ PUBLIC FUNCTIONS
+***************************************************************************/
+
#define MCFG_PPC_BUS_FREQUENCY(_frequency) \ ppc_device::set_bus_frequency(*device, _frequency); @@ -225,14 +213,14 @@ protected: public: // construction/destruction ppc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int address_bits, int data_bits, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor, address_map_constructor internal_map); - - static void set_bus_frequency(device_t &device, UINT32 bus_frequency) { downcast<ppc_device &>(device).c_bus_frequency = bus_frequency; } - - void ppc_set_dcstore_callback(ppc_dcstore_handler handler); - - void ppcdrc_set_options(UINT32 options); - void ppcdrc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base); - void ppcdrc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles); +
+ static void set_bus_frequency(device_t &device, UINT32 bus_frequency) { downcast<ppc_device &>(device).c_bus_frequency = bus_frequency; }
+
+ void ppc_set_dcstore_callback(write32_delegate callback);
+
+ void ppcdrc_set_options(UINT32 options);
+ void ppcdrc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
+ void ppcdrc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
TIMER_CALLBACK_MEMBER(decrementer_int_callback); TIMER_CALLBACK_MEMBER(ppc4xx_buffered_dma_callback); @@ -491,13 +479,13 @@ protected: UINT8 regs[9]; UINT8 txbuf; UINT8 rxbuf; - emu_timer * timer; - UINT8 rxbuffer[256]; - UINT32 rxin, rxout; - ppc4xx_spu_tx_handler tx_handler; - }; - - ppc4xx_spu_state m_spu; + emu_timer * timer;
+ UINT8 rxbuffer[256];
+ UINT32 rxin, rxout;
+ write8_delegate tx_cb;
+ };
+
+ ppc4xx_spu_state m_spu;
emu_timer * m_fit_timer; emu_timer * m_pit_timer; emu_timer * m_wdog_timer; @@ -515,16 +503,16 @@ protected: UINT64 m_dec_zero_cycles; emu_timer * m_decrementer_int_timer; - read32_delegate m_dcr_read_func; - write32_delegate m_dcr_write_func; - - ppc_dcstore_handler m_dcstore_handler; - - ppc4xx_dma_read_handler m_ext_dma_read_handler[4]; - ppc4xx_dma_write_handler m_ext_dma_write_handler[4]; - - /* PowerPC function pointers for memory accesses/exceptions */ - jmp_buf m_exception_jmpbuf; + read32_delegate m_dcr_read_func;
+ write32_delegate m_dcr_write_func;
+
+ write32_delegate m_dcstore_cb;
+
+ read32_delegate m_ext_dma_read_cb[4];
+ write32_delegate m_ext_dma_write_cb[4];
+
+ /* PowerPC function pointers for memory accesses/exceptions */
+ jmp_buf m_exception_jmpbuf;
UINT8 (*m_ppcread8)(address_space &space, offs_t address); UINT16 (*m_ppcread16)(address_space &space, offs_t address); UINT32 (*m_ppcread32)(address_space &space, offs_t address); @@ -763,17 +751,17 @@ public: class ppc4xx_device : public ppc_device { -public: - ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor); - - void ppc4xx_spu_set_tx_handler(ppc4xx_spu_tx_handler handler); - void ppc4xx_spu_receive_byte(UINT8 byteval); - - void ppc4xx_set_dma_read_handler(int channel, ppc4xx_dma_read_handler handler, int rate); - void ppc4xx_set_dma_write_handler(int channel, ppc4xx_dma_write_handler handler, int rate); - void ppc4xx_set_dcr_read_handler(read32_delegate dcr_read_func); - void ppc4xx_set_dcr_write_handler(write32_delegate dcr_write_func); - +public:
+ ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor);
+
+ void ppc4xx_spu_set_tx_handler(write8_delegate callback);
+ void ppc4xx_spu_receive_byte(UINT8 byteval);
+
+ void ppc4xx_set_dma_read_handler(int channel, read32_delegate callback, int rate);
+ void ppc4xx_set_dma_write_handler(int channel, write32_delegate callback, int rate);
+ void ppc4xx_set_dcr_read_handler(read32_delegate dcr_read_func);
+ void ppc4xx_set_dcr_write_handler(write32_delegate dcr_write_func);
+
DECLARE_READ8_MEMBER( ppc4xx_spu_r ); DECLARE_WRITE8_MEMBER( ppc4xx_spu_w ); |
