summaryrefslogtreecommitdiffstatshomepage
path: root/src/emu/cpu/nec/v25priv.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/emu/cpu/nec/v25priv.h')
-rw-r--r--src/emu/cpu/nec/v25priv.h204
1 files changed, 102 insertions, 102 deletions
diff --git a/src/emu/cpu/nec/v25priv.h b/src/emu/cpu/nec/v25priv.h
index 39e1bf13f8b..68817f2d987 100644
--- a/src/emu/cpu/nec/v25priv.h
+++ b/src/emu/cpu/nec/v25priv.h
@@ -11,52 +11,52 @@
/* interrupt vectors */
enum
{
- NEC_DIVIDE_VECTOR = 0,
- NEC_TRAP_VECTOR = 1,
- NEC_NMI_VECTOR = 2,
- NEC_BRKV_VECTOR = 4,
- NEC_CHKIND_VECTOR = 5,
- NEC_IBRK_VECTOR = 19,
- NEC_INTTU0_VECTOR = 28,
- NEC_INTTU1_VECTOR = 29,
- NEC_INTTU2_VECTOR = 30,
- NEC_INTD0_VECTOR = 20,
- NEC_INTD1_VECTOR = 21,
- NEC_INTP0_VECTOR = 24,
- NEC_INTP1_VECTOR = 25,
- NEC_INTP2_VECTOR = 26,
- NEC_INTSER0_VECTOR = 12,
- NEC_INTSR0_VECTOR = 13,
- NEC_INTST0_VECTOR = 14,
- NEC_INTSER1_VECTOR = 16,
- NEC_INTSR1_VECTOR = 17,
- NEC_INTST1_VECTOR = 18,
- NEC_INTTB_VECTOR = 31
+ NEC_DIVIDE_VECTOR = 0,
+ NEC_TRAP_VECTOR = 1,
+ NEC_NMI_VECTOR = 2,
+ NEC_BRKV_VECTOR = 4,
+ NEC_CHKIND_VECTOR = 5,
+ NEC_IBRK_VECTOR = 19,
+ NEC_INTTU0_VECTOR = 28,
+ NEC_INTTU1_VECTOR = 29,
+ NEC_INTTU2_VECTOR = 30,
+ NEC_INTD0_VECTOR = 20,
+ NEC_INTD1_VECTOR = 21,
+ NEC_INTP0_VECTOR = 24,
+ NEC_INTP1_VECTOR = 25,
+ NEC_INTP2_VECTOR = 26,
+ NEC_INTSER0_VECTOR = 12,
+ NEC_INTSR0_VECTOR = 13,
+ NEC_INTST0_VECTOR = 14,
+ NEC_INTSER1_VECTOR = 16,
+ NEC_INTSR1_VECTOR = 17,
+ NEC_INTST1_VECTOR = 18,
+ NEC_INTTB_VECTOR = 31
};
/* interrupt sources */
enum INTSOURCES
{
- BRK = 0,
- INT_IRQ = 1,
- NMI_IRQ = 1 << 1,
- INTTU0 = 1 << 2,
- INTTU1 = 1 << 3,
- INTTU2 = 1 << 4,
- INTD0 = 1 << 5,
- INTD1 = 1 << 6,
- INTP0 = 1 << 7,
- INTP1 = 1 << 8,
- INTP2 = 1 << 9,
- INTSER0 = 1 << 10,
- INTSR0 = 1 << 11,
- INTST0 = 1 << 12,
- INTSER1 = 1 << 13,
- INTSR1 = 1 << 14,
- INTST1 = 1 << 15,
- INTTB = 1 << 16,
- BRKN = 1 << 17,
- BRKS = 1 << 18
+ BRK = 0,
+ INT_IRQ = 1,
+ NMI_IRQ = 1 << 1,
+ INTTU0 = 1 << 2,
+ INTTU1 = 1 << 3,
+ INTTU2 = 1 << 4,
+ INTD0 = 1 << 5,
+ INTD1 = 1 << 6,
+ INTP0 = 1 << 7,
+ INTP1 = 1 << 8,
+ INTP2 = 1 << 9,
+ INTSER0 = 1 << 10,
+ INTSR0 = 1 << 11,
+ INTST0 = 1 << 12,
+ INTSER1 = 1 << 13,
+ INTSR1 = 1 << 14,
+ INTST1 = 1 << 15,
+ INTTB = 1 << 16,
+ BRKN = 1 << 17,
+ BRKS = 1 << 18
};
/* internal RAM and register banks */
@@ -69,56 +69,56 @@ union internalram
struct v25_state_t
{
internalram ram;
- offs_t fetch_xor;
+ offs_t fetch_xor;
- UINT16 ip;
+ UINT16 ip;
/* PSW flags */
- INT32 SignVal;
- UINT32 AuxVal, OverVal, ZeroVal, CarryVal, ParityVal; /* 0 or non-0 valued flags */
- UINT8 IBRK, F0, F1, TF, IF, DF, MF; /* 0 or 1 valued flags */
- UINT8 RBW, RBB; /* current register bank base, preshifted for word and byte registers */
+ INT32 SignVal;
+ UINT32 AuxVal, OverVal, ZeroVal, CarryVal, ParityVal; /* 0 or non-0 valued flags */
+ UINT8 IBRK, F0, F1, TF, IF, DF, MF; /* 0 or 1 valued flags */
+ UINT8 RBW, RBB; /* current register bank base, preshifted for word and byte registers */
/* interrupt related */
- UINT32 pending_irq;
- UINT32 unmasked_irq;
- UINT32 bankswitch_irq;
- UINT8 priority_inttu, priority_intd, priority_intp, priority_ints0, priority_ints1;
- UINT8 IRQS, ISPR;
- UINT32 nmi_state;
- UINT32 irq_state;
- UINT32 poll_state;
- UINT32 mode_state;
- UINT32 intp_state[3];
- UINT8 no_interrupt;
- UINT8 halted;
+ UINT32 pending_irq;
+ UINT32 unmasked_irq;
+ UINT32 bankswitch_irq;
+ UINT8 priority_inttu, priority_intd, priority_intp, priority_ints0, priority_ints1;
+ UINT8 IRQS, ISPR;
+ UINT32 nmi_state;
+ UINT32 irq_state;
+ UINT32 poll_state;
+ UINT32 mode_state;
+ UINT32 intp_state[3];
+ UINT8 no_interrupt;
+ UINT8 halted;
/* timer related */
- UINT16 TM0, MD0, TM1, MD1;
- UINT8 TMC0, TMC1;
+ UINT16 TM0, MD0, TM1, MD1;
+ UINT8 TMC0, TMC1;
emu_timer *timers[4];
/* system control */
- UINT8 RAMEN, TB, PCK; /* PRC register */
- UINT32 IDB;
+ UINT8 RAMEN, TB, PCK; /* PRC register */
+ UINT32 IDB;
device_irq_acknowledge_callback irq_callback;
legacy_cpu_device *device;
address_space *program;
direct_read_data *direct;
address_space *io;
- int icount;
+ int icount;
const nec_config *config;
- UINT8 prefetch_size;
- UINT8 prefetch_cycles;
- INT8 prefetch_count;
- UINT8 prefetch_reset;
- UINT32 chip_type;
+ UINT8 prefetch_size;
+ UINT8 prefetch_cycles;
+ INT8 prefetch_count;
+ UINT8 prefetch_reset;
+ UINT32 chip_type;
- UINT32 prefix_base; /* base address of the latest prefix segment */
- UINT8 seg_prefix; /* prefix segment indicator */
+ UINT32 prefix_base; /* base address of the latest prefix segment */
+ UINT8 seg_prefix; /* prefix segment indicator */
};
enum {
@@ -146,31 +146,31 @@ enum WREGS {
};
enum BREGS {
- AL = NATIVE_ENDIAN_VALUE_LE_BE(0x1E, 0x1F),
- AH = NATIVE_ENDIAN_VALUE_LE_BE(0x1F, 0x1E),
- CL = NATIVE_ENDIAN_VALUE_LE_BE(0x1C, 0x1D),
- CH = NATIVE_ENDIAN_VALUE_LE_BE(0x1D, 0x1C),
- DL = NATIVE_ENDIAN_VALUE_LE_BE(0x1A, 0x1B),
- DH = NATIVE_ENDIAN_VALUE_LE_BE(0x1B, 0x1A),
- BL = NATIVE_ENDIAN_VALUE_LE_BE(0x18, 0x19),
- BH = NATIVE_ENDIAN_VALUE_LE_BE(0x19, 0x18)
+ AL = NATIVE_ENDIAN_VALUE_LE_BE(0x1E, 0x1F),
+ AH = NATIVE_ENDIAN_VALUE_LE_BE(0x1F, 0x1E),
+ CL = NATIVE_ENDIAN_VALUE_LE_BE(0x1C, 0x1D),
+ CH = NATIVE_ENDIAN_VALUE_LE_BE(0x1D, 0x1C),
+ DL = NATIVE_ENDIAN_VALUE_LE_BE(0x1A, 0x1B),
+ DH = NATIVE_ENDIAN_VALUE_LE_BE(0x1B, 0x1A),
+ BL = NATIVE_ENDIAN_VALUE_LE_BE(0x18, 0x19),
+ BH = NATIVE_ENDIAN_VALUE_LE_BE(0x19, 0x18)
};
-#define SetRB(x) do { nec_state->RBW = (x) << 4; nec_state->RBB = (x) << 5; } while (0)
+#define SetRB(x) do { nec_state->RBW = (x) << 4; nec_state->RBB = (x) << 5; } while (0)
-#define Sreg(x) nec_state->ram.w[nec_state->RBW + (x)]
-#define Wreg(x) nec_state->ram.w[nec_state->RBW + (x)]
-#define Breg(x) nec_state->ram.b[nec_state->RBB + (x)]
+#define Sreg(x) nec_state->ram.w[nec_state->RBW + (x)]
+#define Wreg(x) nec_state->ram.w[nec_state->RBW + (x)]
+#define Breg(x) nec_state->ram.b[nec_state->RBB + (x)]
-#define PC(n) ((Sreg(PS)<<4)+(n)->ip)
+#define PC(n) ((Sreg(PS)<<4)+(n)->ip)
-#define CF (nec_state->CarryVal!=0)
-#define SF (nec_state->SignVal<0)
-#define ZF (nec_state->ZeroVal==0)
-#define PF parity_table[(BYTE)nec_state->ParityVal]
-#define AF (nec_state->AuxVal!=0)
-#define OF (nec_state->OverVal!=0)
-#define RB (nec_state->RBW >> 4)
+#define CF (nec_state->CarryVal!=0)
+#define SF (nec_state->SignVal<0)
+#define ZF (nec_state->ZeroVal==0)
+#define PF parity_table[(BYTE)nec_state->ParityVal]
+#define AF (nec_state->AuxVal!=0)
+#define OF (nec_state->OverVal!=0)
+#define RB (nec_state->RBW >> 4)
/************************************************************************/
@@ -179,15 +179,15 @@ UINT16 v25_read_word(v25_state_t *nec_state, unsigned a);
void v25_write_byte(v25_state_t *nec_state, unsigned a, UINT8 d);
void v25_write_word(v25_state_t *nec_state, unsigned a, UINT16 d);
-#define read_mem_byte(a) v25_read_byte(nec_state,(a))
-#define read_mem_word(a) v25_read_word(nec_state,(a))
-#define write_mem_byte(a,d) v25_write_byte(nec_state,(a),(d))
-#define write_mem_word(a,d) v25_write_word(nec_state,(a),(d))
+#define read_mem_byte(a) v25_read_byte(nec_state,(a))
+#define read_mem_word(a) v25_read_word(nec_state,(a))
+#define write_mem_byte(a,d) v25_write_byte(nec_state,(a),(d))
+#define write_mem_word(a,d) v25_write_word(nec_state,(a),(d))
-#define read_port_byte(a) nec_state->io->read_byte(a)
-#define read_port_word(a) nec_state->io->read_word_unaligned(a)
-#define write_port_byte(a,d) nec_state->io->write_byte((a),(d))
-#define write_port_word(a,d) nec_state->io->write_word_unaligned((a),(d))
+#define read_port_byte(a) nec_state->io->read_byte(a)
+#define read_port_word(a) nec_state->io->read_word_unaligned(a)
+#define write_port_byte(a,d) nec_state->io->write_byte((a),(d))
+#define write_port_word(a,d) nec_state->io->write_word_unaligned((a),(d))
/************************************************************************/
@@ -205,9 +205,9 @@ void v25_write_word(v25_state_t *nec_state, unsigned a, UINT16 d);
/* prefetch timing */
-#define FETCH() fetch(nec_state)
-#define FETCHWORD() fetchword(nec_state)
-#define EMPTY_PREFETCH() nec_state->prefetch_reset = 1
+#define FETCH() fetch(nec_state)
+#define FETCHWORD() fetchword(nec_state)
+#define EMPTY_PREFETCH() nec_state->prefetch_reset = 1
#define PUSH(val) { Wreg(SP) -= 2; write_mem_word(((Sreg(SS)<<4)+Wreg(SP)), val); }