diff options
Diffstat (limited to 'src/emu/cpu/mcs51/mcs51.c')
-rw-r--r-- | src/emu/cpu/mcs51/mcs51.c | 1444 |
1 files changed, 722 insertions, 722 deletions
diff --git a/src/emu/cpu/mcs51/mcs51.c b/src/emu/cpu/mcs51/mcs51.c index 23eabc3708a..b69930223ae 100644 --- a/src/emu/cpu/mcs51/mcs51.c +++ b/src/emu/cpu/mcs51/mcs51.c @@ -143,7 +143,7 @@ #define VERBOSE 0 -#define LOG(x) do { if (VERBOSE) logerror x; } while (0) +#define LOG(x) do { if (VERBOSE) logerror x; } while (0) /*************************************************************************** CONSTANTS @@ -151,64 +151,64 @@ enum { - FEATURE_NONE = 0x00, - FEATURE_I8052 = 0x01, - FEATURE_CMOS = 0x02, - FEATURE_I80C52 = 0x04, - FEATURE_DS5002FP = 0x08, + FEATURE_NONE = 0x00, + FEATURE_I8052 = 0x01, + FEATURE_CMOS = 0x02, + FEATURE_I80C52 = 0x04, + FEATURE_DS5002FP = 0x08, }; /* Internal address in SFR of registers */ enum { - ADDR_PSW = 0xd0, - ADDR_ACC = 0xe0, - ADDR_B = 0xf0, - - ADDR_P0 = 0x80, - ADDR_SP = 0x81, - ADDR_DPL = 0x82, - ADDR_DPH = 0x83, - ADDR_PCON = 0x87, - ADDR_TCON = 0x88, - ADDR_TMOD = 0x89, - ADDR_TL0 = 0x8a, - ADDR_TL1 = 0x8b, - ADDR_TH0 = 0x8c, - ADDR_TH1 = 0x8d, - ADDR_P1 = 0x90, - ADDR_SCON = 0x98, - ADDR_SBUF = 0x99, - ADDR_P2 = 0xa0, - ADDR_IE = 0xa8, - ADDR_P3 = 0xb0, - ADDR_IP = 0xb8, + ADDR_PSW = 0xd0, + ADDR_ACC = 0xe0, + ADDR_B = 0xf0, + + ADDR_P0 = 0x80, + ADDR_SP = 0x81, + ADDR_DPL = 0x82, + ADDR_DPH = 0x83, + ADDR_PCON = 0x87, + ADDR_TCON = 0x88, + ADDR_TMOD = 0x89, + ADDR_TL0 = 0x8a, + ADDR_TL1 = 0x8b, + ADDR_TH0 = 0x8c, + ADDR_TH1 = 0x8d, + ADDR_P1 = 0x90, + ADDR_SCON = 0x98, + ADDR_SBUF = 0x99, + ADDR_P2 = 0xa0, + ADDR_IE = 0xa8, + ADDR_P3 = 0xb0, + ADDR_IP = 0xb8, /* 8052 Only registers */ - ADDR_T2CON = 0xc8, - ADDR_RCAP2L = 0xca, - ADDR_RCAP2H = 0xcb, - ADDR_TL2 = 0xcc, - ADDR_TH2 = 0xcd, + ADDR_T2CON = 0xc8, + ADDR_RCAP2L = 0xca, + ADDR_RCAP2H = 0xcb, + ADDR_TL2 = 0xcc, + ADDR_TH2 = 0xcd, /* 80C52 Only registers */ - ADDR_IPH = 0xb7, - ADDR_SADDR = 0xa9, - ADDR_SADEN = 0xb9, + ADDR_IPH = 0xb7, + ADDR_SADDR = 0xa9, + ADDR_SADEN = 0xb9, /* Philips 80C52 */ - ADDR_AUXR = 0x8e, - ADDR_AUXR1 = 0xa2, + ADDR_AUXR = 0x8e, + ADDR_AUXR1 = 0xa2, /* DS5002FP */ - ADDR_CRCR = 0xc1, - ADDR_CRCL = 0xc2, - ADDR_CRCH = 0xc3, - ADDR_MCON = 0xc6, - ADDR_TA = 0xc7, - ADDR_RNR = 0xcf, - ADDR_RPCTL = 0xd8, - ADDR_RPS = 0xda, + ADDR_CRCR = 0xc1, + ADDR_CRCL = 0xc2, + ADDR_CRCH = 0xc3, + ADDR_MCON = 0xc6, + ADDR_TA = 0xc7, + ADDR_RNR = 0xcf, + ADDR_RPCTL = 0xd8, + ADDR_RPS = 0xda, }; @@ -216,18 +216,18 @@ enum enum { - V_RESET = 0x000, /* power on address */ - V_IE0 = 0x003, /* External Interrupt 0 */ - V_TF0 = 0x00b, /* Timer 0 Overflow */ - V_IE1 = 0x013, /* External Interrupt 1 */ - V_TF1 = 0x01b, /* Timer 1 Overflow */ - V_RITI = 0x023, /* Serial Receive/Transmit */ + V_RESET = 0x000, /* power on address */ + V_IE0 = 0x003, /* External Interrupt 0 */ + V_TF0 = 0x00b, /* Timer 0 Overflow */ + V_IE1 = 0x013, /* External Interrupt 1 */ + V_TF1 = 0x01b, /* Timer 1 Overflow */ + V_RITI = 0x023, /* Serial Receive/Transmit */ /* 8052 Only Vectors */ - V_TF2 = 0x02b, /* Timer 2 Overflow */ + V_TF2 = 0x02b, /* Timer 2 Overflow */ /* DS5002FP */ - V_PFI = 0x02b, /* Power Failure Interrupt */ + V_PFI = 0x02b, /* Power Failure Interrupt */ }; /*************************************************************************** @@ -236,69 +236,69 @@ enum struct mcs51_uart { - UINT8 data_out; //Data to send out - UINT8 bits_to_send; //How many bits left to send when transmitting out the serial port + UINT8 data_out; //Data to send out + UINT8 bits_to_send; //How many bits left to send when transmitting out the serial port - int smod_div; /* signal divided by 2^SMOD */ - int rx_clk; /* rx clock */ - int tx_clk; /* tx clock */ - UINT8 delay_cycles; //Gross Hack; + int smod_div; /* signal divided by 2^SMOD */ + int rx_clk; /* rx clock */ + int tx_clk; /* tx clock */ + UINT8 delay_cycles; //Gross Hack; }; struct mcs51_state_t { //Internal stuff - UINT16 ppc; //previous pc - UINT16 pc; //current pc - UINT16 features; //features of this cpu - UINT8 rwm; //Signals that the current instruction is a read/write/modify instruction - - int inst_cycles; /* cycles for the current instruction */ - int ram_mask; /* second ram bank for indirect access available ? */ - int num_interrupts; /* number of interrupts supported */ - int recalc_parity; /* recalculate parity before next instruction */ - UINT32 last_line_state; /* last state of input lines line */ - int t0_cnt; /* number of 0->1 transistions on T0 line */ - int t1_cnt; /* number of 0->1 transistions on T1 line */ - int t2_cnt; /* number of 0->1 transistions on T2 line */ - int t2ex_cnt; /* number of 0->1 transistions on T2EX line */ - int cur_irq_prio; /* Holds value of the current IRQ Priority Level; -1 if no irq */ - UINT8 irq_active; /* mask which irq levels are serviced */ - UINT8 irq_prio[8]; /* interrupt priority */ - - int icount; - - mcs51_uart uart; /* internal uart */ + UINT16 ppc; //previous pc + UINT16 pc; //current pc + UINT16 features; //features of this cpu + UINT8 rwm; //Signals that the current instruction is a read/write/modify instruction + + int inst_cycles; /* cycles for the current instruction */ + int ram_mask; /* second ram bank for indirect access available ? */ + int num_interrupts; /* number of interrupts supported */ + int recalc_parity; /* recalculate parity before next instruction */ + UINT32 last_line_state; /* last state of input lines line */ + int t0_cnt; /* number of 0->1 transistions on T0 line */ + int t1_cnt; /* number of 0->1 transistions on T1 line */ + int t2_cnt; /* number of 0->1 transistions on T2 line */ + int t2ex_cnt; /* number of 0->1 transistions on T2EX line */ + int cur_irq_prio; /* Holds value of the current IRQ Priority Level; -1 if no irq */ + UINT8 irq_active; /* mask which irq levels are serviced */ + UINT8 irq_prio[8]; /* interrupt priority */ + + int icount; + + mcs51_uart uart; /* internal uart */ /* Internal Ram */ - UINT8 *internal_ram; /* 128 RAM (8031/51) + 128 RAM in second bank (8032/52) */ - UINT8 *sfr_ram; /* 128 SFR - these are in 0x80 - 0xFF */ + UINT8 *internal_ram; /* 128 RAM (8031/51) + 128 RAM in second bank (8032/52) */ + UINT8 *sfr_ram; /* 128 SFR - these are in 0x80 - 0xFF */ /* SFR Callbacks */ - void (*sfr_write)(mcs51_state_t *mcs51_state, size_t offset, UINT8 data); - UINT8 (*sfr_read)(mcs51_state_t *mcs51_state, size_t offset); + void (*sfr_write)(mcs51_state_t *mcs51_state, size_t offset, UINT8 data); + UINT8 (*sfr_read)(mcs51_state_t *mcs51_state, size_t offset); /* Interrupt Callback */ device_irq_acknowledge_callback irq_callback; legacy_cpu_device *device; /* Memory spaces */ - address_space *program; - direct_read_data *direct; - address_space *data; - address_space *io; + address_space *program; + direct_read_data *direct; + address_space *data; + address_space *io; /* Serial Port TX/RX Callbacks */ // TODO: Move to special port r/w - mcs51_serial_tx_func serial_tx_callback; //Call back funciton when sending data out of serial port - mcs51_serial_rx_func serial_rx_callback; //Call back function to retrieve data when receiving serial port data + mcs51_serial_tx_func serial_tx_callback; //Call back funciton when sending data out of serial port + mcs51_serial_rx_func serial_rx_callback; //Call back function to retrieve data when receiving serial port data /* DS5002FP */ struct { - UINT8 previous_ta; /* Previous Timed Access value */ - UINT8 ta_window; /* Limed Access window */ - UINT8 range; /* Memory Range */ - const ds5002fp_config *config; /* Bootstrap Configuration */ + UINT8 previous_ta; /* Previous Timed Access value */ + UINT8 ta_window; /* Limed Access window */ + UINT8 range; /* Memory Range */ + const ds5002fp_config *config; /* Bootstrap Configuration */ } ds5002fp; @@ -309,39 +309,39 @@ struct mcs51_state_t ***************************************************************************/ /* Read Opcode/Opcode Arguments from Program Code */ -#define ROP(pc) mcs51_state->direct->read_decrypted_byte(pc) -#define ROP_ARG(pc) mcs51_state->direct->read_raw_byte(pc) +#define ROP(pc) mcs51_state->direct->read_decrypted_byte(pc) +#define ROP_ARG(pc) mcs51_state->direct->read_raw_byte(pc) /* Read a byte from External Code Memory (Usually Program Rom(s) Space) */ -#define CODEMEM_R(a) (UINT8)mcs51_state->program->read_byte(a) +#define CODEMEM_R(a) (UINT8)mcs51_state->program->read_byte(a) /* Read/Write a byte from/to External Data Memory (Usually RAM or other I/O) */ -#define DATAMEM_R(a) (UINT8)mcs51_state->io->read_byte(a) -#define DATAMEM_W(a,v) mcs51_state->io->write_byte(a, v) +#define DATAMEM_R(a) (UINT8)mcs51_state->io->read_byte(a) +#define DATAMEM_W(a,v) mcs51_state->io->write_byte(a, v) /* Read/Write a byte from/to the Internal RAM */ -#define IRAM_R(a) iram_read(mcs51_state, a) -#define IRAM_W(a, d) iram_write(mcs51_state, a, d) +#define IRAM_R(a) iram_read(mcs51_state, a) +#define IRAM_W(a, d) iram_write(mcs51_state, a, d) /* Read/Write a byte from/to the Internal RAM indirectly */ /* (called from indirect addressing) */ INLINE UINT8 iram_iread(mcs51_state_t *mcs51_state, offs_t a) { return (a <= mcs51_state->ram_mask) ? mcs51_state->data->read_byte(a) : 0xff; } INLINE void iram_iwrite(mcs51_state_t *mcs51_state, offs_t a, UINT8 d) { if (a <= mcs51_state->ram_mask) mcs51_state->data->write_byte(a, d); } -#define IRAM_IR(a) iram_iread(mcs51_state, a) -#define IRAM_IW(a, d) iram_iwrite(mcs51_state, a, d) +#define IRAM_IR(a) iram_iread(mcs51_state, a) +#define IRAM_IW(a, d) iram_iwrite(mcs51_state, a, d) /* Form an Address to Read/Write to External RAM indirectly */ /* (called from indirect addressing) */ -#define ERAM_ADDR(a,m) external_ram_iaddr(mcs51_state, a,m) +#define ERAM_ADDR(a,m) external_ram_iaddr(mcs51_state, a,m) /* Read/Write a bit from Bit Addressable Memory */ -#define BIT_R(a) bit_address_r(mcs51_state, a) -#define BIT_W(a,v) bit_address_w(mcs51_state, a, v) +#define BIT_R(a) bit_address_r(mcs51_state, a) +#define BIT_W(a,v) bit_address_w(mcs51_state, a, v) /* Input/Output a byte from given I/O port */ -#define IN(port) ((UINT8)mcs51_state->io->read_byte(port)) +#define IN(port) ((UINT8)mcs51_state->io->read_byte(port)) #define OUT(port,value) mcs51_state->io->write_byte(port,value) @@ -349,54 +349,54 @@ INLINE void iram_iwrite(mcs51_state_t *mcs51_state, offs_t a, UINT8 d) { if (a < SHORTCUTS ***************************************************************************/ -#define PPC mcs51_state->ppc -#define PC mcs51_state->pc -#define RWM mcs51_state->rwm +#define PPC mcs51_state->ppc +#define PC mcs51_state->pc +#define RWM mcs51_state->rwm /* SFR Registers - These are accessed directly for speed on read */ /* Read accessors */ -#define SFR_A(a) mcs51_state->sfr_ram[(a)] -#define SET_SFR_A(a,v) do { SFR_A(a) = (v); } while (0) - -#define ACC ((const UINT8) SFR_A(ADDR_ACC)) -#define PSW ((const UINT8) SFR_A(ADDR_PSW)) - -#define P0 ((const UINT8) SFR_A(ADDR_P0)) -#define P1 ((const UINT8) SFR_A(ADDR_P1)) -#define P2 ((const UINT8) SFR_A(ADDR_P2)) -#define P3 ((const UINT8) SFR_A(ADDR_P3)) - -#define SP SFR_A(ADDR_SP) -#define DPL SFR_A(ADDR_DPL) -#define DPH SFR_A(ADDR_DPH) -#define PCON SFR_A(ADDR_PCON) -#define TCON SFR_A(ADDR_TCON) -#define TMOD SFR_A(ADDR_TMOD) -#define TL0 SFR_A(ADDR_TL0) -#define TL1 SFR_A(ADDR_TL1) -#define TH0 SFR_A(ADDR_TH0) -#define TH1 SFR_A(ADDR_TH1) -#define SCON SFR_A(ADDR_SCON) -#define IE SFR_A(ADDR_IE) -#define IP SFR_A(ADDR_IP) -#define B SFR_A(ADDR_B) -#define SBUF SFR_A(ADDR_SBUF) - -#define R_REG(r) mcs51_state->internal_ram[(r) | (PSW & 0x18)] -#define DPTR ((DPH<<8) | DPL) +#define SFR_A(a) mcs51_state->sfr_ram[(a)] +#define SET_SFR_A(a,v) do { SFR_A(a) = (v); } while (0) + +#define ACC ((const UINT8) SFR_A(ADDR_ACC)) +#define PSW ((const UINT8) SFR_A(ADDR_PSW)) + +#define P0 ((const UINT8) SFR_A(ADDR_P0)) +#define P1 ((const UINT8) SFR_A(ADDR_P1)) +#define P2 ((const UINT8) SFR_A(ADDR_P2)) +#define P3 ((const UINT8) SFR_A(ADDR_P3)) + +#define SP SFR_A(ADDR_SP) +#define DPL SFR_A(ADDR_DPL) +#define DPH SFR_A(ADDR_DPH) +#define PCON SFR_A(ADDR_PCON) +#define TCON SFR_A(ADDR_TCON) +#define TMOD SFR_A(ADDR_TMOD) +#define TL0 SFR_A(ADDR_TL0) +#define TL1 SFR_A(ADDR_TL1) +#define TH0 SFR_A(ADDR_TH0) +#define TH1 SFR_A(ADDR_TH1) +#define SCON SFR_A(ADDR_SCON) +#define IE SFR_A(ADDR_IE) +#define IP SFR_A(ADDR_IP) +#define B SFR_A(ADDR_B) +#define SBUF SFR_A(ADDR_SBUF) + +#define R_REG(r) mcs51_state->internal_ram[(r) | (PSW & 0x18)] +#define DPTR ((DPH<<8) | DPL) /* 8052 Only registers */ -#define T2CON SFR_A(ADDR_T2CON) -#define RCAP2L SFR_A(ADDR_RCAP2L) -#define RCAP2H SFR_A(ADDR_RCAP2H) -#define TL2 SFR_A(ADDR_TL2) -#define TH2 SFR_A(ADDR_TH2) +#define T2CON SFR_A(ADDR_T2CON) +#define RCAP2L SFR_A(ADDR_RCAP2L) +#define RCAP2H SFR_A(ADDR_RCAP2H) +#define TL2 SFR_A(ADDR_TL2) +#define TH2 SFR_A(ADDR_TH2) /* 80C52 Only registers */ -#define IPH SFR_A(ADDR_IPH) -#define SADDR SFR_A(ADDR_SADDR) -#define SADEN SFR_A(ADDR_SADEN) +#define IPH SFR_A(ADDR_IPH) +#define SADDR SFR_A(ADDR_SADDR) +#define SADEN SFR_A(ADDR_SADEN) /* Philips 80C52 */ /* ============= */ @@ -404,7 +404,7 @@ INLINE void iram_iwrite(mcs51_state_t *mcs51_state, offs_t a, UINT8 d) { if (a < * The AO bit (AUXR.0) in the AUXR register when set disables the * ALE output. */ -#define AUXR SFR_A(ADDR_AUXR) +#define AUXR SFR_A(ADDR_AUXR) /* The dual DPTR structure (see Figure 12) is a way by which the * 80C52/54/58 will specify the address of an external data memory @@ -412,224 +412,224 @@ INLINE void iram_iwrite(mcs51_state_t *mcs51_state, offs_t a, UINT8 d) { if (a < * external memory, and a single bit called DPS = AUXR1/bit0 that * allows the program code to switch between them. */ -#define AUXR1 SFR_A(ADDR_AUXR1) +#define AUXR1 SFR_A(ADDR_AUXR1) /* DS5002FP only registers */ -#define CRCR SFR_A(ADDR_CRCR) -#define CRCL SFR_A(ADDR_CRCL) -#define CRCH SFR_A(ADDR_CRCH) -#define MCON SFR_A(ADDR_MCON) -#define TA SFR_A(ADDR_TA) -#define RNR SFR_A(ADDR_RNR) -#define RPCTL SFR_A(ADDR_RPCTL) -#define RPS SFR_A(ADDR_RPS) +#define CRCR SFR_A(ADDR_CRCR) +#define CRCL SFR_A(ADDR_CRCL) +#define CRCH SFR_A(ADDR_CRCH) +#define MCON SFR_A(ADDR_MCON) +#define TA SFR_A(ADDR_TA) +#define RNR SFR_A(ADDR_RNR) +#define RPCTL SFR_A(ADDR_RPCTL) +#define RPS SFR_A(ADDR_RPS) /* WRITE accessors */ /* Shortcuts */ -#define SET_PSW(v) do { SFR_A(ADDR_PSW) = (v); SET_PARITY(); } while (0) -#define SET_ACC(v) do { SFR_A(ADDR_ACC) = (v); SET_PARITY(); } while (0) +#define SET_PSW(v) do { SFR_A(ADDR_PSW) = (v); SET_PARITY(); } while (0) +#define SET_ACC(v) do { SFR_A(ADDR_ACC) = (v); SET_PARITY(); } while (0) /* These trigger actions on modification and have to be written through SFR_W */ -#define SET_P0(v) IRAM_W(ADDR_P0, v) -#define SET_P1(v) IRAM_W(ADDR_P1, v) -#define SET_P2(v) IRAM_W(ADDR_P2, v) -#define SET_P3(v) IRAM_W(ADDR_P3, v) +#define SET_P0(v) IRAM_W(ADDR_P0, v) +#define SET_P1(v) IRAM_W(ADDR_P1, v) +#define SET_P2(v) IRAM_W(ADDR_P2, v) +#define SET_P3(v) IRAM_W(ADDR_P3, v) /* Within the cpu core, do not trigger a send */ -#define SET_SBUF(v) SET_SFR_A(ADDR_SBUF, v) +#define SET_SBUF(v) SET_SFR_A(ADDR_SBUF, v) /* No actions triggered on write */ -#define SET_REG(r, v) do { mcs51_state->internal_ram[(r) | (PSW & 0x18)] = (v); } while (0) +#define SET_REG(r, v) do { mcs51_state->internal_ram[(r) | (PSW & 0x18)] = (v); } while (0) -#define SET_DPTR(n) do { DPH = ((n) >> 8) & 0xff; DPL = (n) & 0xff; } while (0) +#define SET_DPTR(n) do { DPH = ((n) >> 8) & 0xff; DPL = (n) & 0xff; } while (0) /* Macros for Setting Flags */ #define SET_X(R, v) do { R = (v);} while (0) -#define SET_CY(n) SET_PSW((PSW & 0x7f) | (n<<7)) //Carry Flag -#define SET_AC(n) SET_PSW((PSW & 0xbf) | (n<<6)) //Aux.Carry Flag -#define SET_FO(n) SET_PSW((PSW & 0xdf) | (n<<5)) //User Flag -#define SET_RS(n) SET_PSW((PSW & 0xe7) | (n<<3)) //R Bank Select -#define SET_OV(n) SET_PSW((PSW & 0xfb) | (n<<2)) //Overflow Flag -#define SET_P(n) SET_PSW((PSW & 0xfe) | (n<<0)) //Parity Flag +#define SET_CY(n) SET_PSW((PSW & 0x7f) | (n<<7)) //Carry Flag +#define SET_AC(n) SET_PSW((PSW & 0xbf) | (n<<6)) //Aux.Carry Flag +#define SET_FO(n) SET_PSW((PSW & 0xdf) | (n<<5)) //User Flag +#define SET_RS(n) SET_PSW((PSW & 0xe7) | (n<<3)) //R Bank Select +#define SET_OV(n) SET_PSW((PSW & 0xfb) | (n<<2)) //Overflow Flag +#define SET_P(n) SET_PSW((PSW & 0xfe) | (n<<0)) //Parity Flag #define SET_BIT(R, n, v) do { R = (R & ~(1<<(n))) | ((v) << (n));} while (0) #define GET_BIT(R, n) (((R)>>(n)) & 0x01) -#define SET_EA(n) SET_BIT(IE, 7, n) //Global Interrupt Enable/Disable -#define SET_ES(n) SET_BIT(IE, 4, v) //Serial Interrupt Enable/Disable -#define SET_ET1(n) SET_BIT(IE, 3, n) //Timer 1 Interrupt Enable/Disable -#define SET_EX1(n) SET_BIT(IE, 2, n) //External Int 1 Interrupt Enable/Disable -#define SET_ET0(n) SET_BIT(IE, 1, n) //Timer 0 Interrupt Enable/Disable -#define SET_EX0(n) SET_BIT(IE, 0, n) //External Int 0 Interrupt Enable/Disable +#define SET_EA(n) SET_BIT(IE, 7, n) //Global Interrupt Enable/Disable +#define SET_ES(n) SET_BIT(IE, 4, v) //Serial Interrupt Enable/Disable +#define SET_ET1(n) SET_BIT(IE, 3, n) //Timer 1 Interrupt Enable/Disable +#define SET_EX1(n) SET_BIT(IE, 2, n) //External Int 1 Interrupt Enable/Disable +#define SET_ET0(n) SET_BIT(IE, 1, n) //Timer 0 Interrupt Enable/Disable +#define SET_EX0(n) SET_BIT(IE, 0, n) //External Int 0 Interrupt Enable/Disable /* 8052 Only flags */ -#define SET_ET2(n) SET_BIT(IE, 5, n) //Timer 2 Interrupt Enable/Disable +#define SET_ET2(n) SET_BIT(IE, 5, n) //Timer 2 Interrupt Enable/Disable /* 8052 Only flags */ -#define SET_PT2(n) SET_BIT(IP, 5, n); //Set Timer 2 Priority Level - -#define SET_PS0(n) SET_BIT(IP, 4, n) //Set Serial Priority Level -#define SET_PT1(n) SET_BIT(IP, 3, n) //Set Timer 1 Priority Level -#define SET_PX1(n) SET_BIT(IP, 2, n) //Set External Int 1 Priority Level -#define SET_PT0(n) SET_BIT(IP, 1, n) //Set Timer 0 Priority Level -#define SET_PX0(n) SET_BIT(IP, 0, n) //Set External Int 0 Priority Level - -#define SET_TF1(n) SET_BIT(TCON, 7, n) //Indicated Timer 1 Overflow Int Triggered -#define SET_TR1(n) SET_BIT(TCON, 6, n) //IndicateS Timer 1 is running -#define SET_TF0(n) SET_BIT(TCON, 5, n) //Indicated Timer 0 Overflow Int Triggered -#define SET_TR0(n) SET_BIT(TCON, 4, n) //IndicateS Timer 0 is running -#define SET_IE1(n) SET_BIT(TCON, 3, n) //Indicated External Int 1 Triggered -#define SET_IT1(n) SET_BIT(TCON, 2, n) //Indicates how External Int 1 is Triggered -#define SET_IE0(n) SET_BIT(TCON, 1, n) //Indicated External Int 0 Triggered -#define SET_IT0(n) SET_BIT(TCON, 0, n) //Indicates how External Int 0 is Triggered - -#define SET_SM0(n) SET_BIT(SCON, 7, n) //Sets Serial Port Mode -#define SET_SM1(n) SET_BIT(SCON, 6, n) //Sets Serial Port Mode -#define SET_SM2(n) SET_BIT(SCON, 5, n) //Sets Serial Port Mode (Multiprocesser mode) -#define SET_REN(n) SET_BIT(SCON, 4, n) //Sets Serial Port Receive Enable -#define SET_TB8(n) SET_BIT(SCON, 3, n) //Transmit 8th Bit -#define SET_RB8(n) SET_BIT(SCON, 2, n) //Receive 8th Bit -#define SET_TI(n) SET_BIT(SCON, 1, n) //Indicates Transmit Interrupt Occurred -#define SET_RI(n) SET_BIT(SCON, 0, n) //Indicates Receive Interrupt Occurred - -#define SET_GATE1(n) SET_BIT(TMOD, 7, n) //Timer 1 Gate Mode -#define SET_CT1(n) SET_BIT(TMOD, 6, n) //Timer 1 Counter Mode -#define SET_M1_1(n) SET_BIT(TMOD, 5, n) //Timer 1 Timer Mode Bit 1 -#define SET_M1_0(n) SET_BIT(TMOD, 4, n) //Timer 1 Timer Mode Bit 0 -#define SET_GATE0(n) SET_BIT(TMOD, 3, n) //Timer 0 Gate Mode -#define SET_CT0(n) SET_BIT(TMOD, 2, n) //Timer 0 Counter Mode -#define SET_M0_1(n) SET_BIT(TMOD, 1, n) //Timer 0 Timer Mode Bit 1 -#define SET_M0_0(n) SET_BIT(TMOD, 0, n) //Timer 0 Timer Mode Bit 0 +#define SET_PT2(n) SET_BIT(IP, 5, n); //Set Timer 2 Priority Level + +#define SET_PS0(n) SET_BIT(IP, 4, n) //Set Serial Priority Level +#define SET_PT1(n) SET_BIT(IP, 3, n) //Set Timer 1 Priority Level +#define SET_PX1(n) SET_BIT(IP, 2, n) //Set External Int 1 Priority Level +#define SET_PT0(n) SET_BIT(IP, 1, n) //Set Timer 0 Priority Level +#define SET_PX0(n) SET_BIT(IP, 0, n) //Set External Int 0 Priority Level + +#define SET_TF1(n) SET_BIT(TCON, 7, n) //Indicated Timer 1 Overflow Int Triggered +#define SET_TR1(n) SET_BIT(TCON, 6, n) //IndicateS Timer 1 is running +#define SET_TF0(n) SET_BIT(TCON, 5, n) //Indicated Timer 0 Overflow Int Triggered +#define SET_TR0(n) SET_BIT(TCON, 4, n) //IndicateS Timer 0 is running +#define SET_IE1(n) SET_BIT(TCON, 3, n) //Indicated External Int 1 Triggered +#define SET_IT1(n) SET_BIT(TCON, 2, n) //Indicates how External Int 1 is Triggered +#define SET_IE0(n) SET_BIT(TCON, 1, n) //Indicated External Int 0 Triggered +#define SET_IT0(n) SET_BIT(TCON, 0, n) //Indicates how External Int 0 is Triggered + +#define SET_SM0(n) SET_BIT(SCON, 7, n) //Sets Serial Port Mode +#define SET_SM1(n) SET_BIT(SCON, 6, n) //Sets Serial Port Mode +#define SET_SM2(n) SET_BIT(SCON, 5, n) //Sets Serial Port Mode (Multiprocesser mode) +#define SET_REN(n) SET_BIT(SCON, 4, n) //Sets Serial Port Receive Enable +#define SET_TB8(n) SET_BIT(SCON, 3, n) //Transmit 8th Bit +#define SET_RB8(n) SET_BIT(SCON, 2, n) //Receive 8th Bit +#define SET_TI(n) SET_BIT(SCON, 1, n) //Indicates Transmit Interrupt Occurred +#define SET_RI(n) SET_BIT(SCON, 0, n) //Indicates Receive Interrupt Occurred + +#define SET_GATE1(n) SET_BIT(TMOD, 7, n) //Timer 1 Gate Mode +#define SET_CT1(n) SET_BIT(TMOD, 6, n) //Timer 1 Counter Mode +#define SET_M1_1(n) SET_BIT(TMOD, 5, n) //Timer 1 Timer Mode Bit 1 +#define SET_M1_0(n) SET_BIT(TMOD, 4, n) //Timer 1 Timer Mode Bit 0 +#define SET_GATE0(n) SET_BIT(TMOD, 3, n) //Timer 0 Gate Mode +#define SET_CT0(n) SET_BIT(TMOD, 2, n) //Timer 0 Counter Mode +#define SET_M0_1(n) SET_BIT(TMOD, 1, n) //Timer 0 Timer Mode Bit 1 +#define SET_M0_0(n) SET_BIT(TMOD, 0, n) //Timer 0 Timer Mode Bit 0 /* 8052 Only flags - T2CON Flags */ -#define SET_TF2(n) SET_BIT(T2CON, 7, n) //Indicated Timer 2 Overflow Int Triggered -#define SET_EXF2(n) SET_BIT(T2CON, 6, n) //Indicates Timer 2 External Flag -#define SET_RCLK(n) SET_BIT(T2CON, 5, n) //Receive Clock -#define SET_TCLK(n) SET_BIT(T2CON, 4, n) //Transmit Clock -#define SET_EXEN2(n) SET_BIT(T2CON, 3, n) //Timer 2 External Interrupt Enable -#define SET_TR2(n) SET_BIT(T2CON, 2, n) //Indicates Timer 2 is running -#define SET_CT2(n) SET_BIT(T2CON, 1, n) //Sets Timer 2 Counter/Timer Mode -#define SET_CP(n) SET_BIT(T2CON, 0, n) //Sets Timer 2 Capture/Reload Mode - -#define SET_GF1(n) SET_BIT(PCON, 3, n) -#define SET_GF0(n) SET_BIT(PCON, 2, n) -#define SET_PD(n) SET_BIT(PCON, 1, n) -#define SET_IDL(n) SET_BIT(PCON, 0, n) +#define SET_TF2(n) SET_BIT(T2CON, 7, n) //Indicated Timer 2 Overflow Int Triggered +#define SET_EXF2(n) SET_BIT(T2CON, 6, n) //Indicates Timer 2 External Flag +#define SET_RCLK(n) SET_BIT(T2CON, 5, n) //Receive Clock +#define SET_TCLK(n) SET_BIT(T2CON, 4, n) //Transmit Clock +#define SET_EXEN2(n) SET_BIT(T2CON, 3, n) //Timer 2 External Interrupt Enable +#define SET_TR2(n) SET_BIT(T2CON, 2, n) //Indicates Timer 2 is running +#define SET_CT2(n) SET_BIT(T2CON, 1, n) //Sets Timer 2 Counter/Timer Mode +#define SET_CP(n) SET_BIT(T2CON, 0, n) //Sets Timer 2 Capture/Reload Mode + +#define SET_GF1(n) SET_BIT(PCON, 3, n) +#define SET_GF0(n) SET_BIT(PCON, 2, n) +#define SET_PD(n) SET_BIT(PCON, 1, n) +#define SET_IDL(n) SET_BIT(PCON, 0, n) /* Macros for accessing flags */ -#define GET_CY GET_BIT(PSW, 7) -#define GET_AC GET_BIT(PSW, 6) -#define GET_FO GET_BIT(PSW, 5) -#define GET_RS GET_BIT(PSW, 3) -#define GET_OV GET_BIT(PSW, 2) -#define GET_P GET_BIT(PSW, 0) - -#define GET_EA GET_BIT(IE, 7) -#define GET_ET2 GET_BIT(IE, 5) -#define GET_ES GET_BIT(IE, 4) -#define GET_ET1 GET_BIT(IE, 3) -#define GET_EX1 GET_BIT(IE, 2) -#define GET_ET0 GET_BIT(IE, 1) -#define GET_EX0 GET_BIT(IE, 0) +#define GET_CY GET_BIT(PSW, 7) +#define GET_AC GET_BIT(PSW, 6) +#define GET_FO GET_BIT(PSW, 5) +#define GET_RS GET_BIT(PSW, 3) +#define GET_OV GET_BIT(PSW, 2) +#define GET_P GET_BIT(PSW, 0) + +#define GET_EA GET_BIT(IE, 7) +#define GET_ET2 GET_BIT(IE, 5) +#define GET_ES GET_BIT(IE, 4) +#define GET_ET1 GET_BIT(IE, 3) +#define GET_EX1 GET_BIT(IE, 2) +#define GET_ET0 GET_BIT(IE, 1) +#define GET_EX0 GET_BIT(IE, 0) /* 8052 Only flags */ -#define GET_PT2 GET_BIT(IP, 5) - -#define GET_PS GET_BIT(IP, 4) -#define GET_PT1 GET_BIT(IP, 3) -#define GET_PX1 GET_BIT(IP, 2) -#define GET_PT0 GET_BIT(IP, 1) -#define GET_PX0 GET_BIT(IP, 0) - -#define GET_TF1 GET_BIT(TCON, 7) -#define GET_TR1 GET_BIT(TCON, 6) -#define GET_TF0 GET_BIT(TCON, 5) -#define GET_TR0 GET_BIT(TCON, 4) -#define GET_IE1 GET_BIT(TCON, 3) -#define GET_IT1 GET_BIT(TCON, 2) -#define GET_IE0 GET_BIT(TCON, 1) -#define GET_IT0 GET_BIT(TCON, 0) - -#define GET_SM0 GET_BIT(SCON, 7) -#define GET_SM1 GET_BIT(SCON, 6) -#define GET_SM2 GET_BIT(SCON, 5) -#define GET_REN GET_BIT(SCON, 4) -#define GET_TB8 GET_BIT(SCON, 3) -#define GET_RB8 GET_BIT(SCON, 2) -#define GET_TI GET_BIT(SCON, 1) -#define GET_RI GET_BIT(SCON, 0) - -#define GET_GATE1 GET_BIT(TMOD, 7) -#define GET_CT1 GET_BIT(TMOD, 6) -#define GET_M1_1 GET_BIT(TMOD, 5) -#define GET_M1_0 GET_BIT(TMOD, 4) -#define GET_GATE0 GET_BIT(TMOD, 3) -#define GET_CT0 GET_BIT(TMOD, 2) -#define GET_M0_1 GET_BIT(TMOD, 1) -#define GET_M0_0 GET_BIT(TMOD, 0) - -#define GET_SMOD GET_BIT(PCON, 7) +#define GET_PT2 GET_BIT(IP, 5) + +#define GET_PS GET_BIT(IP, 4) +#define GET_PT1 GET_BIT(IP, 3) +#define GET_PX1 GET_BIT(IP, 2) +#define GET_PT0 GET_BIT(IP, 1) +#define GET_PX0 GET_BIT(IP, 0) + +#define GET_TF1 GET_BIT(TCON, 7) +#define GET_TR1 GET_BIT(TCON, 6) +#define GET_TF0 GET_BIT(TCON, 5) +#define GET_TR0 GET_BIT(TCON, 4) +#define GET_IE1 GET_BIT(TCON, 3) +#define GET_IT1 GET_BIT(TCON, 2) +#define GET_IE0 GET_BIT(TCON, 1) +#define GET_IT0 GET_BIT(TCON, 0) + +#define GET_SM0 GET_BIT(SCON, 7) +#define GET_SM1 GET_BIT(SCON, 6) +#define GET_SM2 GET_BIT(SCON, 5) +#define GET_REN GET_BIT(SCON, 4) +#define GET_TB8 GET_BIT(SCON, 3) +#define GET_RB8 GET_BIT(SCON, 2) +#define GET_TI GET_BIT(SCON, 1) +#define GET_RI GET_BIT(SCON, 0) + +#define GET_GATE1 GET_BIT(TMOD, 7) +#define GET_CT1 GET_BIT(TMOD, 6) +#define GET_M1_1 GET_BIT(TMOD, 5) +#define GET_M1_0 GET_BIT(TMOD, 4) +#define GET_GATE0 GET_BIT(TMOD, 3) +#define GET_CT0 GET_BIT(TMOD, 2) +#define GET_M0_1 GET_BIT(TMOD, 1) +#define GET_M0_0 GET_BIT(TMOD, 0) + +#define GET_SMOD GET_BIT(PCON, 7) /* Only in 80C51BH & other cmos */ -#define GET_GF1 GET_BIT(PCON, 3) -#define GET_GF0 GET_BIT(PCON, 2) -#define GET_PD GET_BIT(PCON, 1) -#define GET_IDL (GET_BIT(PCON, 0) & ~(GET_PD)) /* PD takes precedence! */ +#define GET_GF1 GET_BIT(PCON, 3) +#define GET_GF0 GET_BIT(PCON, 2) +#define GET_PD GET_BIT(PCON, 1) +#define GET_IDL (GET_BIT(PCON, 0) & ~(GET_PD)) /* PD takes precedence! */ /* 8052 Only flags */ -#define GET_TF2 GET_BIT(T2CON, 7) -#define GET_EXF2 GET_BIT(T2CON, 6) -#define GET_RCLK GET_BIT(T2CON, 5) -#define GET_TCLK GET_BIT(T2CON, 4) -#define GET_EXEN2 GET_BIT(T2CON, 3) -#define GET_TR2 GET_BIT(T2CON, 2) -#define GET_CT2 GET_BIT(T2CON, 1) -#define GET_CP GET_BIT(T2CON, 0) +#define GET_TF2 GET_BIT(T2CON, 7) +#define GET_EXF2 GET_BIT(T2CON, 6) +#define GET_RCLK GET_BIT(T2CON, 5) +#define GET_TCLK GET_BIT(T2CON, 4) +#define GET_EXEN2 GET_BIT(T2CON, 3) +#define GET_TR2 GET_BIT(T2CON, 2) +#define GET_CT2 GET_BIT(T2CON, 1) +#define GET_CP GET_BIT(T2CON, 0) /* DS5002FP Only flags */ /* PCON Flags - DS5002FP */ -#define GET_POR GET_BIT(PCON, 6) -#define GET_PFW GET_BIT(PCON, 5) -#define GET_WTR GET_BIT(PCON, 4) -#define GET_EPFW GET_BIT(PCON, 3) -#define GET_EWT GET_BIT(PCON, 2) +#define GET_POR GET_BIT(PCON, 6) +#define GET_PFW GET_BIT(PCON, 5) +#define GET_WTR GET_BIT(PCON, 4) +#define GET_EPFW GET_BIT(PCON, 3) +#define GET_EWT GET_BIT(PCON, 2) -#define SET_PFW(n) SET_BIT(PCON, 5, n) +#define SET_PFW(n) SET_BIT(PCON, 5, n) /* MCON Flags - DS5002FP */ -#define GET_PA ((MCON & 0xf0)>>4) -#define GET_RG1 GET_BIT(MCON, 3) -#define GET_PES GET_BIT(MCON, 2) -#define GET_PM GET_BIT(MCON, 1) -#define GET_SL GET_BIT(MCON, 0) +#define GET_PA ((MCON & 0xf0)>>4) +#define GET_RG1 GET_BIT(MCON, 3) +#define GET_PES GET_BIT(MCON, 2) +#define GET_PM GET_BIT(MCON, 1) +#define GET_SL GET_BIT(MCON, 0) /* RPCTL Flags - DS5002FP */ -#define GET_RNR GET_BIT(RPCTL, 7) /* Bit 6 ?? */ -#define GET_EXBS GET_BIT(RPCTL, 5) -#define GET_AE GET_BIT(RPCTL, 4) -#define GET_IBI GET_BIT(RPCTL, 3) -#define GET_DMA GET_BIT(RPCTL, 2) -#define GET_RPCON GET_BIT(RPCTL, 1) -#define GET_RG0 GET_BIT(RPCTL, 0) +#define GET_RNR GET_BIT(RPCTL, 7) /* Bit 6 ?? */ +#define GET_EXBS GET_BIT(RPCTL, 5) +#define GET_AE GET_BIT(RPCTL, 4) +#define GET_IBI GET_BIT(RPCTL, 3) +#define GET_DMA GET_BIT(RPCTL, 2) +#define GET_RPCON GET_BIT(RPCTL, 1) +#define GET_RG0 GET_BIT(RPCTL, 0) /*Add and Subtract Flag settings*/ -#define DO_ADD_FLAGS(a,d,c) do_add_flags(mcs51_state, a, d, c) -#define DO_SUB_FLAGS(a,d,c) do_sub_flags(mcs51_state, a, d, c) +#define DO_ADD_FLAGS(a,d,c) do_add_flags(mcs51_state, a, d, c) +#define DO_SUB_FLAGS(a,d,c) do_sub_flags(mcs51_state, a, d, c) -#define SET_PARITY() do {mcs51_state->recalc_parity |= 1;} while (0) -#define PUSH_PC() push_pc(mcs51_state) -#define POP_PC() pop_pc(mcs51_state) +#define SET_PARITY() do {mcs51_state->recalc_parity |= 1;} while (0) +#define PUSH_PC() push_pc(mcs51_state) +#define POP_PC() pop_pc(mcs51_state) /* Clear Current IRQ */ #define CLEAR_CURRENT_IRQ() clear_current_irq(mcs51_state) @@ -651,19 +651,19 @@ INLINE mcs51_state_t *get_safe_token(device_t *device) { assert(device != NULL); assert(device->type() == I8031 || - device->type() == I8032 || - device->type() == I8051 || - device->type() == I8751 || - device->type() == I8052 || - device->type() == I8752 || - device->type() == I80C31 || - device->type() == I80C32 || - device->type() == I80C51 || - device->type() == I80C52 || - device->type() == I87C51 || - device->type() == I87C52 || - device->type() == AT89C4051 || - device->type() == DS5002FP); + device->type() == I8032 || + device->type() == I8051 || + device->type() == I8751 || + device->type() == I8052 || + device->type() == I8752 || + device->type() == I80C31 || + device->type() == I80C32 || + device->type() == I80C51 || + device->type() == I80C52 || + device->type() == I87C51 || + device->type() == I87C52 || + device->type() == AT89C4051 || + device->type() == DS5002FP); return (mcs51_state_t *)downcast<legacy_cpu_device *>(device)->token(); } @@ -731,7 +731,7 @@ INLINE offs_t external_ram_iaddr(mcs51_state_t *mcs51_state, offs_t offset, offs /* Memory Partition Table (RG1 & RG0 @ MCON & RPCTL registers) */ static const UINT32 ds5002fp_partitions[16] = { 0x0000, 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x6000, 0x7000, - 0x8000, 0x9000, 0xa000, 0xb000, 0xc000, 0xd000, 0xe000, 0x10000 }; + 0x8000, 0x9000, 0xa000, 0xb000, 0xc000, 0xd000, 0xe000, 0x10000 }; /* if partition mode is set, adjust offset based on the bus */ if (mcs51_state->features & FEATURE_DS5002FP) @@ -770,20 +770,20 @@ INLINE void iram_write(mcs51_state_t *mcs51_state, size_t offset, UINT8 data) /*Push the current PC to the stack*/ INLINE void push_pc(mcs51_state_t *mcs51_state) { - UINT8 tmpSP = SP+1; //Grab and Increment Stack Pointer - IRAM_IW(tmpSP, (PC & 0xff)); //Store low byte of PC to Internal Ram (Use IRAM_IW to store stack above 128 bytes) - tmpSP++; // "" - SP = tmpSP; // "" - IRAM_IW(tmpSP, ( (PC & 0xff00) >> 8)); //Store hi byte of PC to next address in Internal Ram (Use IRAM_IW to store stack above 128 bytes) + UINT8 tmpSP = SP+1; //Grab and Increment Stack Pointer + IRAM_IW(tmpSP, (PC & 0xff)); //Store low byte of PC to Internal Ram (Use IRAM_IW to store stack above 128 bytes) + tmpSP++; // "" + SP = tmpSP; // "" + IRAM_IW(tmpSP, ( (PC & 0xff00) >> 8)); //Store hi byte of PC to next address in Internal Ram (Use IRAM_IW to store stack above 128 bytes) } /*Pop the current PC off the stack and into the pc*/ INLINE void pop_pc(mcs51_state_t *mcs51_state) { - UINT8 tmpSP = SP; //Grab Stack Pointer - PC = (IRAM_IR(tmpSP--) & 0xff) << 8; //Store hi byte to PC (must use IRAM_IR to access stack pointing above 128 bytes) - PC = PC | IRAM_IR(tmpSP--); //Store lo byte to PC (must use IRAM_IR to access stack pointing above 128 bytes) - SP = tmpSP; //Decrement Stack Pointer + UINT8 tmpSP = SP; //Grab Stack Pointer + PC = (IRAM_IR(tmpSP--) & 0xff) << 8; //Store hi byte to PC (must use IRAM_IR to access stack pointing above 128 bytes) + PC = PC | IRAM_IR(tmpSP--); //Store lo byte to PC (must use IRAM_IR to access stack pointing above 128 bytes) + SP = tmpSP; //Decrement Stack Pointer } //Set the PSW Parity Flag @@ -794,7 +794,7 @@ INLINE void set_parity(mcs51_state_t *mcs51_state) int i; UINT8 a = ACC; - for (i=0; i<8; i++) { //Test for each of the 8 bits in the ACC! + for (i=0; i<8; i++) { //Test for each of the 8 bits in the ACC! p ^= (a & 1); a = (a >> 1); } @@ -804,10 +804,10 @@ INLINE void set_parity(mcs51_state_t *mcs51_state) INLINE UINT8 bit_address_r(mcs51_state_t *mcs51_state, UINT8 offset) { - UINT8 word; - UINT8 mask; - int bit_pos; - int distance; /* distance between bit addressable words */ + UINT8 word; + UINT8 mask; + int bit_pos; + int distance; /* distance between bit addressable words */ /* 1 for normal bits, 8 for sfr bit addresses */ //User defined bit addresses 0x20-0x2f (values are 0x0-0x7f) @@ -831,11 +831,11 @@ INLINE UINT8 bit_address_r(mcs51_state_t *mcs51_state, UINT8 offset) INLINE void bit_address_w(mcs51_state_t *mcs51_state, UINT8 offset, UINT8 bit) { - int word; - UINT8 mask; - int bit_pos; - UINT8 result; - int distance; + int word; + UINT8 mask; + int bit_pos; + UINT8 result; + int distance; /* User defined bit addresses 0x20-0x2f (values are 0x0-0x7f) */ if (offset < 0x80) { @@ -971,13 +971,13 @@ INLINE void update_timer_t0(mcs51_state_t *mcs51_state, int cycles) /* taken, reset */ mcs51_state->t0_cnt = 0; /* TODO: Not sure about IE0. The manual specifies INT0=high, - * which in turn means CLEAR_LINE. - * IE0 may be edge triggered depending on IT0 */ + * which in turn means CLEAR_LINE. + * IE0 may be edge triggered depending on IT0 */ if (GET_GATE0 && !GET_IE0) delta = 0; switch(mode) { - case 0: /* 13 Bit Timer Mode */ + case 0: /* 13 Bit Timer Mode */ count = ((TH0<<5) | ( TL0 & 0x1f ) ); count += delta; if ( count & 0xffffe000 ) /* Check for overflow */ @@ -985,7 +985,7 @@ INLINE void update_timer_t0(mcs51_state_t *mcs51_state, int cycles) TH0 = (count>>5) & 0xff; TL0 = count & 0x1f ; break; - case 1: /* 16 Bit Timer Mode */ + case 1: /* 16 Bit Timer Mode */ count = ((TH0<<8) | TL0); count += delta; if ( count & 0xffff0000 ) /* Check for overflow */ @@ -993,12 +993,12 @@ INLINE void update_timer_t0(mcs51_state_t *mcs51_state, int cycles) TH0 = (count>>8) & 0xff; TL0 = count & 0xff; break; - case 2: /* 8 Bit Autoreload */ + case 2: /* 8 Bit Autoreload */ count = ((UINT32) TL0) + delta; - if ( count & 0xffffff00 ) /* Check for overflow */ + if ( count & 0xffffff00 ) /* Check for overflow */ { SET_TF0(1); - count += TH0; /* Reload timer */ + count += TH0; /* Reload timer */ } /* Update new values of the counter */ TL0 = count & 0xff; @@ -1006,9 +1006,9 @@ INLINE void update_timer_t0(mcs51_state_t *mcs51_state, int cycles) case 3: /* Split Timer 1 */ count = ((UINT32) TL0) + delta; - if ( count & 0xffffff00 ) /* Check for overflow */ + if ( count & 0xffffff00 ) /* Check for overflow */ SET_TF0(1); - TL0 = count & 0xff; /* Update new values of the counter */ + TL0 = count & 0xff; /* Update new values of the counter */ break; } } @@ -1018,10 +1018,10 @@ INLINE void update_timer_t0(mcs51_state_t *mcs51_state, int cycles) { case 3: /* Split Timer 2 */ - count = ((UINT32) TH0) + cycles; /* No gate control or counting !*/ - if ( count & 0xffffff00 ) /* Check for overflow */ + count = ((UINT32) TH0) + cycles; /* No gate control or counting !*/ + if ( count & 0xffffff00 ) /* Check for overflow */ SET_TF1(1); - TH0 = count & 0xff; /* Update new values of the counter */ + TH0 = count & 0xff; /* Update new values of the counter */ break; } } @@ -1061,32 +1061,32 @@ INLINE void update_timer_t1(mcs51_state_t *mcs51_state, int cycles) /* taken, reset */ mcs51_state->t1_cnt = 0; /* TODO: Not sure about IE0. The manual specifies INT0=high, - * which in turn means CLEAR_LINE. Change to access last_state? - * IE0 may be edge triggered depending on IT0 */ + * which in turn means CLEAR_LINE. Change to access last_state? + * IE0 may be edge triggered depending on IT0 */ if (GET_GATE1 && !GET_IE1) delta = 0; switch(mode) { - case 0: /* 13 Bit Timer Mode */ + case 0: /* 13 Bit Timer Mode */ count = ((TH1<<5) | ( TL1 & 0x1f ) ); count += delta; overflow = count & 0xffffe000; /* Check for overflow */ TH1 = (count>>5) & 0xff; TL1 = count & 0x1f ; break; - case 1: /* 16 Bit Timer Mode */ + case 1: /* 16 Bit Timer Mode */ count = ((TH1<<8) | TL1); count += delta; overflow = count & 0xffff0000; /* Check for overflow */ TH1 = (count>>8) & 0xff; TL1 = count & 0xff; break; - case 2: /* 8 Bit Autoreload */ + case 2: /* 8 Bit Autoreload */ count = ((UINT32) TL1) + delta; overflow = count & 0xffffff00; /* Check for overflow */ if ( overflow ) { - count += TH1; /* Reload timer */ + count += TH1; /* Reload timer */ } /* Update new values of the counter */ TL1 = count & 0xff; @@ -1111,26 +1111,26 @@ INLINE void update_timer_t1(mcs51_state_t *mcs51_state, int cycles) /* taken, reset */ mcs51_state->t1_cnt = 0; switch(mode) { - case 0: /* 13 Bit Timer Mode */ + case 0: /* 13 Bit Timer Mode */ count = ((TH1<<5) | ( TL1 & 0x1f ) ); count += delta; overflow = count & 0xffffe000; /* Check for overflow */ TH1 = (count>>5) & 0xff; TL1 = count & 0x1f ; break; - case 1: /* 16 Bit Timer Mode */ + case 1: /* 16 Bit Timer Mode */ count = ((TH1<<8) | TL1); count += delta; overflow = count & 0xffff0000; /* Check for overflow */ TH1 = (count>>8) & 0xff; TL1 = count & 0xff; break; - case 2: /* 8 Bit Autoreload */ + case 2: /* 8 Bit Autoreload */ count = ((UINT32) TL1) + delta; overflow = count & 0xffffff00; /* Check for overflow */ if ( overflow ) { - count += TH1; /* Reload timer */ + count += TH1; /* Reload timer */ } /* Update new values of the counter */ TL1 = count & 0xff; @@ -1158,7 +1158,7 @@ INLINE void update_timer_t2(mcs51_state_t *mcs51_state, int cycles) switch (mode) { - case 0: /* 16 Bit Auto Reload */ + case 0: /* 16 Bit Auto Reload */ if ( count & 0xffff0000 ) { SET_TF2(1); @@ -1186,7 +1186,7 @@ INLINE void update_timer_t2(mcs51_state_t *mcs51_state, int cycles) } break; case 2: - case 3: /* Baud rate */ + case 3: /* Baud rate */ if ( count & 0xffff0000 ) { count += ((RCAP2H<<8) | RCAP2L); @@ -1264,14 +1264,14 @@ INLINE void serial_receive(mcs51_state_t *mcs51_state) } /* Check and update status of serial port */ -INLINE void update_serial(mcs51_state_t *mcs51_state, int cycles) +INLINE void update_serial(mcs51_state_t *mcs51_state, int cycles) { while (--cycles>=0) transmit_receive(mcs51_state, 0); } /* Check and update status of serial port */ -INLINE void update_irq_prio(mcs51_state_t *mcs51_state, UINT8 ipl, UINT8 iph) +INLINE void update_irq_prio(mcs51_state_t *mcs51_state, UINT8 ipl, UINT8 iph) { int i; for (i=0; i<8; i++) @@ -1315,15 +1315,15 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) switch( op ) { - case 0x00: nop(mcs51_state, op); break; //NOP - case 0x01: ajmp(mcs51_state, op); break; //AJMP code addr - case 0x02: ljmp(mcs51_state, op); break; //LJMP code addr - case 0x03: rr_a(mcs51_state, op); break; //RR A - case 0x04: inc_a(mcs51_state, op); break; //INC A - case 0x05: RWM=1; inc_mem(mcs51_state, op); RWM=0; break; //INC data addr + case 0x00: nop(mcs51_state, op); break; //NOP + case 0x01: ajmp(mcs51_state, op); break; //AJMP code addr + case 0x02: ljmp(mcs51_state, op); break; //LJMP code addr + case 0x03: rr_a(mcs51_state, op); break; //RR A + case 0x04: inc_a(mcs51_state, op); break; //INC A + case 0x05: RWM=1; inc_mem(mcs51_state, op); RWM=0; break; //INC data addr case 0x06: - case 0x07: inc_ir(mcs51_state,op&1); break; //INC @R0/@R1 + case 0x07: inc_ir(mcs51_state,op&1); break; //INC @R0/@R1 case 0x08: case 0x09: @@ -1332,17 +1332,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0x0c: case 0x0d: case 0x0e: - case 0x0f: inc_r(mcs51_state, op&7); break; //INC R0 to R7 + case 0x0f: inc_r(mcs51_state, op&7); break; //INC R0 to R7 - case 0x10: RWM=1; jbc(mcs51_state, op); RWM=0; break; //JBC bit addr, code addr - case 0x11: acall(mcs51_state, op); break; //ACALL code addr - case 0x12: lcall(mcs51_state, op); break; //LCALL code addr - case 0x13: rrc_a(mcs51_state, op); break; //RRC A - case 0x14: dec_a(mcs51_state, op); break; //DEC A - case 0x15: RWM=1; dec_mem(mcs51_state, op); RWM=0; break; //DEC data addr + case 0x10: RWM=1; jbc(mcs51_state, op); RWM=0; break; //JBC bit addr, code addr + case 0x11: acall(mcs51_state, op); break; //ACALL code addr + case 0x12: lcall(mcs51_state, op); break; //LCALL code addr + case 0x13: rrc_a(mcs51_state, op); break; //RRC A + case 0x14: dec_a(mcs51_state, op); break; //DEC A + case 0x15: RWM=1; dec_mem(mcs51_state, op); RWM=0; break; //DEC data addr case 0x16: - case 0x17: dec_ir(mcs51_state, op&1); break; //DEC @R0/@R1 + case 0x17: dec_ir(mcs51_state, op&1); break; //DEC @R0/@R1 case 0x18: case 0x19: @@ -1351,17 +1351,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0x1c: case 0x1d: case 0x1e: - case 0x1f: dec_r(mcs51_state, op&7); break; //DEC R0 to R7 + case 0x1f: dec_r(mcs51_state, op&7); break; //DEC R0 to R7 - case 0x20: jb(mcs51_state, op); break; //JB bit addr, code addr - case 0x21: ajmp(mcs51_state, op); break; //AJMP code addr - case 0x22: ret(mcs51_state, op); break; //RET - case 0x23: rl_a(mcs51_state, op); break; //RL A - case 0x24: add_a_byte(mcs51_state, op); break; //ADD A, #data - case 0x25: add_a_mem(mcs51_state, op); break; //ADD A, data addr + case 0x20: jb(mcs51_state, op); break; //JB bit addr, code addr + case 0x21: ajmp(mcs51_state, op); break; //AJMP code addr + case 0x22: ret(mcs51_state, op); break; //RET + case 0x23: rl_a(mcs51_state, op); break; //RL A + case 0x24: add_a_byte(mcs51_state, op); break; //ADD A, #data + case 0x25: add_a_mem(mcs51_state, op); break; //ADD A, data addr case 0x26: - case 0x27: add_a_ir(mcs51_state, op&1); break; //ADD A, @R0/@R1 + case 0x27: add_a_ir(mcs51_state, op&1); break; //ADD A, @R0/@R1 case 0x28: case 0x29: @@ -1370,17 +1370,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0x2c: case 0x2d: case 0x2e: - case 0x2f: add_a_r(mcs51_state, op&7); break; //ADD A, R0 to R7 + case 0x2f: add_a_r(mcs51_state, op&7); break; //ADD A, R0 to R7 - case 0x30: jnb(mcs51_state, op); break; //JNB bit addr, code addr - case 0x31: acall(mcs51_state, op); break; //ACALL code addr - case 0x32: reti(mcs51_state, op); break; //RETI - case 0x33: rlc_a(mcs51_state, op); break; //RLC A - case 0x34: addc_a_byte(mcs51_state, op); break; //ADDC A, #data - case 0x35: addc_a_mem(mcs51_state, op); break; //ADDC A, data addr + case 0x30: jnb(mcs51_state, op); break; //JNB bit addr, code addr + case 0x31: acall(mcs51_state, op); break; //ACALL code addr + case 0x32: reti(mcs51_state, op); break; //RETI + case 0x33: rlc_a(mcs51_state, op); break; //RLC A + case 0x34: addc_a_byte(mcs51_state, op); break; //ADDC A, #data + case 0x35: addc_a_mem(mcs51_state, op); break; //ADDC A, data addr case 0x36: - case 0x37: addc_a_ir(mcs51_state, op&1); break; //ADDC A, @R0/@R1 + case 0x37: addc_a_ir(mcs51_state, op&1); break; //ADDC A, @R0/@R1 case 0x38: case 0x39: @@ -1389,17 +1389,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0x3c: case 0x3d: case 0x3e: - case 0x3f: addc_a_r(mcs51_state, op&7); break; //ADDC A, R0 to R7 + case 0x3f: addc_a_r(mcs51_state, op&7); break; //ADDC A, R0 to R7 - case 0x40: jc(mcs51_state, op); break; //JC code addr - case 0x41: ajmp(mcs51_state, op); break; //AJMP code addr - case 0x42: RWM=1; orl_mem_a(mcs51_state, op); RWM=0; break; //ORL data addr, A - case 0x43: RWM=1; orl_mem_byte(mcs51_state, op); RWM=0; break; //ORL data addr, #data - case 0x44: orl_a_byte(mcs51_state, op); break; - case 0x45: orl_a_mem(mcs51_state, op); break; //ORL A, data addr + case 0x40: jc(mcs51_state, op); break; //JC code addr + case 0x41: ajmp(mcs51_state, op); break; //AJMP code addr + case 0x42: RWM=1; orl_mem_a(mcs51_state, op); RWM=0; break; //ORL data addr, A + case 0x43: RWM=1; orl_mem_byte(mcs51_state, op); RWM=0; break; //ORL data addr, #data + case 0x44: orl_a_byte(mcs51_state, op); break; + case 0x45: orl_a_mem(mcs51_state, op); break; //ORL A, data addr case 0x46: - case 0x47: orl_a_ir(mcs51_state, op&1); break; //ORL A, @RO/@R1 + case 0x47: orl_a_ir(mcs51_state, op&1); break; //ORL A, @RO/@R1 case 0x48: case 0x49: @@ -1408,17 +1408,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0x4c: case 0x4d: case 0x4e: - case 0x4f: orl_a_r(mcs51_state, op&7); break; //ORL A, RO to R7 + case 0x4f: orl_a_r(mcs51_state, op&7); break; //ORL A, RO to R7 - case 0x50: jnc(mcs51_state, op); break; //JNC code addr - case 0x51: acall(mcs51_state, op); break; //ACALL code addr - case 0x52: RWM=1; anl_mem_a(mcs51_state, op); RWM=0; break; //ANL data addr, A - case 0x53: RWM=1; anl_mem_byte(mcs51_state, op); RWM=0; break; //ANL data addr, #data - case 0x54: anl_a_byte(mcs51_state, op); break; //ANL A, #data - case 0x55: anl_a_mem(mcs51_state, op); break; //ANL A, data addr + case 0x50: jnc(mcs51_state, op); break; //JNC code addr + case 0x51: acall(mcs51_state, op); break; //ACALL code addr + case 0x52: RWM=1; anl_mem_a(mcs51_state, op); RWM=0; break; //ANL data addr, A + case 0x53: RWM=1; anl_mem_byte(mcs51_state, op); RWM=0; break; //ANL data addr, #data + case 0x54: anl_a_byte(mcs51_state, op); break; //ANL A, #data + case 0x55: anl_a_mem(mcs51_state, op); break; //ANL A, data addr case 0x56: - case 0x57: anl_a_ir(mcs51_state, op&1); break; //ANL A, @RO/@R1 + case 0x57: anl_a_ir(mcs51_state, op&1); break; //ANL A, @RO/@R1 case 0x58: case 0x59: @@ -1427,17 +1427,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0x5c: case 0x5d: case 0x5e: - case 0x5f: anl_a_r(mcs51_state, op&7); break; //ANL A, RO to R7 + case 0x5f: anl_a_r(mcs51_state, op&7); break; //ANL A, RO to R7 - case 0x60: jz(mcs51_state, op); break; //JZ code addr - case 0x61: ajmp(mcs51_state, op); break; //AJMP code addr - case 0x62: RWM=1; xrl_mem_a(mcs51_state, op); RWM=0; break; //XRL data addr, A - case 0x63: RWM=1; xrl_mem_byte(mcs51_state, op); RWM=0; break; //XRL data addr, #data - case 0x64: xrl_a_byte(mcs51_state, op); break; //XRL A, #data - case 0x65: xrl_a_mem(mcs51_state, op); break; //XRL A, data addr + case 0x60: jz(mcs51_state, op); break; //JZ code addr + case 0x61: ajmp(mcs51_state, op); break; //AJMP code addr + case 0x62: RWM=1; xrl_mem_a(mcs51_state, op); RWM=0; break; //XRL data addr, A + case 0x63: RWM=1; xrl_mem_byte(mcs51_state, op); RWM=0; break; //XRL data addr, #data + case 0x64: xrl_a_byte(mcs51_state, op); break; //XRL A, #data + case 0x65: xrl_a_mem(mcs51_state, op); break; //XRL A, data addr case 0x66: - case 0x67: xrl_a_ir(mcs51_state, op&1); break; //XRL A, @R0/@R1 + case 0x67: xrl_a_ir(mcs51_state, op&1); break; //XRL A, @R0/@R1 case 0x68: case 0x69: @@ -1446,17 +1446,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0x6c: case 0x6d: case 0x6e: - case 0x6f: xrl_a_r(mcs51_state, op&7); break; //XRL A, R0 to R7 + case 0x6f: xrl_a_r(mcs51_state, op&7); break; //XRL A, R0 to R7 - case 0x70: jnz(mcs51_state, op); break; //JNZ code addr - case 0x71: acall(mcs51_state, op); break; //ACALL code addr - case 0x72: orl_c_bitaddr(mcs51_state, op); break; //ORL C, bit addr - case 0x73: jmp_iadptr(mcs51_state, op); break; //JMP @A+DPTR - case 0x74: mov_a_byte(mcs51_state, op); break; //MOV A, #data - case 0x75: mov_mem_byte(mcs51_state, op); break; //MOV data addr, #data + case 0x70: jnz(mcs51_state, op); break; //JNZ code addr + case 0x71: acall(mcs51_state, op); break; //ACALL code addr + case 0x72: orl_c_bitaddr(mcs51_state, op); break; //ORL C, bit addr + case 0x73: jmp_iadptr(mcs51_state, op); break; //JMP @A+DPTR + case 0x74: mov_a_byte(mcs51_state, op); break; //MOV A, #data + case 0x75: mov_mem_byte(mcs51_state, op); break; //MOV data addr, #data case 0x76: - case 0x77: mov_ir_byte(mcs51_state, op&1); break; //MOV @R0/@R1, #data + case 0x77: mov_ir_byte(mcs51_state, op&1); break; //MOV @R0/@R1, #data case 0x78: case 0x79: @@ -1465,17 +1465,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0x7c: case 0x7d: case 0x7e: - case 0x7f: mov_r_byte(mcs51_state, op&7); break; //MOV R0 to R7, #data + case 0x7f: mov_r_byte(mcs51_state, op&7); break; //MOV R0 to R7, #data - case 0x80: sjmp(mcs51_state, op); break; //SJMP code addr - case 0x81: ajmp(mcs51_state, op); break; //AJMP code addr - case 0x82: anl_c_bitaddr(mcs51_state, op); break; //ANL C, bit addr - case 0x83: movc_a_iapc(mcs51_state, op); break; //MOVC A, @A + PC - case 0x84: div_ab(mcs51_state, op); break; //DIV AB - case 0x85: mov_mem_mem(mcs51_state, op); break; //MOV data addr, data addr + case 0x80: sjmp(mcs51_state, op); break; //SJMP code addr + case 0x81: ajmp(mcs51_state, op); break; //AJMP code addr + case 0x82: anl_c_bitaddr(mcs51_state, op); break; //ANL C, bit addr + case 0x83: movc_a_iapc(mcs51_state, op); break; //MOVC A, @A + PC + case 0x84: div_ab(mcs51_state, op); break; //DIV AB + case 0x85: mov_mem_mem(mcs51_state, op); break; //MOV data addr, data addr case 0x86: - case 0x87: mov_mem_ir(mcs51_state, op&1); break; //MOV data addr, @R0/@R1 + case 0x87: mov_mem_ir(mcs51_state, op&1); break; //MOV data addr, @R0/@R1 case 0x88: case 0x89: @@ -1484,17 +1484,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0x8c: case 0x8d: case 0x8e: - case 0x8f: mov_mem_r(mcs51_state, op&7); break; //MOV data addr,R0 to R7 + case 0x8f: mov_mem_r(mcs51_state, op&7); break; //MOV data addr,R0 to R7 - case 0x90: mov_dptr_byte(mcs51_state, op); break; //MOV DPTR, #data - case 0x91: acall(mcs51_state, op); break; //ACALL code addr - case 0x92: RWM = 1; mov_bitaddr_c(mcs51_state, op); RWM = 0; break; //MOV bit addr, C - case 0x93: movc_a_iadptr(mcs51_state, op); break; //MOVC A, @A + DPTR - case 0x94: subb_a_byte(mcs51_state, op); break; //SUBB A, #data - case 0x95: subb_a_mem(mcs51_state, op); break; //SUBB A, data addr + case 0x90: mov_dptr_byte(mcs51_state, op); break; //MOV DPTR, #data + case 0x91: acall(mcs51_state, op); break; //ACALL code addr + case 0x92: RWM = 1; mov_bitaddr_c(mcs51_state, op); RWM = 0; break; //MOV bit addr, C + case 0x93: movc_a_iadptr(mcs51_state, op); break; //MOVC A, @A + DPTR + case 0x94: subb_a_byte(mcs51_state, op); break; //SUBB A, #data + case 0x95: subb_a_mem(mcs51_state, op); break; //SUBB A, data addr case 0x96: - case 0x97: subb_a_ir(mcs51_state, op&1); break; //SUBB A, @R0/@R1 + case 0x97: subb_a_ir(mcs51_state, op&1); break; //SUBB A, @R0/@R1 case 0x98: case 0x99: @@ -1503,17 +1503,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0x9c: case 0x9d: case 0x9e: - case 0x9f: subb_a_r(mcs51_state, op&7); break; //SUBB A, R0 to R7 + case 0x9f: subb_a_r(mcs51_state, op&7); break; //SUBB A, R0 to R7 - case 0xa0: orl_c_nbitaddr(mcs51_state, op); break; //ORL C, /bit addr - case 0xa1: ajmp(mcs51_state, op); break; //AJMP code addr - case 0xa2: mov_c_bitaddr(mcs51_state, op); break; //MOV C, bit addr - case 0xa3: inc_dptr(mcs51_state, op); break; //INC DPTR - case 0xa4: mul_ab(mcs51_state, op); break; //MUL AB - case 0xa5: illegal(mcs51_state, op); break; //reserved + case 0xa0: orl_c_nbitaddr(mcs51_state, op); break; //ORL C, /bit addr + case 0xa1: ajmp(mcs51_state, op); break; //AJMP code addr + case 0xa2: mov_c_bitaddr(mcs51_state, op); break; //MOV C, bit addr + case 0xa3: inc_dptr(mcs51_state, op); break; //INC DPTR + case 0xa4: mul_ab(mcs51_state, op); break; //MUL AB + case 0xa5: illegal(mcs51_state, op); break; //reserved case 0xa6: - case 0xa7: mov_ir_mem(mcs51_state, op&1); break; //MOV @R0/@R1, data addr + case 0xa7: mov_ir_mem(mcs51_state, op&1); break; //MOV @R0/@R1, data addr case 0xa8: case 0xa9: @@ -1522,17 +1522,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0xac: case 0xad: case 0xae: - case 0xaf: mov_r_mem(mcs51_state, op&7); break; //MOV R0 to R7, data addr + case 0xaf: mov_r_mem(mcs51_state, op&7); break; //MOV R0 to R7, data addr - case 0xb0: anl_c_nbitaddr(mcs51_state, op); break; //ANL C,/bit addr - case 0xb1: acall(mcs51_state, op); break; //ACALL code addr - case 0xb2: RWM=1; cpl_bitaddr(mcs51_state, op); RWM=0; break; //CPL bit addr - case 0xb3: cpl_c(mcs51_state, op); break; //CPL C - case 0xb4: cjne_a_byte(mcs51_state, op); break; //CJNE A, #data, code addr - case 0xb5: cjne_a_mem(mcs51_state, op); break; //CJNE A, data addr, code addr + case 0xb0: anl_c_nbitaddr(mcs51_state, op); break; //ANL C,/bit addr + case 0xb1: acall(mcs51_state, op); break; //ACALL code addr + case 0xb2: RWM=1; cpl_bitaddr(mcs51_state, op); RWM=0; break; //CPL bit addr + case 0xb3: cpl_c(mcs51_state, op); break; //CPL C + case 0xb4: cjne_a_byte(mcs51_state, op); break; //CJNE A, #data, code addr + case 0xb5: cjne_a_mem(mcs51_state, op); break; //CJNE A, data addr, code addr case 0xb6: - case 0xb7: cjne_ir_byte(mcs51_state, op&1); break; //CJNE @R0/@R1, #data, code addr + case 0xb7: cjne_ir_byte(mcs51_state, op&1); break; //CJNE @R0/@R1, #data, code addr case 0xb8: case 0xb9: @@ -1541,17 +1541,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0xbc: case 0xbd: case 0xbe: - case 0xbf: cjne_r_byte(mcs51_state, op&7); break; //CJNE R0 to R7, #data, code addr + case 0xbf: cjne_r_byte(mcs51_state, op&7); break; //CJNE R0 to R7, #data, code addr - case 0xc0: push(mcs51_state, op); break; //PUSH data addr - case 0xc1: ajmp(mcs51_state, op); break; //AJMP code addr - case 0xc2: RWM=1; clr_bitaddr(mcs51_state, op); RWM=0; break; //CLR bit addr - case 0xc3: clr_c(mcs51_state, op); break; //CLR C - case 0xc4: swap_a(mcs51_state, op); break; //SWAP A - case 0xc5: xch_a_mem(mcs51_state, op); break; //XCH A, data addr + case 0xc0: push(mcs51_state, op); break; //PUSH data addr + case 0xc1: ajmp(mcs51_state, op); break; //AJMP code addr + case 0xc2: RWM=1; clr_bitaddr(mcs51_state, op); RWM=0; break; //CLR bit addr + case 0xc3: clr_c(mcs51_state, op); break; //CLR C + case 0xc4: swap_a(mcs51_state, op); break; //SWAP A + case 0xc5: xch_a_mem(mcs51_state, op); break; //XCH A, data addr case 0xc6: - case 0xc7: xch_a_ir(mcs51_state, op&1); break; //XCH A, @RO/@R1 + case 0xc7: xch_a_ir(mcs51_state, op&1); break; //XCH A, @RO/@R1 case 0xc8: case 0xc9: @@ -1560,17 +1560,17 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0xcc: case 0xcd: case 0xce: - case 0xcf: xch_a_r(mcs51_state, op&7); break; //XCH A, RO to R7 + case 0xcf: xch_a_r(mcs51_state, op&7); break; //XCH A, RO to R7 - case 0xd0: pop(mcs51_state, op); break; //POP data addr - case 0xd1: acall(mcs51_state, op); break; //ACALL code addr - case 0xd2: RWM=1; setb_bitaddr(mcs51_state, op); RWM=0; break; //SETB bit addr - case 0xd3: setb_c(mcs51_state, op); break; //SETB C - case 0xd4: da_a(mcs51_state, op); break; //DA A - case 0xd5: RWM=1; djnz_mem(mcs51_state, op); RWM=0; break; //DJNZ data addr, code addr + case 0xd0: pop(mcs51_state, op); break; //POP data addr + case 0xd1: acall(mcs51_state, op); break; //ACALL code addr + case 0xd2: RWM=1; setb_bitaddr(mcs51_state, op); RWM=0; break; //SETB bit addr + case 0xd3: setb_c(mcs51_state, op); break; //SETB C + case 0xd4: da_a(mcs51_state, op); break; //DA A + case 0xd5: RWM=1; djnz_mem(mcs51_state, op); RWM=0; break; //DJNZ data addr, code addr case 0xd6: - case 0xd7: xchd_a_ir(mcs51_state, op&1); break; //XCHD A, @R0/@R1 + case 0xd7: xchd_a_ir(mcs51_state, op&1); break; //XCHD A, @R0/@R1 case 0xd8: case 0xd9: @@ -1579,18 +1579,18 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0xdc: case 0xdd: case 0xde: - case 0xdf: djnz_r(mcs51_state, op&7); break; //DJNZ R0 to R7,code addr + case 0xdf: djnz_r(mcs51_state, op&7); break; //DJNZ R0 to R7,code addr - case 0xe0: movx_a_idptr(mcs51_state, op); break; //MOVX A,@DPTR - case 0xe1: ajmp(mcs51_state, op); break; //AJMP code addr + case 0xe0: movx_a_idptr(mcs51_state, op); break; //MOVX A,@DPTR + case 0xe1: ajmp(mcs51_state, op); break; //AJMP code addr case 0xe2: - case 0xe3: movx_a_ir(mcs51_state, op&1); break; //MOVX A, @R0/@R1 + case 0xe3: movx_a_ir(mcs51_state, op&1); break; //MOVX A, @R0/@R1 - case 0xe4: clr_a(mcs51_state, op); break; //CLR A - case 0xe5: mov_a_mem(mcs51_state, op); break; //MOV A, data addr + case 0xe4: clr_a(mcs51_state, op); break; //CLR A + case 0xe5: mov_a_mem(mcs51_state, op); break; //MOV A, data addr case 0xe6: - case 0xe7: mov_a_ir(mcs51_state, op&1); break; //MOV A,@RO/@R1 + case 0xe7: mov_a_ir(mcs51_state, op&1); break; //MOV A,@RO/@R1 case 0xe8: case 0xe9: @@ -1599,19 +1599,19 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0xec: case 0xed: case 0xee: - case 0xef: mov_a_r(mcs51_state, op&7); break; //MOV A,R0 to R7 + case 0xef: mov_a_r(mcs51_state, op&7); break; //MOV A,R0 to R7 - case 0xf0: movx_idptr_a(mcs51_state, op); break; //MOVX @DPTR,A - case 0xf1: acall(mcs51_state, op); break; //ACALL code addr + case 0xf0: movx_idptr_a(mcs51_state, op); break; //MOVX @DPTR,A + case 0xf1: acall(mcs51_state, op); break; //ACALL code addr case 0xf2: - case 0xf3: movx_ir_a(mcs51_state, op&1); break; //MOVX @R0/@R1,A + case 0xf3: movx_ir_a(mcs51_state, op&1); break; //MOVX @R0/@R1,A - case 0xf4: cpl_a(mcs51_state, op); break; //CPL A - case 0xf5: mov_mem_a(mcs51_state, op); break; //MOV data addr, A + case 0xf4: cpl_a(mcs51_state, op); break; //CPL A + case 0xf5: mov_mem_a(mcs51_state, op); break; //MOV data addr, A case 0xf6: - case 0xf7: mov_ir_a(mcs51_state, op&1); break; //MOV @R0/@R1, A + case 0xf7: mov_ir_a(mcs51_state, op&1); break; //MOV @R0/@R1, A case 0xf8: case 0xf9: @@ -1620,7 +1620,7 @@ static void execute_op(mcs51_state_t *mcs51_state, UINT8 op) case 0xfc: case 0xfd: case 0xfe: - case 0xff: mov_r_a(mcs51_state, op&7); break; //MOV R0 to R7, A + case 0xff: mov_r_a(mcs51_state, op&7); break; //MOV R0 to R7, A default: illegal(mcs51_state, op); } @@ -1685,7 +1685,7 @@ static void check_irqs(mcs51_state_t *mcs51_state) if (mcs51_state->features & FEATURE_DS5002FP) { ints |= ((GET_PFW)<<5); - mcs51_state->irq_prio[6] = 3; /* force highest priority */ + mcs51_state->irq_prio[6] = 3; /* force highest priority */ /* mask out interrupts not enabled */ ints &= ((int_mask & 0x1f) | ((GET_EPFW)<<5)); } @@ -1695,7 +1695,7 @@ static void check_irqs(mcs51_state_t *mcs51_state) ints &= int_mask; } - if (!ints) return; + if (!ints) return; /* CLear IDL - got enabled interrupt */ if (mcs51_state->features & FEATURE_CMOS) @@ -1722,8 +1722,8 @@ static void check_irqs(mcs51_state_t *mcs51_state) } /* Skip the interrupt request if currently processing interrupt - * and the new request does not have a higher priority - */ + * and the new request does not have a higher priority + */ LOG(("Request: %d\n", priority_request)); if (mcs51_state->irq_active && (priority_request <= mcs51_state->cur_irq_prio)) @@ -1787,9 +1787,9 @@ static void check_irqs(mcs51_state_t *mcs51_state) break; /* DS5002FP specific */ /* case V_PFI: - * no flags are cleared, PFW is reset by software - * This has the same vector as V_TF2. - */ + * no flags are cleared, PFW is reset by software + * This has the same vector as V_TF2. + */ } } @@ -1809,15 +1809,15 @@ INLINE void burn_cycles(mcs51_state_t *mcs51_state, int cycles) static void mcs51_set_irq_line(mcs51_state_t *mcs51_state, int irqline, int state) { /* From the manual: - * - * <cite>In operation all the interrupt flags are latched into the - * interrupt control system during State 5 of every machine cycle. - * The samples are polled during the following machine cycle.</cite> - * - * ==> Since we do not emulate sub-states, this assumes that the signal is present - * for at least one cycle (12 states) - * - */ + * + * <cite>In operation all the interrupt flags are latched into the + * interrupt control system during State 5 of every machine cycle. + * The samples are polled during the following machine cycle.</cite> + * + * ==> Since we do not emulate sub-states, this assumes that the signal is present + * for at least one cycle (12 states) + * + */ UINT32 new_state = (mcs51_state->last_line_state & ~(1 << irqline)) | ((state != CLEAR_LINE) << irqline); /* detect 0->1 transistions */ UINT32 tr_state = (~mcs51_state->last_line_state) & new_state; @@ -1834,7 +1834,7 @@ static void mcs51_set_irq_line(mcs51_state_t *mcs51_state, int irqline, int stat SET_IE0(1); } else - SET_IE0(1); //Nope, just set it.. + SET_IE0(1); //Nope, just set it.. } else { @@ -1855,7 +1855,7 @@ static void mcs51_set_irq_line(mcs51_state_t *mcs51_state, int irqline, int stat SET_IE1(1); } else - SET_IE1(1); //Nope, just set it.. + SET_IE1(1); //Nope, just set it.. } else { @@ -1996,14 +1996,14 @@ static void mcs51_sfr_write(mcs51_state_t *mcs51_state, size_t offset, UINT8 dat switch (offset) { - case ADDR_P0: OUT(MCS51_PORT_P0,data); break; - case ADDR_P1: OUT(MCS51_PORT_P1,data); break; - case ADDR_P2: OUT(MCS51_PORT_P2,data); break; - case ADDR_P3: OUT(MCS51_PORT_P3,data); break; - case ADDR_SBUF: serial_transmit(mcs51_state, data); break; - case ADDR_PSW: SET_PARITY(); break; - case ADDR_ACC: SET_PARITY(); break; - case ADDR_IP: update_irq_prio(mcs51_state, data, 0); break; + case ADDR_P0: OUT(MCS51_PORT_P0,data); break; + case ADDR_P1: OUT(MCS51_PORT_P1,data); break; + case ADDR_P2: OUT(MCS51_PORT_P2,data); break; + case ADDR_P3: OUT(MCS51_PORT_P3,data); break; + case ADDR_SBUF: serial_transmit(mcs51_state, data); break; + case ADDR_PSW: SET_PARITY(); break; + case ADDR_ACC: SET_PARITY(); break; + case ADDR_IP: update_irq_prio(mcs51_state, data, 0); break; /* R_SBUF = data; //This register is used only for "Receiving data coming in!" */ case ADDR_B: @@ -2036,10 +2036,10 @@ static UINT8 mcs51_sfr_read(mcs51_state_t *mcs51_state, size_t offset) { /* Read/Write/Modify operations read the port latch ! */ /* Move to memory map */ - case ADDR_P0: return RWM ? P0 : P0 & IN(MCS51_PORT_P0); - case ADDR_P1: return RWM ? P1 : P1 & IN(MCS51_PORT_P1); - case ADDR_P2: return RWM ? P2 : P2 & IN(MCS51_PORT_P2); - case ADDR_P3: return RWM ? P3 : P3 & IN(MCS51_PORT_P3); + case ADDR_P0: return RWM ? P0 : P0 & IN(MCS51_PORT_P0); + case ADDR_P1: return RWM ? P1 : P1 & IN(MCS51_PORT_P1); + case ADDR_P2: return RWM ? P2 : P2 & IN(MCS51_PORT_P2); + case ADDR_P3: return RWM ? P3 : P3 & IN(MCS51_PORT_P3); case ADDR_PSW: case ADDR_ACC: @@ -2081,8 +2081,8 @@ static CPU_INIT( mcs51 ) mcs51_state->io = &device->space(AS_IO); mcs51_state->features = FEATURE_NONE; - mcs51_state->ram_mask = 0x7F; /* 128 bytes of ram */ - mcs51_state->num_interrupts = 5; /* 5 interrupts */ + mcs51_state->ram_mask = 0x7F; /* 128 bytes of ram */ + mcs51_state->num_interrupts = 5; /* 5 interrupts */ mcs51_state->sfr_read = mcs51_sfr_read; mcs51_state->sfr_write = mcs51_sfr_write; @@ -2247,8 +2247,8 @@ static CPU_INIT( i8052 ) mcs51_state_t *mcs51_state = get_safe_token(device); CPU_INIT_CALL(mcs51); - mcs51_state->ram_mask = 0xFF; /* 256 bytes of ram */ - mcs51_state->num_interrupts = 6; /* 6 interrupts */ + mcs51_state->ram_mask = 0xFF; /* 256 bytes of ram */ + mcs51_state->num_interrupts = 6; /* 6 interrupts */ mcs51_state->features |= FEATURE_I8052; mcs51_state->sfr_read = i8052_sfr_read; @@ -2310,7 +2310,7 @@ static CPU_INIT( i80c31 ) mcs51_state_t *mcs51_state = get_safe_token(device); CPU_INIT_CALL(i8052); - mcs51_state->ram_mask = 0x7F; /* 128 bytes of ram */ + mcs51_state->ram_mask = 0x7F; /* 128 bytes of ram */ } /**************************************************************************** @@ -2318,8 +2318,8 @@ static CPU_INIT( i80c31 ) ****************************************************************************/ -#define DS5_LOGW(a, d) LOG(("ds5002fp '%s': write to " # a " register at 0x%04x, data=%x\n", mcs51_state->device->tag(), PC, d)) -#define DS5_LOGR(a, d) LOG(("ds5002fp '%s': read from " # a " register at 0x%04x\n", mcs51_state->device->tag(), PC)) +#define DS5_LOGW(a, d) LOG(("ds5002fp '%s': write to " # a " register at 0x%04x, data=%x\n", mcs51_state->device->tag(), PC, d)) +#define DS5_LOGR(a, d) LOG(("ds5002fp '%s': read from " # a " register at 0x%04x\n", mcs51_state->device->tag(), PC)) INLINE UINT8 ds5002fp_protected(mcs51_state_t *mcs51_state, size_t offset, UINT8 data, UINT8 ta_mask, UINT8 mask) { @@ -2348,15 +2348,15 @@ static void ds5002fp_sfr_write(mcs51_state_t *mcs51_state, size_t offset, UINT8 LOG(("ds5002fp '%s': TA window initiated at 0x%04x\n", mcs51_state->device->tag(), PC)); } break; - case ADDR_MCON: data = ds5002fp_protected(mcs51_state, ADDR_MCON, data, 0x0f, 0xf7); DS5_LOGW(MCON, data); break; - case ADDR_RPCTL: data = ds5002fp_protected(mcs51_state, ADDR_RPCTL, data, 0xef, 0xfe); DS5_LOGW(RPCTL, data); break; - case ADDR_CRCR: data = ds5002fp_protected(mcs51_state, ADDR_CRCR, data, 0xff, 0x0f); DS5_LOGW(CRCR, data); break; - case ADDR_PCON: data = ds5002fp_protected(mcs51_state, ADDR_PCON, data, 0xb9, 0xff); break; - case ADDR_IP: data = ds5002fp_protected(mcs51_state, ADDR_IP, data, 0x7f, 0xff); break; - case ADDR_CRCL: DS5_LOGW(CRCL, data); break; - case ADDR_CRCH: DS5_LOGW(CRCH, data); break; - case ADDR_RNR: DS5_LOGW(RNR, data); break; - case ADDR_RPS: DS5_LOGW(RPS, data); break; + case ADDR_MCON: data = ds5002fp_protected(mcs51_state, ADDR_MCON, data, 0x0f, 0xf7); DS5_LOGW(MCON, data); break; + case ADDR_RPCTL: data = ds5002fp_protected(mcs51_state, ADDR_RPCTL, data, 0xef, 0xfe); DS5_LOGW(RPCTL, data); break; + case ADDR_CRCR: data = ds5002fp_protected(mcs51_state, ADDR_CRCR, data, 0xff, 0x0f); DS5_LOGW(CRCR, data); break; + case ADDR_PCON: data = ds5002fp_protected(mcs51_state, ADDR_PCON, data, 0xb9, 0xff); break; + case ADDR_IP: data = ds5002fp_protected(mcs51_state, ADDR_IP, data, 0x7f, 0xff); break; + case ADDR_CRCL: DS5_LOGW(CRCL, data); break; + case ADDR_CRCH: DS5_LOGW(CRCH, data); break; + case ADDR_RNR: DS5_LOGW(RNR, data); break; + case ADDR_RPS: DS5_LOGW(RPS, data); break; default: mcs51_sfr_write(mcs51_state, offset, data); return; @@ -2368,16 +2368,16 @@ static UINT8 ds5002fp_sfr_read(mcs51_state_t *mcs51_state, size_t offset) { switch (offset) { - case ADDR_CRCR: DS5_LOGR(CRCR, data); break; - case ADDR_CRCL: DS5_LOGR(CRCL, data); break; - case ADDR_CRCH: DS5_LOGR(CRCH, data); break; - case ADDR_MCON: DS5_LOGR(MCON, data); break; - case ADDR_TA: DS5_LOGR(TA, data); break; - case ADDR_RNR: DS5_LOGR(RNR, data); break; - case ADDR_RPCTL: DS5_LOGR(RPCTL, data); break; - case ADDR_RPS: DS5_LOGR(RPS, data); break; + case ADDR_CRCR: DS5_LOGR(CRCR, data); break; + case ADDR_CRCL: DS5_LOGR(CRCL, data); break; + case ADDR_CRCH: DS5_LOGR(CRCH, data); break; + case ADDR_MCON: DS5_LOGR(MCON, data); break; + case ADDR_TA: DS5_LOGR(TA, data); break; + case ADDR_RNR: DS5_LOGR(RNR, data); break; + case ADDR_RPCTL: DS5_LOGR(RPCTL, data); break; + case ADDR_RPS: DS5_LOGR(RPS, data); break; case ADDR_PCON: - SET_PFW(0); /* reset PFW flag */ + SET_PFW(0); /* reset PFW flag */ return mcs51_sfr_read(mcs51_state, offset); default: return mcs51_sfr_read(mcs51_state, offset); @@ -2439,32 +2439,32 @@ static CPU_SET_INFO( mcs51 ) switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_PC: PC = info->i; break; - case CPUINFO_INT_SP: SP = info->i; break; - - case CPUINFO_INT_INPUT_STATE + MCS51_INT0_LINE: mcs51_set_irq_line(mcs51_state, MCS51_INT0_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + MCS51_INT1_LINE: mcs51_set_irq_line(mcs51_state, MCS51_INT1_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + MCS51_T0_LINE: mcs51_set_irq_line(mcs51_state, MCS51_T0_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + MCS51_T1_LINE: mcs51_set_irq_line(mcs51_state, MCS51_T1_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + MCS51_RX_LINE: mcs51_set_irq_line(mcs51_state, MCS51_RX_LINE, info->i); break; - - case CPUINFO_INT_REGISTER + MCS51_PC: PC = info->i; break; - case CPUINFO_INT_REGISTER + MCS51_SP: SP = info->i; break; - case CPUINFO_INT_REGISTER + MCS51_PSW: SET_PSW(info->i); break; - case CPUINFO_INT_REGISTER + MCS51_ACC: SET_ACC(info->i); break; - case CPUINFO_INT_REGISTER + MCS51_B: B = info->i; break; - case CPUINFO_INT_REGISTER + MCS51_DPH: DPH = info->i; break; - case CPUINFO_INT_REGISTER + MCS51_DPL: DPL = info->i; break; - case CPUINFO_INT_REGISTER + MCS51_IE: IE = info->i; break; - case CPUINFO_INT_REGISTER + MCS51_R0: SET_REG(0, info->i); break; - case CPUINFO_INT_REGISTER + MCS51_R1: SET_REG(1, info->i); break; - case CPUINFO_INT_REGISTER + MCS51_R2: SET_REG(2, info->i); break; - case CPUINFO_INT_REGISTER + MCS51_R3: SET_REG(3, info->i); break; - case CPUINFO_INT_REGISTER + MCS51_R4: SET_REG(4, info->i); break; - case CPUINFO_INT_REGISTER + MCS51_R5: SET_REG(5, info->i); break; - case CPUINFO_INT_REGISTER + MCS51_R6: SET_REG(6, info->i); break; - case CPUINFO_INT_REGISTER + MCS51_R7: SET_REG(7, info->i); break; - case CPUINFO_INT_REGISTER + MCS51_RB: SET_RS(info->i); break; + case CPUINFO_INT_PC: PC = info->i; break; + case CPUINFO_INT_SP: SP = info->i; break; + + case CPUINFO_INT_INPUT_STATE + MCS51_INT0_LINE: mcs51_set_irq_line(mcs51_state, MCS51_INT0_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MCS51_INT1_LINE: mcs51_set_irq_line(mcs51_state, MCS51_INT1_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MCS51_T0_LINE: mcs51_set_irq_line(mcs51_state, MCS51_T0_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MCS51_T1_LINE: mcs51_set_irq_line(mcs51_state, MCS51_T1_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MCS51_RX_LINE: mcs51_set_irq_line(mcs51_state, MCS51_RX_LINE, info->i); break; + + case CPUINFO_INT_REGISTER + MCS51_PC: PC = info->i; break; + case CPUINFO_INT_REGISTER + MCS51_SP: SP = info->i; break; + case CPUINFO_INT_REGISTER + MCS51_PSW: SET_PSW(info->i); break; + case CPUINFO_INT_REGISTER + MCS51_ACC: SET_ACC(info->i); break; + case CPUINFO_INT_REGISTER + MCS51_B: B = info->i; break; + case CPUINFO_INT_REGISTER + MCS51_DPH: DPH = info->i; break; + case CPUINFO_INT_REGISTER + MCS51_DPL: DPL = info->i; break; + case CPUINFO_INT_REGISTER + MCS51_IE: IE = info->i; break; + case CPUINFO_INT_REGISTER + MCS51_R0: SET_REG(0, info->i); break; + case CPUINFO_INT_REGISTER + MCS51_R1: SET_REG(1, info->i); break; + case CPUINFO_INT_REGISTER + MCS51_R2: SET_REG(2, info->i); break; + case CPUINFO_INT_REGISTER + MCS51_R3: SET_REG(3, info->i); break; + case CPUINFO_INT_REGISTER + MCS51_R4: SET_REG(4, info->i); break; + case CPUINFO_INT_REGISTER + MCS51_R5: SET_REG(5, info->i); break; + case CPUINFO_INT_REGISTER + MCS51_R6: SET_REG(6, info->i); break; + case CPUINFO_INT_REGISTER + MCS51_R7: SET_REG(7, info->i); break; + case CPUINFO_INT_REGISTER + MCS51_RB: SET_RS(info->i); break; } } @@ -2481,68 +2481,68 @@ static CPU_GET_INFO( mcs51 ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mcs51_state_t); break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 12; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 20; /* rough guess */ break; - case CPUINFO_INT_INPUT_LINES: info->i = 3; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 9; /* due to sfr mapping */ break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 18; /* 128k for ds5002fp */ break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = PPC; break; - case CPUINFO_INT_PC: info->i = PC; break; - case CPUINFO_INT_SP: info->i = SP; break; - - case CPUINFO_INT_REGISTER + MCS51_PC: info->i = PC; break; - case CPUINFO_INT_REGISTER + MCS51_SP: info->i = SP; break; - case CPUINFO_INT_REGISTER + MCS51_PSW: info->i = PSW; break; - case CPUINFO_INT_REGISTER + MCS51_ACC: info->i = ACC; break; - case CPUINFO_INT_REGISTER + MCS51_B: info->i = B; break; - case CPUINFO_INT_REGISTER + MCS51_DPH: info->i = DPH; break; - case CPUINFO_INT_REGISTER + MCS51_DPL: info->i = DPL; break; - case CPUINFO_INT_REGISTER + MCS51_IE: info->i = IE; break; - case CPUINFO_INT_REGISTER + MCS51_R0: info->i = R_REG(0); break; - case CPUINFO_INT_REGISTER + MCS51_R1: info->i = R_REG(1); break; - case CPUINFO_INT_REGISTER + MCS51_R2: info->i = R_REG(2); break; - case CPUINFO_INT_REGISTER + MCS51_R3: info->i = R_REG(3); break; - case CPUINFO_INT_REGISTER + MCS51_R4: info->i = R_REG(4); break; - case CPUINFO_INT_REGISTER + MCS51_R5: info->i = R_REG(5); break; - case CPUINFO_INT_REGISTER + MCS51_R6: info->i = R_REG(6); break; - case CPUINFO_INT_REGISTER + MCS51_R7: info->i = R_REG(7); break; - case CPUINFO_INT_REGISTER + MCS51_RB: info->i = R_REG(8); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mcs51_state_t); break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 12; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 20; /* rough guess */ break; + case CPUINFO_INT_INPUT_LINES: info->i = 3; break; + + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 9; /* due to sfr mapping */ break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 18; /* 128k for ds5002fp */ break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; + + case CPUINFO_INT_PREVIOUSPC: info->i = PPC; break; + case CPUINFO_INT_PC: info->i = PC; break; + case CPUINFO_INT_SP: info->i = SP; break; + + case CPUINFO_INT_REGISTER + MCS51_PC: info->i = PC; break; + case CPUINFO_INT_REGISTER + MCS51_SP: info->i = SP; break; + case CPUINFO_INT_REGISTER + MCS51_PSW: info->i = PSW; break; + case CPUINFO_INT_REGISTER + MCS51_ACC: info->i = ACC; break; + case CPUINFO_INT_REGISTER + MCS51_B: info->i = B; break; + case CPUINFO_INT_REGISTER + MCS51_DPH: info->i = DPH; break; + case CPUINFO_INT_REGISTER + MCS51_DPL: info->i = DPL; break; + case CPUINFO_INT_REGISTER + MCS51_IE: info->i = IE; break; + case CPUINFO_INT_REGISTER + MCS51_R0: info->i = R_REG(0); break; + case CPUINFO_INT_REGISTER + MCS51_R1: info->i = R_REG(1); break; + case CPUINFO_INT_REGISTER + MCS51_R2: info->i = R_REG(2); break; + case CPUINFO_INT_REGISTER + MCS51_R3: info->i = R_REG(3); break; + case CPUINFO_INT_REGISTER + MCS51_R4: info->i = R_REG(4); break; + case CPUINFO_INT_REGISTER + MCS51_R5: info->i = R_REG(5); break; + case CPUINFO_INT_REGISTER + MCS51_R6: info->i = R_REG(6); break; + case CPUINFO_INT_REGISTER + MCS51_R7: info->i = R_REG(7); break; + case CPUINFO_INT_REGISTER + MCS51_RB: info->i = R_REG(8); break; /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mcs51); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(mcs51); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(mcs51); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(mcs51); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(mcs51); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8051); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mcs51_state->icount; break; - - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = NULL; break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = NULL; break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_IO: info->internal_map8 = NULL; break; - - case CPUINFO_STR_NAME: strcpy(info->s, "I8051"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "MCS-51"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Steve Ellenoff"); break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mcs51); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(mcs51); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(mcs51); break; + case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(mcs51); break; + case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(mcs51); break; + case CPUINFO_FCT_BURN: info->burn = NULL; break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8051); break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mcs51_state->icount; break; + + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = NULL; break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = NULL; break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_IO: info->internal_map8 = NULL; break; + + case CPUINFO_STR_NAME: strcpy(info->s, "I8051"); break; + case CPUINFO_STR_FAMILY: strcpy(info->s, "MCS-51"); break; + case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; + case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Steve Ellenoff"); break; case CPUINFO_STR_FLAGS: sprintf(info->s, "%c%c%c%c%c%c%c%c", @@ -2556,23 +2556,23 @@ static CPU_GET_INFO( mcs51 ) PSW & 0x01 ? 'P':'.'); break; - case CPUINFO_STR_REGISTER + MCS51_PC: sprintf(info->s, "PC:%04X", mcs51_state->pc); break; - case CPUINFO_STR_REGISTER + MCS51_SP: sprintf(info->s, "SP:%02X", SP); break; - case CPUINFO_STR_REGISTER + MCS51_PSW: sprintf(info->s, "PSW:%02X", PSW); break; - case CPUINFO_STR_REGISTER + MCS51_ACC: sprintf(info->s, "A:%02X", ACC); break; - case CPUINFO_STR_REGISTER + MCS51_B: sprintf(info->s, "B:%02X", B); break; - case CPUINFO_STR_REGISTER + MCS51_DPH: sprintf(info->s, "DPH:%02X", DPH); break; - case CPUINFO_STR_REGISTER + MCS51_DPL: sprintf(info->s, "DPL:%02X", DPL); break; - case CPUINFO_STR_REGISTER + MCS51_IE: sprintf(info->s, "IE:%02X", IE); break; - case CPUINFO_STR_REGISTER + MCS51_R0: sprintf(info->s, "R0:%02X", R_REG(0)); break; - case CPUINFO_STR_REGISTER + MCS51_R1: sprintf(info->s, "R1:%02X", R_REG(1)); break; - case CPUINFO_STR_REGISTER + MCS51_R2: sprintf(info->s, "R2:%02X", R_REG(2)); break; - case CPUINFO_STR_REGISTER + MCS51_R3: sprintf(info->s, "R3:%02X", R_REG(3)); break; - case CPUINFO_STR_REGISTER + MCS51_R4: sprintf(info->s, "R4:%02X", R_REG(4)); break; - case CPUINFO_STR_REGISTER + MCS51_R5: sprintf(info->s, "R5:%02X", R_REG(5)); break; - case CPUINFO_STR_REGISTER + MCS51_R6: sprintf(info->s, "R6:%02X", R_REG(6)); break; - case CPUINFO_STR_REGISTER + MCS51_R7: sprintf(info->s, "R7:%02X", R_REG(7)); break; - case CPUINFO_STR_REGISTER + MCS51_RB: sprintf(info->s, "RB:%02X", ((PSW & 0x18)>>3)); break; + case CPUINFO_STR_REGISTER + MCS51_PC: sprintf(info->s, "PC:%04X", mcs51_state->pc); break; + case CPUINFO_STR_REGISTER + MCS51_SP: sprintf(info->s, "SP:%02X", SP); break; + case CPUINFO_STR_REGISTER + MCS51_PSW: sprintf(info->s, "PSW:%02X", PSW); break; + case CPUINFO_STR_REGISTER + MCS51_ACC: sprintf(info->s, "A:%02X", ACC); break; + case CPUINFO_STR_REGISTER + MCS51_B: sprintf(info->s, "B:%02X", B); break; + case CPUINFO_STR_REGISTER + MCS51_DPH: sprintf(info->s, "DPH:%02X", DPH); break; + case CPUINFO_STR_REGISTER + MCS51_DPL: sprintf(info->s, "DPL:%02X", DPL); break; + case CPUINFO_STR_REGISTER + MCS51_IE: sprintf(info->s, "IE:%02X", IE); break; + case CPUINFO_STR_REGISTER + MCS51_R0: sprintf(info->s, "R0:%02X", R_REG(0)); break; + case CPUINFO_STR_REGISTER + MCS51_R1: sprintf(info->s, "R1:%02X", R_REG(1)); break; + case CPUINFO_STR_REGISTER + MCS51_R2: sprintf(info->s, "R2:%02X", R_REG(2)); break; + case CPUINFO_STR_REGISTER + MCS51_R3: sprintf(info->s, "R3:%02X", R_REG(3)); break; + case CPUINFO_STR_REGISTER + MCS51_R4: sprintf(info->s, "R4:%02X", R_REG(4)); break; + case CPUINFO_STR_REGISTER + MCS51_R5: sprintf(info->s, "R5:%02X", R_REG(5)); break; + case CPUINFO_STR_REGISTER + MCS51_R6: sprintf(info->s, "R6:%02X", R_REG(6)); break; + case CPUINFO_STR_REGISTER + MCS51_R7: sprintf(info->s, "R7:%02X", R_REG(7)); break; + case CPUINFO_STR_REGISTER + MCS51_RB: sprintf(info->s, "RB:%02X", ((PSW & 0x18)>>3)); break; } } @@ -2584,9 +2584,9 @@ CPU_GET_INFO( i8031 ) { switch (state) { - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_7bit); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I8031"); break; - default: CPU_GET_INFO_CALL(mcs51); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_7bit); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I8031"); break; + default: CPU_GET_INFO_CALL(mcs51); break; } /* --- the following bits of info are returned as NULL-terminated strings --- */ } @@ -2595,10 +2595,10 @@ CPU_GET_INFO( i8051 ) { switch (state) { - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(program_12bit); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_7bit); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I8051"); break; - default: CPU_GET_INFO_CALL(mcs51); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(program_12bit); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_7bit); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I8051"); break; + default: CPU_GET_INFO_CALL(mcs51); break; } /* --- the following bits of info are returned as NULL-terminated strings --- */ } @@ -2607,11 +2607,11 @@ CPU_GET_INFO( i8032 ) { switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i8052); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_8bit); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8052); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I8032"); break; - default: CPU_GET_INFO_CALL(mcs51); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i8052); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_8bit); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8052); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I8032"); break; + default: CPU_GET_INFO_CALL(mcs51); break; } } @@ -2619,12 +2619,12 @@ CPU_GET_INFO( i8052 ) { switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i8052); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(program_13bit); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_8bit); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8052); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I8052"); break; - default: CPU_GET_INFO_CALL(mcs51); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i8052); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(program_13bit); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_8bit); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8052); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I8052"); break; + default: CPU_GET_INFO_CALL(mcs51); break; } } @@ -2632,10 +2632,10 @@ CPU_GET_INFO( i8751 ) { switch (state) { - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(program_12bit); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_7bit); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I8751"); break; - default: CPU_GET_INFO_CALL(mcs51); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(program_12bit); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_7bit); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I8751"); break; + default: CPU_GET_INFO_CALL(mcs51); break; } } @@ -2643,12 +2643,12 @@ CPU_GET_INFO( i8752 ) { switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i8052); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(program_13bit); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_8bit); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8052); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I8752"); break; - default: CPU_GET_INFO_CALL(mcs51); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i8052); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(program_13bit); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_8bit); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8052); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I8752"); break; + default: CPU_GET_INFO_CALL(mcs51); break; } } @@ -2659,15 +2659,15 @@ CPU_GET_INFO( i8752 ) CPU_GET_INFO( i80c31 ) { /* according to PHILIPS datasheet this is a stripped down version - * of i80c52 with 128 bytes internal ram */ + * of i80c52 with 128 bytes internal ram */ switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c31); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = NULL; break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_7bit); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c51); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I80C31"); break; - default: CPU_GET_INFO_CALL(i8031); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c31); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = NULL; break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = ADDRESS_MAP_NAME(data_7bit); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c51); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I80C31"); break; + default: CPU_GET_INFO_CALL(i8031); break; } } @@ -2675,10 +2675,10 @@ CPU_GET_INFO( i80c51 ) { switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c51); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c51); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I80C51"); break; - default: CPU_GET_INFO_CALL(i8051); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c51); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c51); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I80C51"); break; + default: CPU_GET_INFO_CALL(i8051); break; } } @@ -2686,10 +2686,10 @@ CPU_GET_INFO( i80c32 ) { switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c52); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c52); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I80C32"); break; - default: CPU_GET_INFO_CALL(i8032); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c52); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c52); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I80C32"); break; + default: CPU_GET_INFO_CALL(i8032); break; } } @@ -2697,10 +2697,10 @@ CPU_GET_INFO( i80c52 ) { switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c52); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I80C52"); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c52); break; - default: CPU_GET_INFO_CALL(i8052); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c52); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I80C52"); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c52); break; + default: CPU_GET_INFO_CALL(i8052); break; } } @@ -2708,10 +2708,10 @@ CPU_GET_INFO( i87c51 ) { switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c51); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I87C51"); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c51); break; - default: CPU_GET_INFO_CALL(i8751); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c51); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I87C51"); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c51); break; + default: CPU_GET_INFO_CALL(i8751); break; } } @@ -2719,10 +2719,10 @@ CPU_GET_INFO( i87c52 ) { switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c52); break; - case CPUINFO_STR_NAME: strcpy(info->s, "I87C52"); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c52); break; - default: CPU_GET_INFO_CALL(i8752); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c52); break; + case CPUINFO_STR_NAME: strcpy(info->s, "I87C52"); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c52); break; + default: CPU_GET_INFO_CALL(i8752); break; } } @@ -2734,10 +2734,10 @@ CPU_GET_INFO( at89c4051 ) { switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c51); break; - case CPUINFO_STR_NAME: strcpy(info->s, "AT89C4051"); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c51); break; - default: CPU_GET_INFO_CALL(i8051); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i80c51); break; + case CPUINFO_STR_NAME: strcpy(info->s, "AT89C4051"); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80c51); break; + default: CPU_GET_INFO_CALL(i8051); break; } } @@ -2745,14 +2745,14 @@ CPU_GET_INFO( ds5002fp ) { switch (state) { - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ds5002fp); break; - case CPUINFO_STR_NAME: strcpy(info->s, "DS5002FP"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Dallas"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Manuel Abadia"); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(ds5002fp); break; - default: CPU_GET_INFO_CALL(i8051); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ds5002fp); break; + case CPUINFO_STR_NAME: strcpy(info->s, "DS5002FP"); break; + case CPUINFO_STR_FAMILY: strcpy(info->s, "Dallas"); break; + case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; + case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Manuel Abadia"); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(ds5002fp); break; + default: CPU_GET_INFO_CALL(i8051); break; } } |