diff options
Diffstat (limited to 'src/emu/cpu/mc68hc11/mc68hc11.c')
-rw-r--r-- | src/emu/cpu/mc68hc11/mc68hc11.c | 260 |
1 files changed, 130 insertions, 130 deletions
diff --git a/src/emu/cpu/mc68hc11/mc68hc11.c b/src/emu/cpu/mc68hc11/mc68hc11.c index 3c9882972f4..0a06445c1dd 100644 --- a/src/emu/cpu/mc68hc11/mc68hc11.c +++ b/src/emu/cpu/mc68hc11/mc68hc11.c @@ -25,14 +25,14 @@ enum HC11_IY }; -#define CC_S 0x80 -#define CC_X 0x40 -#define CC_H 0x20 -#define CC_I 0x10 -#define CC_N 0x08 -#define CC_Z 0x04 -#define CC_V 0x02 -#define CC_C 0x01 +#define CC_S 0x80 +#define CC_X 0x40 +#define CC_H 0x20 +#define CC_I 0x10 +#define CC_N 0x08 +#define CC_Z 0x04 +#define CC_V 0x02 +#define CC_C 0x01 static const int div_tab[4] = { 1, 4, 8, 16 }; @@ -95,7 +95,7 @@ INLINE hc11_state *get_safe_token(device_t *device) return (hc11_state *)downcast<legacy_cpu_device *>(device)->token(); } -#define HC11OP(XX) hc11_##XX +#define HC11OP(XX) hc11_##XX /*****************************************************************************/ /* Internal registers */ @@ -106,37 +106,37 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) switch(reg) { - case 0x00: /* PORTA */ + case 0x00: /* PORTA */ return cpustate->io->read_byte(MC68HC11_IO_PORTA); - case 0x01: /* DDRA */ + case 0x01: /* DDRA */ return 0; - case 0x02: /* PIOC */ + case 0x02: /* PIOC */ return 0; - case 0x03: /* PORTC */ + case 0x03: /* PORTC */ return cpustate->io->read_byte(MC68HC11_IO_PORTC); - case 0x04: /* PORTB */ + case 0x04: /* PORTB */ return cpustate->io->read_byte(MC68HC11_IO_PORTB); - case 0x08: /* PORTD */ + case 0x08: /* PORTD */ return cpustate->io->read_byte(MC68HC11_IO_PORTD); - case 0x09: /* DDRD */ + case 0x09: /* DDRD */ return 0; - case 0x0a: /* PORTE */ + case 0x0a: /* PORTE */ return cpustate->io->read_byte(MC68HC11_IO_PORTE); - case 0x0e: /* TCNT */ + case 0x0e: /* TCNT */ return cpustate->tcnt >> 8; case 0x0f: return cpustate->tcnt & 0xff; - case 0x16: /* TOC1 */ + case 0x16: /* TOC1 */ return cpustate->toc1 >> 8; case 0x17: return cpustate->toc1 & 0xff; case 0x23: return cpustate->tflg1; - case 0x28: /* SPCR1 */ + case 0x28: /* SPCR1 */ return 0; - case 0x30: /* ADCTL */ + case 0x30: /* ADCTL */ return 0x80; - case 0x31: /* ADR1 */ + case 0x31: /* ADR1 */ { if (cpustate->adctl & 0x10) { @@ -147,7 +147,7 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); } } - case 0x32: /* ADR2 */ + case 0x32: /* ADR2 */ { if (cpustate->adctl & 0x10) { @@ -158,7 +158,7 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); } } - case 0x33: /* ADR3 */ + case 0x33: /* ADR3 */ { if (cpustate->adctl & 0x10) { @@ -169,7 +169,7 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); } } - case 0x34: /* ADR4 */ + case 0x34: /* ADR4 */ { if (cpustate->adctl & 0x10) { @@ -180,33 +180,33 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); } } - case 0x38: /* OPT2 */ + case 0x38: /* OPT2 */ return 0; - case 0x70: /* SCBDH */ + case 0x70: /* SCBDH */ return 0; - case 0x71: /* SCBDL */ + case 0x71: /* SCBDL */ return 0; - case 0x72: /* SCCR1 */ + case 0x72: /* SCCR1 */ return 0; - case 0x73: /* SCCR2 */ + case 0x73: /* SCCR2 */ return 0; - case 0x74: /* SCSR1 */ + case 0x74: /* SCSR1 */ return 0x40; - case 0x7c: /* PORTH */ + case 0x7c: /* PORTH */ return cpustate->io->read_byte(MC68HC11_IO_PORTH); - case 0x7e: /* PORTG */ + case 0x7e: /* PORTG */ return cpustate->io->read_byte(MC68HC11_IO_PORTG); - case 0x7f: /* DDRG */ + case 0x7f: /* DDRG */ return 0; - case 0x88: /* SPCR2 */ + case 0x88: /* SPCR2 */ return 0; - case 0x89: /* SPSR2 */ + case 0x89: /* SPSR2 */ return 0x80; - case 0x8a: /* SPDR2 */ + case 0x8a: /* SPDR2 */ return cpustate->io->read_byte(MC68HC11_IO_SPI2_DATA); - case 0x8b: /* OPT4 */ + case 0x8b: /* OPT4 */ return 0; } @@ -220,60 +220,60 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value) switch(reg) { - case 0x00: /* PORTA */ + case 0x00: /* PORTA */ cpustate->io->write_byte(MC68HC11_IO_PORTA, value); return; - case 0x01: /* DDRA */ + case 0x01: /* DDRA */ //mame_printf_debug("HC11: ddra = %02X\n", value); return; - case 0x03: /* PORTC */ + case 0x03: /* PORTC */ cpustate->io->write_byte(MC68HC11_IO_PORTC, value); return; - case 0x04: /* PORTC */ + case 0x04: /* PORTC */ cpustate->io->write_byte(MC68HC11_IO_PORTB, value); return; - case 0x08: /* PORTD */ + case 0x08: /* PORTD */ cpustate->io->write_byte(MC68HC11_IO_PORTD, value); //mask & 0x3f? return; - case 0x09: /* DDRD */ + case 0x09: /* DDRD */ //mame_printf_debug("HC11: ddrd = %02X\n", value); return; - case 0x0a: /* PORTE */ + case 0x0a: /* PORTE */ cpustate->io->write_byte(MC68HC11_IO_PORTE, value); return; - case 0x0e: /* TCNT */ + case 0x0e: /* TCNT */ case 0x0f: logerror("HC11: TCNT register write %02x %02x!\n",address,value); return; - case 0x16: /* TOC1 */ + case 0x16: /* TOC1 */ /* TODO: inhibit for one bus cycle */ cpustate->toc1 = (value << 8) | (cpustate->toc1 & 0xff); return; case 0x17: cpustate->toc1 = (value & 0xff) | (cpustate->toc1 & 0xff00); return; - case 0x22: /* TMSK1 */ + case 0x22: /* TMSK1 */ cpustate->tmsk1 = value; return; case 0x23: cpustate->tflg1 &= ~value; return; - case 0x24: /* TMSK2 */ + case 0x24: /* TMSK2 */ cpustate->pr = value & 3; return; - case 0x28: /* SPCR1 */ + case 0x28: /* SPCR1 */ return; - case 0x30: /* ADCTL */ + case 0x30: /* ADCTL */ cpustate->adctl = value; return; - case 0x38: /* OPT2 */ + case 0x38: /* OPT2 */ return; - case 0x39: /* OPTION */ + case 0x39: /* OPTION */ return; - case 0x3a: /* COPRST (watchdog) */ + case 0x3a: /* COPRST (watchdog) */ return; - case 0x3d: /* INIT */ + case 0x3d: /* INIT */ { int reg_page = value & 0xf; int ram_page = (value >> 4) & 0xf; @@ -288,41 +288,41 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value) return; } - case 0x3f: /* CONFIG */ + case 0x3f: /* CONFIG */ return; - case 0x70: /* SCBDH */ + case 0x70: /* SCBDH */ return; - case 0x71: /* SCBDL */ + case 0x71: /* SCBDL */ return; - case 0x72: /* SCCR1 */ + case 0x72: /* SCCR1 */ return; - case 0x73: /* SCCR2 */ + case 0x73: /* SCCR2 */ return; - case 0x77: /* SCDRL */ + case 0x77: /* SCDRL */ return; - case 0x7c: /* PORTH */ + case 0x7c: /* PORTH */ cpustate->io->write_byte(MC68HC11_IO_PORTH, value); return; - case 0x7d: /* DDRH */ + case 0x7d: /* DDRH */ //mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, cpustate->pc); return; - case 0x7e: /* PORTG */ + case 0x7e: /* PORTG */ cpustate->io->write_byte(MC68HC11_IO_PORTG, value); return; - case 0x7f: /* DDRG */ + case 0x7f: /* DDRG */ //mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, cpustate->pc); return; - case 0x88: /* SPCR2 */ + case 0x88: /* SPCR2 */ return; - case 0x89: /* SPSR2 */ + case 0x89: /* SPSR2 */ return; - case 0x8a: /* SPDR2 */ + case 0x8a: /* SPDR2 */ cpustate->io->write_byte(MC68HC11_IO_SPI2_DATA, value); return; - case 0x8b: /* OPT4 */ + case 0x8b: /* OPT4 */ return; } @@ -627,17 +627,17 @@ static CPU_SET_INFO( mc68hc11 ) switch (state) { - case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: set_irq_line(cpustate, MC68HC11_IRQ_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + MC68HC11_TOC1_LINE: set_irq_line(cpustate, MC68HC11_TOC1_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: set_irq_line(cpustate, MC68HC11_IRQ_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + MC68HC11_TOC1_LINE: set_irq_line(cpustate, MC68HC11_TOC1_LINE, info->i); break; /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_PC: cpustate->pc = info->i; break; - case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break; - case CPUINFO_INT_REGISTER + HC11_SP: cpustate->sp = info->i; break; - case CPUINFO_INT_REGISTER + HC11_A: cpustate->d.d8.a = info->i; break; - case CPUINFO_INT_REGISTER + HC11_B: cpustate->d.d8.b = info->i; break; - case CPUINFO_INT_REGISTER + HC11_IX: cpustate->ix = info->i; break; - case CPUINFO_INT_REGISTER + HC11_IY: cpustate->iy = info->i; break; + case CPUINFO_INT_PC: cpustate->pc = info->i; break; + case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break; + case CPUINFO_INT_REGISTER + HC11_SP: cpustate->sp = info->i; break; + case CPUINFO_INT_REGISTER + HC11_A: cpustate->d.d8.a = info->i; break; + case CPUINFO_INT_REGISTER + HC11_B: cpustate->d.d8.b = info->i; break; + case CPUINFO_INT_REGISTER + HC11_IX: cpustate->ix = info->i; break; + case CPUINFO_INT_REGISTER + HC11_IY: cpustate->iy = info->i; break; } } @@ -648,56 +648,56 @@ CPU_GET_INFO( mc68hc11 ) switch(state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 1; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 41; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: info->i = cpustate->irq_state[MC68HC11_IRQ_LINE]; break; - case CPUINFO_INT_INPUT_STATE + MC68HC11_TOC1_LINE: info->i = cpustate->irq_state[MC68HC11_TOC1_LINE]; break; - - case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; - - case CPUINFO_INT_PC: /* intentional fallthrough */ - case CPUINFO_INT_REGISTER + HC11_PC: info->i = cpustate->pc; break; - case CPUINFO_INT_REGISTER + HC11_SP: info->i = cpustate->sp; break; - case CPUINFO_INT_REGISTER + HC11_A: info->i = cpustate->d.d8.a; break; - case CPUINFO_INT_REGISTER + HC11_B: info->i = cpustate->d.d8.b; break; - case CPUINFO_INT_REGISTER + HC11_IX: info->i = cpustate->ix; break; - case CPUINFO_INT_REGISTER + HC11_IY: info->i = cpustate->iy; break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11_state); break; + case CPUINFO_INT_INPUT_LINES: info->i = 1; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 41; break; + + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; + + case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: info->i = cpustate->irq_state[MC68HC11_IRQ_LINE]; break; + case CPUINFO_INT_INPUT_STATE + MC68HC11_TOC1_LINE: info->i = cpustate->irq_state[MC68HC11_TOC1_LINE]; break; + + case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; + + case CPUINFO_INT_PC: /* intentional fallthrough */ + case CPUINFO_INT_REGISTER + HC11_PC: info->i = cpustate->pc; break; + case CPUINFO_INT_REGISTER + HC11_SP: info->i = cpustate->sp; break; + case CPUINFO_INT_REGISTER + HC11_A: info->i = cpustate->d.d8.a; break; + case CPUINFO_INT_REGISTER + HC11_B: info->i = cpustate->d.d8.b; break; + case CPUINFO_INT_REGISTER + HC11_IX: info->i = cpustate->ix; break; + case CPUINFO_INT_REGISTER + HC11_IY: info->i = cpustate->iy; break; /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mc68hc11); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hc11); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hc11); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(hc11); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(hc11); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(hc11); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mc68hc11); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hc11); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hc11); break; + case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(hc11); break; + case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(hc11); break; + case CPUINFO_FCT_BURN: info->burn = NULL; break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(hc11); break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "MC68HC11"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola MC68HC11"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "MC68HC11"); break; + case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola MC68HC11"); break; + case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; + case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde"); break; case CPUINFO_STR_FLAGS: sprintf(info->s, "%c%c%c%c%c%c%c%c", @@ -711,12 +711,12 @@ CPU_GET_INFO( mc68hc11 ) (cpustate->ccr & CC_C) ? 'C' : '.'); break; - case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break; - case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", cpustate->sp); break; - case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", cpustate->d.d8.a); break; - case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", cpustate->d.d8.b); break; - case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", cpustate->ix); break; - case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", cpustate->iy); break; + case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break; + case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", cpustate->sp); break; + case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", cpustate->d.d8.a); break; + case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", cpustate->d.d8.b); break; + case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", cpustate->ix); break; + case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", cpustate->iy); break; } } |