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Diffstat (limited to 'src/emu/cpu/m37710/m37710op.h')
-rw-r--r--src/emu/cpu/m37710/m37710op.h2272
1 files changed, 1136 insertions, 1136 deletions
diff --git a/src/emu/cpu/m37710/m37710op.h b/src/emu/cpu/m37710/m37710op.h
index 3f17ea89f00..5255f667bce 100644
--- a/src/emu/cpu/m37710/m37710op.h
+++ b/src/emu/cpu/m37710/m37710op.h
@@ -108,19 +108,19 @@ INLINE void m37710i_write_16_direct(m37710i_cpu_struct *cpustate, uint address,
INLINE uint m37710i_read_24_normal(m37710i_cpu_struct *cpustate, uint address)
{
- return m37710i_read_16_normal(cpustate, address) |
+ return m37710i_read_16_normal(cpustate, address) |
(m37710i_read_8_normal(cpustate, address+2)<<16);
}
INLINE uint m37710i_read_24_immediate(m37710i_cpu_struct *cpustate, uint address)
{
- return m37710i_read_16_immediate(cpustate, address) |
+ return m37710i_read_16_immediate(cpustate, address) |
(m37710i_read_8_immediate(cpustate, address+2)<<16);
}
INLINE uint m37710i_read_24_direct(m37710i_cpu_struct *cpustate, uint address)
{
- return m37710i_read_16_direct(cpustate, address) |
+ return m37710i_read_16_direct(cpustate, address) |
(m37710i_read_8_direct(cpustate, address+2)<<16);
}
@@ -267,13 +267,13 @@ INLINE void m37710i_set_flag_i(m37710i_cpu_struct *cpustate, uint value)
/* Get the Processor Status Register */
INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *cpustate)
{
- return (FLAG_N&0x80) |
- ((FLAG_V>>1)&0x40) |
- FLAG_M |
- FLAG_X |
- FLAG_D |
- FLAG_I |
- ((!FLAG_Z)<<1) |
+ return (FLAG_N&0x80) |
+ ((FLAG_V>>1)&0x40) |
+ FLAG_M |
+ FLAG_X |
+ FLAG_D |
+ FLAG_I |
+ ((!FLAG_Z)<<1) |
((FLAG_C>>8)&1);
}
@@ -314,169 +314,169 @@ INLINE void m37710i_interrupt_software(m37710i_cpu_struct *cpustate, uint vector
/* ======================================================================== */
/* Effective-address based memory access macros */
-#define read_8_NORM(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_IMM(A) m37710i_read_8_immediate(cpustate, A)
-#define read_8_D(A) m37710i_read_8_direct(cpustate, A)
-#define read_8_A(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_AL(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_DX(A) m37710i_read_8_direct(cpustate, A)
-#define read_8_DY(A) m37710i_read_8_direct(cpustate, A)
-#define read_8_AX(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_ALX(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_AY(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_DI(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_DLI(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_AI(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_ALI(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_DXI(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_DIY(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_DLIY(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_AXI(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_S(A) m37710i_read_8_normal(cpustate, A)
-#define read_8_SIY(A) m37710i_read_8_normal(cpustate, A)
-
-#define read_16_NORM(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_IMM(A) m37710i_read_16_immediate(cpustate, A)
-#define read_16_D(A) m37710i_read_16_direct(cpustate, A)
-#define read_16_A(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_AL(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_DX(A) m37710i_read_16_direct(cpustate, A)
-#define read_16_DY(A) m37710i_read_16_direct(cpustate, A)
-#define read_16_AX(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_ALX(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_AY(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_DI(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_DLI(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_AI(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_ALI(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_DXI(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_DIY(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_DLIY(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_AXI(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_S(A) m37710i_read_16_normal(cpustate, A)
-#define read_16_SIY(A) m37710i_read_16_normal(cpustate, A)
-
-#define read_24_NORM(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_IMM(A) m37710i_read_24_immediate(cpustate, A)
-#define read_24_D(A) m37710i_read_24_direct(cpustate, A)
-#define read_24_A(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_AL(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_DX(A) m37710i_read_24_direct(cpustate, A)
-#define read_24_DY(A) m37710i_read_24_direct(cpustate, A)
-#define read_24_AX(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_ALX(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_AY(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_DI(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_DLI(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_AI(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_ALI(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_DXI(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_DIY(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_DLIY(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_AXI(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_S(A) m37710i_read_24_normal(cpustate, A)
-#define read_24_SIY(A) m37710i_read_24_normal(cpustate, A)
-
-#define write_8_NORM(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_D(A, V) m37710i_write_8_direct(cpustate, A, V)
-#define write_8_A(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_AL(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_DX(A, V) m37710i_write_8_direct(cpustate, A, V)
-#define write_8_DY(A, V) m37710i_write_8_direct(cpustate, A, V)
-#define write_8_AX(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_ALX(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_AY(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_DI(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_DLI(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_AI(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_ALI(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_DXI(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_DIY(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_DLIY(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_AXI(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_S(A, V) m37710i_write_8_normal(cpustate, A, V)
-#define write_8_SIY(A, V) m37710i_write_8_normal(cpustate, A, V)
-
-#define write_16_NORM(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_D(A, V) m37710i_write_16_direct(cpustate, A, V)
-#define write_16_A(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_AL(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_DX(A, V) m37710i_write_16_direct(cpustate, A, V)
-#define write_16_DY(A, V) m37710i_write_16_direct(cpustate, A, V)
-#define write_16_AX(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_ALX(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_AY(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_DI(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_DLI(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_AI(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_ALI(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_DXI(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_DIY(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_DLIY(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_AXI(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_S(A, V) m37710i_write_16_normal(cpustate, A, V)
-#define write_16_SIY(A, V) m37710i_write_16_normal(cpustate, A, V)
-
-
-#define OPER_8_IMM(cpustate) read_8_IMM(EA_IMM8(cpustate))
-#define OPER_8_D(cpustate) read_8_D(EA_D(cpustate))
-#define OPER_8_A(cpustate) read_8_A(EA_A(cpustate))
-#define OPER_8_AL(cpustate) read_8_AL(EA_AL(cpustate))
-#define OPER_8_DX(cpustate) read_8_DX(EA_DX(cpustate))
-#define OPER_8_DY(cpustate) read_8_DY(EA_DY(cpustate))
-#define OPER_8_AX(cpustate) read_8_AX(EA_AX(cpustate))
-#define OPER_8_ALX(cpustate) read_8_ALX(EA_ALX(cpustate))
-#define OPER_8_AY(cpustate) read_8_AY(EA_AY(cpustate))
-#define OPER_8_DI(cpustate) read_8_DI(EA_DI(cpustate))
-#define OPER_8_DLI(cpustate) read_8_DLI(EA_DLI(cpustate))
-#define OPER_8_AI(cpustate) read_8_AI(EA_AI(cpustate))
-#define OPER_8_ALI(cpustate) read_8_ALI(EA_ALI(cpustate))
-#define OPER_8_DXI(cpustate) read_8_DXI(EA_DXI(cpustate))
-#define OPER_8_DIY(cpustate) read_8_DIY(EA_DIY(cpustate))
-#define OPER_8_DLIY(cpustate) read_8_DLIY(EA_DLIY(cpustate))
-#define OPER_8_AXI(cpustate) read_8_AXI(EA_AXI(cpustate))
-#define OPER_8_S(cpustate) read_8_S(EA_S(cpustate))
-#define OPER_8_SIY(cpustate) read_8_SIY(EA_SIY(cpustate))
-
-#define OPER_16_IMM(cpustate) read_16_IMM(EA_IMM16(cpustate))
-#define OPER_16_D(cpustate) read_16_D(EA_D(cpustate))
-#define OPER_16_A(cpustate) read_16_A(EA_A(cpustate))
-#define OPER_16_AL(cpustate) read_16_AL(EA_AL(cpustate))
-#define OPER_16_DX(cpustate) read_16_DX(EA_DX(cpustate))
-#define OPER_16_DY(cpustate) read_16_DY(EA_DY(cpustate))
-#define OPER_16_AX(cpustate) read_16_AX(EA_AX(cpustate))
-#define OPER_16_ALX(cpustate) read_16_ALX(EA_ALX(cpustate))
-#define OPER_16_AY(cpustate) read_16_AY(EA_AY(cpustate))
-#define OPER_16_DI(cpustate) read_16_DI(EA_DI(cpustate))
-#define OPER_16_DLI(cpustate) read_16_DLI(EA_DLI(cpustate))
-#define OPER_16_AI(cpustate) read_16_AI(EA_AI(cpustate))
-#define OPER_16_ALI(cpustate) read_16_ALI(EA_ALI(cpustate))
-#define OPER_16_DXI(cpustate) read_16_DXI(EA_DXI(cpustate))
-#define OPER_16_DIY(cpustate) read_16_DIY(EA_DIY(cpustate))
-#define OPER_16_DLIY(cpustate) read_16_DLIY(EA_DLIY(cpustate))
-#define OPER_16_AXI(cpustate) read_16_AXI(EA_AXI(cpustate))
-#define OPER_16_S(cpustate) read_16_S(EA_S(cpustate))
-#define OPER_16_SIY(cpustate) read_16_SIY(EA_SIY(cpustate))
-
-#define OPER_24_IMM(cpustate) read_24_IMM(EA_IMM24(cpustate))
-#define OPER_24_D(cpustate) read_24_D(EA_D(cpustate))
-#define OPER_24_A(cpustate) read_24_A(EA_A(cpustate))
-#define OPER_24_AL(cpustate) read_24_AL(EA_AL(cpustate))
-#define OPER_24_DX(cpustate) read_24_DX(EA_DX(cpustate))
-#define OPER_24_DY(cpustate) read_24_DY(EA_DY(cpustate))
-#define OPER_24_AX(cpustate) read_24_AX(EA_AX(cpustate))
-#define OPER_24_ALX(cpustate) read_24_ALX(EA_ALX(cpustate))
-#define OPER_24_AY(cpustate) read_24_AY(EA_AY(cpustate))
-#define OPER_24_DI(cpustate) read_24_DI(EA_DI(cpustate))
-#define OPER_24_DLI(cpustate) read_24_DLI(EA_DLI(cpustate))
-#define OPER_24_AI(cpustate) read_24_AI(EA_AI(cpustate))
-#define OPER_24_ALI(cpustate) read_24_ALI(EA_ALI())
-#define OPER_24_DXI(cpustate) read_24_DXI(EA_DXI(cpustate))
-#define OPER_24_DIY(cpustate) read_24_DIY(EA_DIY(cpustate))
-#define OPER_24_DLIY(cpustate) read_24_DLIY(EA_DLIY(cpustate))
-#define OPER_24_AXI(cpustate) read_24_AXI(EA_AXI(cpustate))
-#define OPER_24_S(cpustate) read_24_S(EA_S(cpustate))
-#define OPER_24_SIY(cpustate) read_24_SIY(EA_SIY(cpustate))
+#define read_8_NORM(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_IMM(A) m37710i_read_8_immediate(cpustate, A)
+#define read_8_D(A) m37710i_read_8_direct(cpustate, A)
+#define read_8_A(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_AL(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_DX(A) m37710i_read_8_direct(cpustate, A)
+#define read_8_DY(A) m37710i_read_8_direct(cpustate, A)
+#define read_8_AX(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_ALX(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_AY(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_DI(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_DLI(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_AI(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_ALI(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_DXI(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_DIY(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_DLIY(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_AXI(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_S(A) m37710i_read_8_normal(cpustate, A)
+#define read_8_SIY(A) m37710i_read_8_normal(cpustate, A)
+
+#define read_16_NORM(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_IMM(A) m37710i_read_16_immediate(cpustate, A)
+#define read_16_D(A) m37710i_read_16_direct(cpustate, A)
+#define read_16_A(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_AL(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_DX(A) m37710i_read_16_direct(cpustate, A)
+#define read_16_DY(A) m37710i_read_16_direct(cpustate, A)
+#define read_16_AX(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_ALX(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_AY(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_DI(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_DLI(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_AI(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_ALI(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_DXI(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_DIY(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_DLIY(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_AXI(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_S(A) m37710i_read_16_normal(cpustate, A)
+#define read_16_SIY(A) m37710i_read_16_normal(cpustate, A)
+
+#define read_24_NORM(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_IMM(A) m37710i_read_24_immediate(cpustate, A)
+#define read_24_D(A) m37710i_read_24_direct(cpustate, A)
+#define read_24_A(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_AL(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_DX(A) m37710i_read_24_direct(cpustate, A)
+#define read_24_DY(A) m37710i_read_24_direct(cpustate, A)
+#define read_24_AX(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_ALX(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_AY(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_DI(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_DLI(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_AI(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_ALI(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_DXI(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_DIY(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_DLIY(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_AXI(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_S(A) m37710i_read_24_normal(cpustate, A)
+#define read_24_SIY(A) m37710i_read_24_normal(cpustate, A)
+
+#define write_8_NORM(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_D(A, V) m37710i_write_8_direct(cpustate, A, V)
+#define write_8_A(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_AL(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DX(A, V) m37710i_write_8_direct(cpustate, A, V)
+#define write_8_DY(A, V) m37710i_write_8_direct(cpustate, A, V)
+#define write_8_AX(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_ALX(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_AY(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DI(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DLI(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_AI(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_ALI(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DXI(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DIY(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DLIY(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_AXI(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_S(A, V) m37710i_write_8_normal(cpustate, A, V)
+#define write_8_SIY(A, V) m37710i_write_8_normal(cpustate, A, V)
+
+#define write_16_NORM(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_D(A, V) m37710i_write_16_direct(cpustate, A, V)
+#define write_16_A(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_AL(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DX(A, V) m37710i_write_16_direct(cpustate, A, V)
+#define write_16_DY(A, V) m37710i_write_16_direct(cpustate, A, V)
+#define write_16_AX(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_ALX(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_AY(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DI(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DLI(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_AI(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_ALI(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DXI(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DIY(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DLIY(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_AXI(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_S(A, V) m37710i_write_16_normal(cpustate, A, V)
+#define write_16_SIY(A, V) m37710i_write_16_normal(cpustate, A, V)
+
+
+#define OPER_8_IMM(cpustate) read_8_IMM(EA_IMM8(cpustate))
+#define OPER_8_D(cpustate) read_8_D(EA_D(cpustate))
+#define OPER_8_A(cpustate) read_8_A(EA_A(cpustate))
+#define OPER_8_AL(cpustate) read_8_AL(EA_AL(cpustate))
+#define OPER_8_DX(cpustate) read_8_DX(EA_DX(cpustate))
+#define OPER_8_DY(cpustate) read_8_DY(EA_DY(cpustate))
+#define OPER_8_AX(cpustate) read_8_AX(EA_AX(cpustate))
+#define OPER_8_ALX(cpustate) read_8_ALX(EA_ALX(cpustate))
+#define OPER_8_AY(cpustate) read_8_AY(EA_AY(cpustate))
+#define OPER_8_DI(cpustate) read_8_DI(EA_DI(cpustate))
+#define OPER_8_DLI(cpustate) read_8_DLI(EA_DLI(cpustate))
+#define OPER_8_AI(cpustate) read_8_AI(EA_AI(cpustate))
+#define OPER_8_ALI(cpustate) read_8_ALI(EA_ALI(cpustate))
+#define OPER_8_DXI(cpustate) read_8_DXI(EA_DXI(cpustate))
+#define OPER_8_DIY(cpustate) read_8_DIY(EA_DIY(cpustate))
+#define OPER_8_DLIY(cpustate) read_8_DLIY(EA_DLIY(cpustate))
+#define OPER_8_AXI(cpustate) read_8_AXI(EA_AXI(cpustate))
+#define OPER_8_S(cpustate) read_8_S(EA_S(cpustate))
+#define OPER_8_SIY(cpustate) read_8_SIY(EA_SIY(cpustate))
+
+#define OPER_16_IMM(cpustate) read_16_IMM(EA_IMM16(cpustate))
+#define OPER_16_D(cpustate) read_16_D(EA_D(cpustate))
+#define OPER_16_A(cpustate) read_16_A(EA_A(cpustate))
+#define OPER_16_AL(cpustate) read_16_AL(EA_AL(cpustate))
+#define OPER_16_DX(cpustate) read_16_DX(EA_DX(cpustate))
+#define OPER_16_DY(cpustate) read_16_DY(EA_DY(cpustate))
+#define OPER_16_AX(cpustate) read_16_AX(EA_AX(cpustate))
+#define OPER_16_ALX(cpustate) read_16_ALX(EA_ALX(cpustate))
+#define OPER_16_AY(cpustate) read_16_AY(EA_AY(cpustate))
+#define OPER_16_DI(cpustate) read_16_DI(EA_DI(cpustate))
+#define OPER_16_DLI(cpustate) read_16_DLI(EA_DLI(cpustate))
+#define OPER_16_AI(cpustate) read_16_AI(EA_AI(cpustate))
+#define OPER_16_ALI(cpustate) read_16_ALI(EA_ALI(cpustate))
+#define OPER_16_DXI(cpustate) read_16_DXI(EA_DXI(cpustate))
+#define OPER_16_DIY(cpustate) read_16_DIY(EA_DIY(cpustate))
+#define OPER_16_DLIY(cpustate) read_16_DLIY(EA_DLIY(cpustate))
+#define OPER_16_AXI(cpustate) read_16_AXI(EA_AXI(cpustate))
+#define OPER_16_S(cpustate) read_16_S(EA_S(cpustate))
+#define OPER_16_SIY(cpustate) read_16_SIY(EA_SIY(cpustate))
+
+#define OPER_24_IMM(cpustate) read_24_IMM(EA_IMM24(cpustate))
+#define OPER_24_D(cpustate) read_24_D(EA_D(cpustate))
+#define OPER_24_A(cpustate) read_24_A(EA_A(cpustate))
+#define OPER_24_AL(cpustate) read_24_AL(EA_AL(cpustate))
+#define OPER_24_DX(cpustate) read_24_DX(EA_DX(cpustate))
+#define OPER_24_DY(cpustate) read_24_DY(EA_DY(cpustate))
+#define OPER_24_AX(cpustate) read_24_AX(EA_AX(cpustate))
+#define OPER_24_ALX(cpustate) read_24_ALX(EA_ALX(cpustate))
+#define OPER_24_AY(cpustate) read_24_AY(EA_AY(cpustate))
+#define OPER_24_DI(cpustate) read_24_DI(EA_DI(cpustate))
+#define OPER_24_DLI(cpustate) read_24_DLI(EA_DLI(cpustate))
+#define OPER_24_AI(cpustate) read_24_AI(EA_AI(cpustate))
+#define OPER_24_ALI(cpustate) read_24_ALI(EA_ALI())
+#define OPER_24_DXI(cpustate) read_24_DXI(EA_DXI(cpustate))
+#define OPER_24_DIY(cpustate) read_24_DIY(EA_DIY(cpustate))
+#define OPER_24_DLIY(cpustate) read_24_DLIY(EA_DLIY(cpustate))
+#define OPER_24_AXI(cpustate) read_24_AXI(EA_AXI(cpustate))
+#define OPER_24_S(cpustate) read_24_S(EA_S(cpustate))
+#define OPER_24_SIY(cpustate) read_24_SIY(EA_SIY(cpustate))
INLINE uint EA_IMM8(m37710i_cpu_struct *cpustate) {REG_PC += 1; return REG_PB | MAKE_UINT_16(REG_PC-1);}
INLINE uint EA_IMM16(m37710i_cpu_struct *cpustate) {REG_PC += 2; return REG_PB | MAKE_UINT_16(REG_PC-2);}
@@ -510,415 +510,415 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
#if FLAG_SET_M
#if FLAG_SET_X
-#define OP_PSH(MODE) \
- SRC = OPER_8_##MODE(cpustate); \
+#define OP_PSH(MODE) \
+ SRC = OPER_8_##MODE(cpustate); \
CLK(12); \
- if (SRC&0x1) \
+ if (SRC&0x1) \
{ m37710i_push_8(cpustate, REG_A); CLK(2); } \
- if (SRC&0x2) \
+ if (SRC&0x2) \
{ m37710i_push_8(cpustate, REG_BA); CLK(2); } \
- if (SRC&0x4) \
+ if (SRC&0x4) \
{ m37710i_push_8(cpustate, REG_X); CLK(2); } \
- if (SRC&0x8) \
+ if (SRC&0x8) \
{ m37710i_push_8(cpustate, REG_Y); CLK(2); } \
- if (SRC&0x10) \
+ if (SRC&0x10) \
{ m37710i_push_16(cpustate, REG_D); CLK(2); } \
- if (SRC&0x20) \
+ if (SRC&0x20) \
{ m37710i_push_8(cpustate, REG_DB>>16); CLK(1); } \
- if (SRC&0x40) \
+ if (SRC&0x40) \
{ m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \
- if (SRC&0x80) \
+ if (SRC&0x80) \
{ m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); }
-#else // FLAG_SET_X
-#define OP_PSH(MODE) \
- SRC = OPER_8_##MODE(cpustate); \
+#else // FLAG_SET_X
+#define OP_PSH(MODE) \
+ SRC = OPER_8_##MODE(cpustate); \
CLK(12); \
- if (SRC&0x1) \
+ if (SRC&0x1) \
{ m37710i_push_8(cpustate, REG_A); CLK(2); } \
- if (SRC&0x2) \
+ if (SRC&0x2) \
{ m37710i_push_8(cpustate, REG_BA); CLK(2); } \
- if (SRC&0x4) \
+ if (SRC&0x4) \
{ m37710i_push_16(cpustate, REG_X); CLK(2); } \
- if (SRC&0x8) \
+ if (SRC&0x8) \
{ m37710i_push_16(cpustate, REG_Y); CLK(2); } \
- if (SRC&0x10) \
+ if (SRC&0x10) \
{ m37710i_push_16(cpustate, REG_D); CLK(2); } \
- if (SRC&0x20) \
+ if (SRC&0x20) \
{ m37710i_push_8(cpustate, REG_DB>>16); CLK(1); } \
- if (SRC&0x40) \
+ if (SRC&0x40) \
{ m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \
- if (SRC&0x80) \
+ if (SRC&0x80) \
{ m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); }
-#endif // FLAG_SET_X
-#else // FLAG_SET_M
+#endif // FLAG_SET_X
+#else // FLAG_SET_M
#if FLAG_SET_X
-#define OP_PSH(MODE) \
- SRC = OPER_8_##MODE(cpustate); \
+#define OP_PSH(MODE) \
+ SRC = OPER_8_##MODE(cpustate); \
CLK(12); \
- if (SRC&0x1) \
+ if (SRC&0x1) \
{ m37710i_push_16(cpustate, REG_A); CLK(2); } \
- if (SRC&0x2) \
+ if (SRC&0x2) \
{ m37710i_push_16(cpustate, REG_BA); CLK(2); } \
- if (SRC&0x4) \
+ if (SRC&0x4) \
{ m37710i_push_8(cpustate, REG_X); CLK(2); } \
- if (SRC&0x8) \
+ if (SRC&0x8) \
{ m37710i_push_8(cpustate, REG_Y); CLK(2); } \
- if (SRC&0x10) \
+ if (SRC&0x10) \
{ m37710i_push_16(cpustate, REG_D); CLK(2); } \
- if (SRC&0x20) \
+ if (SRC&0x20) \
{ m37710i_push_8(cpustate, REG_DB>>16); CLK(1); } \
- if (SRC&0x40) \
+ if (SRC&0x40) \
{ m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \
- if (SRC&0x80) \
+ if (SRC&0x80) \
{ m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); }
-#else // FLAG_SET_X
-#define OP_PSH(MODE) \
- SRC = OPER_8_##MODE(cpustate); \
+#else // FLAG_SET_X
+#define OP_PSH(MODE) \
+ SRC = OPER_8_##MODE(cpustate); \
CLK(12); \
- if (SRC&0x1) \
+ if (SRC&0x1) \
{ m37710i_push_16(cpustate, REG_A); CLK(2); } \
- if (SRC&0x2) \
+ if (SRC&0x2) \
{ m37710i_push_16(cpustate, REG_BA); CLK(2);} \
- if (SRC&0x4) \
+ if (SRC&0x4) \
{ m37710i_push_16(cpustate, REG_X); CLK(2); } \
- if (SRC&0x8) \
+ if (SRC&0x8) \
{ m37710i_push_16(cpustate, REG_Y); CLK(2); } \
- if (SRC&0x10) \
+ if (SRC&0x10) \
{ m37710i_push_16(cpustate, REG_D); CLK(2); } \
- if (SRC&0x20) \
+ if (SRC&0x20) \
{ m37710i_push_8(cpustate, REG_DB>>16); CLK(1); } \
- if (SRC&0x40) \
+ if (SRC&0x40) \
{ m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \
- if (SRC&0x80) \
+ if (SRC&0x80) \
{ m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); }
-#endif // FLAG_SET_X
-#endif // FLAG_SET_M
+#endif // FLAG_SET_X
+#endif // FLAG_SET_M
/* M37710 Pull all */
/* Unusual behavior: bit 6 has no effect */
#undef OP_PUL
-#define OP_PUL(MODE) \
- SRC = OPER_8_##MODE(cpustate); \
+#define OP_PUL(MODE) \
+ SRC = OPER_8_##MODE(cpustate); \
CLK(14); \
- if (SRC&0x80) \
+ if (SRC&0x80) \
{ m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); CLK(3); } \
- if (SRC&0x20) \
+ if (SRC&0x20) \
{ REG_DB = m37710i_pull_8(cpustate) << 16; CLK(3); } \
- if (SRC&0x10) \
+ if (SRC&0x10) \
{ REG_D = m37710i_pull_16(cpustate); CLK(4); } \
if (m37710i_get_reg_p(cpustate) & XFLAG_SET) \
{ \
- if (SRC&0x8) \
+ if (SRC&0x8) \
{ REG_Y = m37710i_pull_8(cpustate); CLK(3); } \
- if (SRC&0x4) \
+ if (SRC&0x4) \
{ REG_X = m37710i_pull_8(cpustate); CLK(3); } \
} \
else \
{ \
- if (SRC&0x8) \
+ if (SRC&0x8) \
{ REG_Y = m37710i_pull_16(cpustate); CLK(3); } \
- if (SRC&0x4) \
+ if (SRC&0x4) \
{ REG_X = m37710i_pull_16(cpustate); CLK(3); } \
} \
if (m37710i_get_reg_p(cpustate) & MFLAG_SET) \
{ \
- if (SRC&0x2) \
+ if (SRC&0x2) \
{ REG_BA = m37710i_pull_8(cpustate); CLK(3); } \
- if (SRC&0x1) \
+ if (SRC&0x1) \
{ REG_A = m37710i_pull_8(cpustate); CLK(3); } \
} \
else \
{ \
- if (SRC&0x2) \
+ if (SRC&0x2) \
{ REG_BA = m37710i_pull_16(cpustate); CLK(3); } \
- if (SRC&0x1) \
+ if (SRC&0x1) \
{ REG_A = m37710i_pull_16(cpustate); CLK(3); } \
- } \
+ } \
m37710i_update_irqs(cpustate)
/* M37710 Multiply */
#undef OP_MPY
#if FLAG_SET_M
-#define OP_MPY(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE + 14); \
- SRC = OPER_8_##MODE(cpustate); \
+#define OP_MPY(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE + 14); \
+ SRC = OPER_8_##MODE(cpustate); \
{ UINT16 temp = SRC * (REG_A&0xff); REG_A = temp & 0xff; REG_BA = (temp>>8)&0xff; FLAG_Z = temp; FLAG_N = (temp & 0x8000) ? 1 : 0; FLAG_C = 0; }
#else
-#define OP_MPY(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE + 14+8); \
- SRC = OPER_16_##MODE(cpustate); \
+#define OP_MPY(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE + 14+8); \
+ SRC = OPER_16_##MODE(cpustate); \
{ UINT32 temp = SRC * REG_A; REG_A = temp & 0xffff; REG_BA = (temp>>16)&0xffff; FLAG_Z = temp; FLAG_N = (temp & 0x80000000) ? 1 : 0; FLAG_C = 0; }
#endif
/* M37710 Divide */
#undef OP_DIV
#if FLAG_SET_M
-#define OP_DIV(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE + 17); \
- SRC = (REG_BA&0xff)<<8 | (REG_A & 0xff); \
- DST = OPER_8_##MODE(cpustate); \
- if (DST != 0) \
- { \
- UINT16 tempa = SRC / DST; UINT16 tempb = SRC % DST; \
- FLAG_V = ((tempa | tempb) & 0xff00) ? VFLAG_SET : 0; \
- FLAG_C = FLAG_V ? CFLAG_SET : 0; \
- if (!FLAG_V) { FLAG_N = (tempa & 0x80) ? 1 : 0; } \
- FLAG_Z = REG_A = tempa & 0xff; REG_BA = tempb & 0xff; \
- CLK(8); \
+#define OP_DIV(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE + 17); \
+ SRC = (REG_BA&0xff)<<8 | (REG_A & 0xff); \
+ DST = OPER_8_##MODE(cpustate); \
+ if (DST != 0) \
+ { \
+ UINT16 tempa = SRC / DST; UINT16 tempb = SRC % DST; \
+ FLAG_V = ((tempa | tempb) & 0xff00) ? VFLAG_SET : 0; \
+ FLAG_C = FLAG_V ? CFLAG_SET : 0; \
+ if (!FLAG_V) { FLAG_N = (tempa & 0x80) ? 1 : 0; } \
+ FLAG_Z = REG_A = tempa & 0xff; REG_BA = tempb & 0xff; \
+ CLK(8); \
} else m37710i_interrupt_software(cpustate, 0xfffc)
#else
-#define OP_DIV(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE + 17); \
- SRC = (REG_BA<<16) | REG_A; \
- DST = OPER_16_##MODE(cpustate); \
- if (DST != 0) \
- { \
- UINT32 tempa = SRC / DST; UINT32 tempb = SRC % DST; \
- FLAG_V = ((tempa | tempb) & 0xffff0000) ? VFLAG_SET : 0; \
- FLAG_C = FLAG_V ? CFLAG_SET : 0; \
- if (!FLAG_V) { FLAG_N = (tempa & 0x8000) ? 1 : 0; } \
- FLAG_Z = REG_A = tempa & 0xffff; REG_BA = tempb & 0xffff; \
- CLK(8+15); \
+#define OP_DIV(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE + 17); \
+ SRC = (REG_BA<<16) | REG_A; \
+ DST = OPER_16_##MODE(cpustate); \
+ if (DST != 0) \
+ { \
+ UINT32 tempa = SRC / DST; UINT32 tempb = SRC % DST; \
+ FLAG_V = ((tempa | tempb) & 0xffff0000) ? VFLAG_SET : 0; \
+ FLAG_C = FLAG_V ? CFLAG_SET : 0; \
+ if (!FLAG_V) { FLAG_N = (tempa & 0x8000) ? 1 : 0; } \
+ FLAG_Z = REG_A = tempa & 0xffff; REG_BA = tempb & 0xffff; \
+ CLK(8+15); \
} else m37710i_interrupt_software(cpustate, 0xfffc)
#endif
/* M37710 Add With Carry */
#undef OP_ADC
#if FLAG_SET_M
-#define OP_ADC(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
- SRC = OPER_8_##MODE(cpustate); \
- FLAG_C = REG_A + SRC + CFLAG_AS_1(); \
- if(FLAG_D) \
- { \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C+=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C+=0x60; \
- } \
- FLAG_V = VFLAG_ADD_8(SRC, REG_A, FLAG_C); \
+#define OP_ADC(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ SRC = OPER_8_##MODE(cpustate); \
+ FLAG_C = REG_A + SRC + CFLAG_AS_1(); \
+ if(FLAG_D) \
+ { \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C+=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C+=0x60; \
+ } \
+ FLAG_V = VFLAG_ADD_8(SRC, REG_A, FLAG_C); \
FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C)
#else
-#define OP_ADC(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- SRC = OPER_16_##MODE(cpustate); \
- if(!FLAG_D) \
- { \
- FLAG_C = REG_A + SRC + CFLAG_AS_1(); \
- FLAG_V = VFLAG_ADD_16(SRC, REG_A, FLAG_C); \
- FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(REG_A); \
- FLAG_C = CFLAG_16(FLAG_C); \
- BREAKOUT; \
- } \
- FLAG_C = MAKE_UINT_8(REG_A) + MAKE_UINT_8(SRC) + CFLAG_AS_1(); \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C+=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C+=0x60; \
- FLAG_Z = MAKE_UINT_8(FLAG_C); \
+#define OP_ADC(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ SRC = OPER_16_##MODE(cpustate); \
+ if(!FLAG_D) \
+ { \
+ FLAG_C = REG_A + SRC + CFLAG_AS_1(); \
+ FLAG_V = VFLAG_ADD_16(SRC, REG_A, FLAG_C); \
+ FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(REG_A); \
+ FLAG_C = CFLAG_16(FLAG_C); \
+ BREAKOUT; \
+ } \
+ FLAG_C = MAKE_UINT_8(REG_A) + MAKE_UINT_8(SRC) + CFLAG_AS_1(); \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C+=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C+=0x60; \
+ FLAG_Z = MAKE_UINT_8(FLAG_C); \
\
- FLAG_C = MAKE_UINT_8(REG_A>>8) + MAKE_UINT_8(SRC>>8) + CFLAG_AS_1(); \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C+=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C+=0x60; \
- FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \
- FLAG_N = NFLAG_16(FLAG_Z); \
- FLAG_V = VFLAG_ADD_16(SRC, REG_A, FLAG_C); \
+ FLAG_C = MAKE_UINT_8(REG_A>>8) + MAKE_UINT_8(SRC>>8) + CFLAG_AS_1(); \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C+=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C+=0x60; \
+ FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ FLAG_V = VFLAG_ADD_16(SRC, REG_A, FLAG_C); \
REG_A = FLAG_Z
#endif
/* M37710 Add With Carry - B accumulator*/
#undef OP_ADCB
#if FLAG_SET_M
-#define OP_ADCB(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
- SRC = OPER_8_##MODE(cpustate); \
- FLAG_C = REG_BA + SRC + CFLAG_AS_1(); \
- if(FLAG_D) \
- { \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C+=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C+=0x60; \
- } \
- FLAG_V = VFLAG_ADD_8(SRC, REG_BA, FLAG_C); \
+#define OP_ADCB(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ SRC = OPER_8_##MODE(cpustate); \
+ FLAG_C = REG_BA + SRC + CFLAG_AS_1(); \
+ if(FLAG_D) \
+ { \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C+=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C+=0x60; \
+ } \
+ FLAG_V = VFLAG_ADD_8(SRC, REG_BA, FLAG_C); \
FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C)
#else
-#define OP_ADCB(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- SRC = OPER_16_##MODE(cpustate); \
- if(!FLAG_D) \
- { \
- FLAG_C = REG_BA + SRC + CFLAG_AS_1(); \
- FLAG_V = VFLAG_ADD_16(SRC, REG_BA, FLAG_C); \
- FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(REG_BA); \
- FLAG_C = CFLAG_16(FLAG_C); \
- BREAKOUT; \
- } \
- FLAG_C = MAKE_UINT_8(REG_BA) + MAKE_UINT_8(SRC) + CFLAG_AS_1(); \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C+=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C+=0x60; \
- FLAG_Z = MAKE_UINT_8(FLAG_C); \
+#define OP_ADCB(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ SRC = OPER_16_##MODE(cpustate); \
+ if(!FLAG_D) \
+ { \
+ FLAG_C = REG_BA + SRC + CFLAG_AS_1(); \
+ FLAG_V = VFLAG_ADD_16(SRC, REG_BA, FLAG_C); \
+ FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(REG_BA); \
+ FLAG_C = CFLAG_16(FLAG_C); \
+ BREAKOUT; \
+ } \
+ FLAG_C = MAKE_UINT_8(REG_BA) + MAKE_UINT_8(SRC) + CFLAG_AS_1(); \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C+=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C+=0x60; \
+ FLAG_Z = MAKE_UINT_8(FLAG_C); \
\
- FLAG_C = MAKE_UINT_8(REG_BA>>8) + MAKE_UINT_8(SRC>>8) + CFLAG_AS_1(); \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C+=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C+=0x60; \
- FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \
- FLAG_N = NFLAG_16(FLAG_Z); \
- FLAG_V = VFLAG_ADD_16(SRC, REG_BA, FLAG_C); \
+ FLAG_C = MAKE_UINT_8(REG_BA>>8) + MAKE_UINT_8(SRC>>8) + CFLAG_AS_1(); \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C+=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C+=0x60; \
+ FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ FLAG_V = VFLAG_ADD_16(SRC, REG_BA, FLAG_C); \
REG_BA = FLAG_Z
#endif
/* M37710 Logical AND with accumulator */
#undef OP_AND
#if FLAG_SET_M
-#define OP_AND(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+#define OP_AND(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
FLAG_N = FLAG_Z = REG_A &= OPER_8_##MODE(cpustate)
#else
-#define OP_AND(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_Z = REG_A &= OPER_16_##MODE(cpustate); \
+#define OP_AND(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REG_A &= OPER_16_##MODE(cpustate); \
FLAG_N = NFLAG_16(REG_A)
#endif
/* M37710 Logical AND with B accumulator */
#undef OP_ANDB
#if FLAG_SET_M
-#define OP_ANDB(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+#define OP_ANDB(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
FLAG_N = FLAG_Z = REG_BA &= OPER_8_##MODE(cpustate)
#else
-#define OP_ANDB(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_Z = REG_BA &= OPER_16_##MODE(cpustate); \
+#define OP_ANDB(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REG_BA &= OPER_16_##MODE(cpustate); \
FLAG_N = NFLAG_16(REG_BA)
#endif
/* M37710 Arithmetic Shift Left accumulator */
#undef OP_ASL
#if FLAG_SET_M
-#define OP_ASL() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_C = REG_A << 1; \
+#define OP_ASL() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = REG_A << 1; \
FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C)
#else
-#define OP_ASL() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_C = REG_A << 1; \
- FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(FLAG_C); \
+#define OP_ASL() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = REG_A << 1; \
+ FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
FLAG_C = CFLAG_16(FLAG_C)
#endif
/* M37710 Arithmetic Shift Left B accumulator */
#undef OP_BSL
#if FLAG_SET_M
-#define OP_BSL() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_C = REG_BA << 1; \
+#define OP_BSL() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = REG_BA << 1; \
FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C)
#else
-#define OP_BSL() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_C = REG_BA << 1; \
- FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(FLAG_C); \
+#define OP_BSL() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = REG_BA << 1; \
+ FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
FLAG_C = CFLAG_16(FLAG_C)
#endif
/* M37710 Arithmetic Shift Left operand */
#undef OP_ASLM
#if FLAG_SET_M
-#define OP_ASLM(MODE) \
- CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_C = read_8_##MODE(DST) << 1; \
- FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
+#define OP_ASLM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_C = read_8_##MODE(DST) << 1; \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
write_8_##MODE(DST, FLAG_Z)
#else
-#define OP_ASLM(MODE) \
- CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_C = read_16_##MODE(DST) << 1; \
- FLAG_Z = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(FLAG_C); \
- FLAG_C = CFLAG_16(FLAG_C); \
+#define OP_ASLM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_C = read_16_##MODE(DST) << 1; \
+ FLAG_Z = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
+ FLAG_C = CFLAG_16(FLAG_C); \
write_16_##MODE(DST, FLAG_Z)
#endif
/* M37710 Branch on Condition Code */
#undef OP_BCC
-#define OP_BCC(COND) \
- DST = OPER_8_IMM(cpustate); \
- if(COND) \
- { \
- CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
- m37710i_branch_8(cpustate, DST); \
- BREAKOUT; \
- } \
- CLK(CLK_OP + CLK_RELATIVE_8); \
+#define OP_BCC(COND) \
+ DST = OPER_8_IMM(cpustate); \
+ if(COND) \
+ { \
+ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
+ m37710i_branch_8(cpustate, DST); \
+ BREAKOUT; \
+ } \
+ CLK(CLK_OP + CLK_RELATIVE_8); \
/* M37710 Cause a Break interrupt */
#undef OP_BRK
-#define OP_BRK() \
- REG_PC++; CLK(CLK_OP + CLK_R8 + CLK_IMM); \
- logerror("error M37710: BRK at PC=%06x\n", REG_PB|REG_PC); \
+#define OP_BRK() \
+ REG_PC++; CLK(CLK_OP + CLK_R8 + CLK_IMM); \
+ logerror("error M37710: BRK at PC=%06x\n", REG_PB|REG_PC); \
m37710i_interrupt_software(cpustate, 0xfffa)
/* M37710 Branch Always */
#undef OP_BRA
-#define OP_BRA() \
- CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_8); \
+#define OP_BRA() \
+ CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_8); \
m37710i_branch_8(cpustate, OPER_8_IMM(cpustate))
/* M37710 Branch Always Long */
#undef OP_BRL
-#define OP_BRL() \
- CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_16); \
+#define OP_BRL() \
+ CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_16); \
m37710i_branch_16(cpustate, OPER_16_IMM(cpustate))
/* M37710 Clear Carry flag */
#undef OP_CLC
-#define OP_CLC() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_CLC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_C = CFLAG_CLEAR
/* M37710 Clear Interrupt Mask flag */
#undef OP_CLI
-#define OP_CLI() \
- CLK(CLK_OP + CLK_IMPLIED); \
- m37710i_set_flag_i(cpustate, IFLAG_CLEAR); \
+#define OP_CLI() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ m37710i_set_flag_i(cpustate, IFLAG_CLEAR); \
m37710i_update_irqs(cpustate)
/* M37710 Clear oVerflow flag */
#undef OP_CLV
-#define OP_CLV() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_CLV() \
+ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_V = VFLAG_CLEAR
/* M37710 Compare operand to accumulator */
/* Unusual behavior: C flag is inverted */
#undef OP_CMP
#if FLAG_SET_M
-#define OP_CMP(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
- FLAG_C = REG_A - OPER_8_##MODE(cpustate); \
- FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
+#define OP_CMP(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_C = REG_A - OPER_8_##MODE(cpustate); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
FLAG_C ^= CFLAG_SET
#else
-#define OP_CMP(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_C = REG_A - OPER_16_##MODE(cpustate); \
- FLAG_Z = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(FLAG_C); \
+#define OP_CMP(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_C = REG_A - OPER_16_##MODE(cpustate); \
+ FLAG_Z = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
FLAG_C = ~CFLAG_16(FLAG_C)
#endif
@@ -926,17 +926,17 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
/* Unusual behavior: C flag is inverted */
#undef OP_CMPB
#if FLAG_SET_M
-#define OP_CMPB(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
- FLAG_C = REG_BA - OPER_8_##MODE(cpustate); \
- FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
+#define OP_CMPB(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_C = REG_BA - OPER_8_##MODE(cpustate); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
FLAG_C ^= CFLAG_SET
#else
-#define OP_CMPB(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_C = REG_BA - OPER_16_##MODE(cpustate); \
- FLAG_Z = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(FLAG_C); \
+#define OP_CMPB(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_C = REG_BA - OPER_16_##MODE(cpustate); \
+ FLAG_Z = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
FLAG_C = ~CFLAG_16(FLAG_C)
#endif
@@ -944,412 +944,412 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
/* Unusual behavior: C flag is inverted */
#undef OP_CMPX
#if FLAG_SET_X
-#define OP_CMPX(REG, MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
- FLAG_C = REG - OPER_8_##MODE(cpustate); \
- FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
+#define OP_CMPX(REG, MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_C = REG - OPER_8_##MODE(cpustate); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
FLAG_C ^= CFLAG_SET
#else
-#define OP_CMPX(REG, MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_C = REG - OPER_16_##MODE(cpustate); \
- FLAG_Z = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(FLAG_C); \
+#define OP_CMPX(REG, MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_C = REG - OPER_16_##MODE(cpustate); \
+ FLAG_Z = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
FLAG_C = ~CFLAG_16(FLAG_C)
#endif
/* M37710 Decrement accumulator */
#undef OP_DEC
#if FLAG_SET_M
-#define OP_DEC() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_DEC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(REG_A - 1)
#else
-#define OP_DEC() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_A = MAKE_UINT_16(REG_A - 1); \
+#define OP_DEC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_A = MAKE_UINT_16(REG_A - 1); \
FLAG_N = NFLAG_16(REG_A)
#endif
/* M37710 Decrement B accumulator */
#undef OP_DECB
#if FLAG_SET_M
-#define OP_DECB() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_DECB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(REG_BA - 1)
#else
-#define OP_DECB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_BA = MAKE_UINT_16(REG_BA - 1); \
+#define OP_DECB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_BA = MAKE_UINT_16(REG_BA - 1); \
FLAG_N = NFLAG_16(REG_BA)
#endif
/* M37710 Decrement operand */
#undef OP_DECM
#if FLAG_SET_M
-#define OP_DECM(MODE) \
- CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) - 1); \
+#define OP_DECM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) - 1); \
write_8_##MODE(DST, FLAG_Z)
#else
-#define OP_DECM(MODE) \
- CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) - 1); \
- FLAG_N = NFLAG_16(FLAG_Z); \
+#define OP_DECM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) - 1); \
+ FLAG_N = NFLAG_16(FLAG_Z); \
write_16_##MODE(DST, FLAG_Z)
#endif
/* M37710 Decrement index register */
#undef OP_DECX
#if FLAG_SET_X
-#define OP_DECX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_DECX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_N = FLAG_Z = REG = MAKE_UINT_8(REG - 1)
#else
-#define OP_DECX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG = MAKE_UINT_16(REG - 1); \
+#define OP_DECX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = MAKE_UINT_16(REG - 1); \
FLAG_N = NFLAG_16(REG)
#endif
/* M37710 Exclusive Or operand to accumulator */
#undef OP_EOR
#if FLAG_SET_M
-#define OP_EOR(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+#define OP_EOR(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
FLAG_N = FLAG_Z = REG_A ^= OPER_8_##MODE(cpustate)
#else
-#define OP_EOR(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_Z = REG_A ^= OPER_16_##MODE(cpustate); \
+#define OP_EOR(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REG_A ^= OPER_16_##MODE(cpustate); \
FLAG_N = NFLAG_16(REG_A)
#endif
/* M37710 Exclusive Or operand to accumulator B */
#undef OP_EORB
#if FLAG_SET_M
-#define OP_EORB(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+#define OP_EORB(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
FLAG_N = FLAG_Z = REG_BA ^= OPER_8_##MODE(cpustate)
#else
-#define OP_EORB(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_Z = REG_BA ^= OPER_16_##MODE(cpustate); \
+#define OP_EORB(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REG_BA ^= OPER_16_##MODE(cpustate); \
FLAG_N = NFLAG_16(REG_BA)
#endif
/* M37710 Increment accumulator */
#undef OP_INC
#if FLAG_SET_M
-#define OP_INC() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_INC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(REG_A + 1)
#else
-#define OP_INC() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_A = MAKE_UINT_16(REG_A + 1); \
+#define OP_INC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_A = MAKE_UINT_16(REG_A + 1); \
FLAG_N = NFLAG_16(REG_A)
#endif
/* M37710 Increment B accumulator */
#undef OP_INCB
#if FLAG_SET_M
-#define OP_INCB() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_INCB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(REG_BA + 1)
#else
-#define OP_INCB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_BA = MAKE_UINT_16(REG_BA + 1); \
+#define OP_INCB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_BA = MAKE_UINT_16(REG_BA + 1); \
FLAG_N = NFLAG_16(REG_BA)
#endif
/* M37710 Increment operand */
#undef OP_INCM
#if FLAG_SET_M
-#define OP_INCM(MODE) \
- CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) + 1); \
+#define OP_INCM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) + 1); \
write_8_##MODE(DST, FLAG_Z)
#else
-#define OP_INCM(MODE) \
- CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) + 1); \
- FLAG_N = NFLAG_16(FLAG_Z); \
+#define OP_INCM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) + 1); \
+ FLAG_N = NFLAG_16(FLAG_Z); \
write_16_##MODE(DST, FLAG_Z)
#endif
/* M37710 Increment index register */
#undef OP_INCX
#if FLAG_SET_X
-#define OP_INCX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_INCX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_N = FLAG_Z = REG = MAKE_UINT_8(REG + 1)
#else
-#define OP_INCX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG = MAKE_UINT_16(REG + 1); \
+#define OP_INCX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = MAKE_UINT_16(REG + 1); \
FLAG_N = NFLAG_16(REG)
#endif
/* M37710 Jump Long */
#undef OP_JMLAI
-#define OP_JMLAI() \
- CLK(CLK_OP + CLK_AI + 1); \
+#define OP_JMLAI() \
+ CLK(CLK_OP + CLK_AI + 1); \
m37710i_jump_24(cpustate, read_24_A(OPER_16_IMM(cpustate)))
/* M37710 Jump */
#undef OP_JMP
-#define OP_JMP(MODE) \
- CLK(CLK_OP + CLK_##MODE); \
+#define OP_JMP(MODE) \
+ CLK(CLK_OP + CLK_##MODE); \
m37710i_jump_16(cpustate, EA_##MODE(cpustate))
/* M37710 Jump absolute indexed indirect */
#undef OP_JMPAXI
-#define OP_JMPAXI() \
- CLK(CLK_OP + CLK_AXI); \
+#define OP_JMPAXI() \
+ CLK(CLK_OP + CLK_AXI); \
m37710i_jump_16(cpustate, read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM(cpustate) + REG_X))))
/* M37710 Jump absolute long */
#undef OP_JMPAL
-#define OP_JMPAL() \
- CLK(CLK_OP + CLK_AL); \
+#define OP_JMPAL() \
+ CLK(CLK_OP + CLK_AL); \
m37710i_jump_24(cpustate, EA_AL(cpustate))
/* M37710 Jump to Subroutine Long */
#undef OP_JSL
-#define OP_JSL(MODE) \
- CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1); \
- DST = EA_##MODE(cpustate); \
- m37710i_push_8(cpustate, REG_PB>>16); \
- m37710i_push_16(cpustate, REG_PC); \
+#define OP_JSL(MODE) \
+ CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1); \
+ DST = EA_##MODE(cpustate); \
+ m37710i_push_8(cpustate, REG_PB>>16); \
+ m37710i_push_16(cpustate, REG_PC); \
m37710i_jump_24(cpustate, DST)
/* M37710 Jump to Subroutine */
#undef OP_JSR
-#define OP_JSR(MODE) \
- CLK(CLK_OP + CLK_W16 + CLK_##MODE); \
- DST = EA_##MODE(cpustate); \
- m37710i_push_16(cpustate, REG_PC); \
+#define OP_JSR(MODE) \
+ CLK(CLK_OP + CLK_W16 + CLK_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ m37710i_push_16(cpustate, REG_PC); \
m37710i_jump_16(cpustate, DST)
/* M37710 Jump to Subroutine */
#undef OP_JSRAXI
-#define OP_JSRAXI() \
- CLK(CLK_OP + CLK_W16 + CLK_AXI); \
+#define OP_JSRAXI() \
+ CLK(CLK_OP + CLK_W16 + CLK_AXI); \
DST = read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM(cpustate) + REG_X))); \
- m37710i_push_16(cpustate, REG_PC); \
+ m37710i_push_16(cpustate, REG_PC); \
m37710i_jump_16(cpustate, DST)
/* M37710 Load accumulator with operand */
#undef OP_LDA
#if FLAG_SET_M
-#define OP_LDA(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+#define OP_LDA(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
FLAG_N = FLAG_Z = REG_A = OPER_8_##MODE(cpustate)
#else
-#define OP_LDA(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_Z = REG_A = OPER_16_##MODE(cpustate); \
+#define OP_LDA(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REG_A = OPER_16_##MODE(cpustate); \
FLAG_N = NFLAG_16(REG_A)
#endif
/* M37710 Load B accumulator with operand */
#undef OP_LDB
#if FLAG_SET_M
-#define OP_LDB(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+#define OP_LDB(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
FLAG_N = FLAG_Z = REG_BA = OPER_8_##MODE(cpustate)
#else
-#define OP_LDB(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_Z = REG_BA = OPER_16_##MODE(cpustate); \
+#define OP_LDB(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REG_BA = OPER_16_##MODE(cpustate); \
FLAG_N = NFLAG_16(REG_BA)
#endif
/* M37710 Load memory with operand */
#undef OP_LDM
#if FLAG_SET_M
-#define OP_LDM(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
- REG_IM2 = EA_##MODE(cpustate); \
- REG_IM = read_8_NORM(REG_PB|REG_PC); \
- REG_PC++; \
+#define OP_LDM(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ REG_IM2 = EA_##MODE(cpustate); \
+ REG_IM = read_8_NORM(REG_PB|REG_PC); \
+ REG_PC++; \
write_8_##MODE(REG_IM2, REG_IM)
#else
-#define OP_LDM(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- REG_IM2 = EA_##MODE(cpustate); \
- REG_IM = read_16_NORM(REG_PB|REG_PC); \
- REG_PC+=2; \
+#define OP_LDM(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ REG_IM2 = EA_##MODE(cpustate); \
+ REG_IM = read_16_NORM(REG_PB|REG_PC); \
+ REG_PC+=2; \
write_16_##MODE(REG_IM2, REG_IM)
#endif
/* M37710 Branch if bits set */
#undef OP_BBS
#if FLAG_SET_M
-#define OP_BBS(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
- REG_IM2 = read_8_NORM(EA_##MODE(cpustate)); \
- REG_IM = read_8_NORM(REG_PB | REG_PC); \
- REG_PC++; \
- DST = OPER_8_IMM(cpustate); \
- if ((REG_IM2 & REG_IM) == REG_IM) \
- { \
- CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
- m37710i_branch_8(cpustate, DST); \
- BREAKOUT; \
+#define OP_BBS(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ REG_IM2 = read_8_NORM(EA_##MODE(cpustate)); \
+ REG_IM = read_8_NORM(REG_PB | REG_PC); \
+ REG_PC++; \
+ DST = OPER_8_IMM(cpustate); \
+ if ((REG_IM2 & REG_IM) == REG_IM) \
+ { \
+ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
+ m37710i_branch_8(cpustate, DST); \
+ BREAKOUT; \
}
#else
-#define OP_BBS(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- REG_IM2 = read_16_NORM(EA_##MODE(cpustate)); \
- REG_IM = read_16_NORM(REG_PB | REG_PC); \
- REG_PC++; \
- REG_PC++; \
- DST = OPER_8_IMM(cpustate); \
- if ((REG_IM2 & REG_IM) == REG_IM) \
- { \
- CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
- m37710i_branch_8(cpustate, DST); \
- BREAKOUT; \
+#define OP_BBS(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ REG_IM2 = read_16_NORM(EA_##MODE(cpustate)); \
+ REG_IM = read_16_NORM(REG_PB | REG_PC); \
+ REG_PC++; \
+ REG_PC++; \
+ DST = OPER_8_IMM(cpustate); \
+ if ((REG_IM2 & REG_IM) == REG_IM) \
+ { \
+ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
+ m37710i_branch_8(cpustate, DST); \
+ BREAKOUT; \
}
#endif
/* M37710 Branch if bits clear */
#undef OP_BBC
#if FLAG_SET_M
-#define OP_BBC(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
- REG_IM2 = read_8_NORM(EA_##MODE(cpustate)); \
- REG_IM = read_8_NORM(REG_PB | REG_PC); \
- REG_PC++; \
- DST = OPER_8_IMM(cpustate); \
- if ((REG_IM2 & REG_IM) == 0) \
- { \
- CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
- m37710i_branch_8(cpustate, DST); \
- BREAKOUT; \
+#define OP_BBC(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ REG_IM2 = read_8_NORM(EA_##MODE(cpustate)); \
+ REG_IM = read_8_NORM(REG_PB | REG_PC); \
+ REG_PC++; \
+ DST = OPER_8_IMM(cpustate); \
+ if ((REG_IM2 & REG_IM) == 0) \
+ { \
+ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
+ m37710i_branch_8(cpustate, DST); \
+ BREAKOUT; \
}
#else
-#define OP_BBC(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- REG_IM2 = read_16_NORM(EA_##MODE(cpustate)); \
- REG_IM = read_16_NORM(REG_PB | REG_PC); \
- REG_PC++; \
- REG_PC++; \
- DST = OPER_8_IMM(cpustate); \
- if ((REG_IM2 & REG_IM) == 0) \
- { \
- CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
- m37710i_branch_8(cpustate, DST); \
- BREAKOUT; \
+#define OP_BBC(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ REG_IM2 = read_16_NORM(EA_##MODE(cpustate)); \
+ REG_IM = read_16_NORM(REG_PB | REG_PC); \
+ REG_PC++; \
+ REG_PC++; \
+ DST = OPER_8_IMM(cpustate); \
+ if ((REG_IM2 & REG_IM) == 0) \
+ { \
+ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
+ m37710i_branch_8(cpustate, DST); \
+ BREAKOUT; \
}
#endif
/* M37710 Swap accumulators */
#undef OP_XAB
#if FLAG_SET_M
-#define OP_XAB() \
- CLK(6); \
- DST = REG_A; \
- FLAG_N = FLAG_Z = REG_A = REG_BA; \
+#define OP_XAB() \
+ CLK(6); \
+ DST = REG_A; \
+ FLAG_N = FLAG_Z = REG_A = REG_BA; \
REG_BA = DST;
#else
-#define OP_XAB() \
- CLK(6); \
- DST = REG_A; \
- FLAG_Z = REG_A = REG_BA; \
- FLAG_N = NFLAG_16(REG_A); \
+#define OP_XAB() \
+ CLK(6); \
+ DST = REG_A; \
+ FLAG_Z = REG_A = REG_BA; \
+ FLAG_N = NFLAG_16(REG_A); \
REG_BA = DST;
#endif
/* M37710 Load index register with operand */
#undef OP_LDX
#if FLAG_SET_X
-#define OP_LDX(REG, MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+#define OP_LDX(REG, MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
FLAG_N = FLAG_Z = REG = OPER_8_##MODE(cpustate)
#else
-#define OP_LDX(REG, MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_Z = REG = OPER_16_##MODE(cpustate); \
+#define OP_LDX(REG, MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REG = OPER_16_##MODE(cpustate); \
FLAG_N = NFLAG_16(REG)
#endif
/* M37710 Logical Shift Right accumulator */
#undef OP_LSR
#if FLAG_SET_M
-#define OP_LSR() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_N = 0; \
- FLAG_C = REG_A << 8; \
+#define OP_LSR() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_N = 0; \
+ FLAG_C = REG_A << 8; \
FLAG_Z = REG_A >>= 1
#else
-#define OP_LSR() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_N = 0; \
- FLAG_C = REG_A << 8; \
+#define OP_LSR() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_N = 0; \
+ FLAG_C = REG_A << 8; \
FLAG_Z = REG_A >>= 1
#endif
/* M37710 Logical Shift Right B accumulator */
#undef OP_LSRB
#if FLAG_SET_M
-#define OP_LSRB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_N = 0; \
- FLAG_C = REG_BA << 8; \
+#define OP_LSRB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_N = 0; \
+ FLAG_C = REG_BA << 8; \
FLAG_Z = REG_BA >>= 1
#else
-#define OP_LSRB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_N = 0; \
- FLAG_C = REG_BA << 8; \
+#define OP_LSRB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_N = 0; \
+ FLAG_C = REG_BA << 8; \
FLAG_Z = REG_BA >>= 1
#endif
/* M37710 Logical Shift Right operand */
#undef OP_LSRM
#if FLAG_SET_M
-#define OP_LSRM(MODE) \
- CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_N = 0; \
- FLAG_Z = read_8_##MODE(DST); \
- FLAG_C = FLAG_Z << 8; \
- FLAG_Z >>= 1; \
+#define OP_LSRM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_N = 0; \
+ FLAG_Z = read_8_##MODE(DST); \
+ FLAG_C = FLAG_Z << 8; \
+ FLAG_Z >>= 1; \
write_8_##MODE(DST, FLAG_Z)
#else
-#define OP_LSRM(MODE) \
- CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_N = 0; \
- FLAG_Z = read_16_##MODE(DST); \
- FLAG_C = FLAG_Z << 8; \
- FLAG_Z >>= 1; \
+#define OP_LSRM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_N = 0; \
+ FLAG_Z = read_16_##MODE(DST); \
+ FLAG_C = FLAG_Z << 8; \
+ FLAG_Z >>= 1; \
write_16_##MODE(DST, FLAG_Z)
#endif
/* M37710 Move Block Negative */
#undef OP_MVN
#if FLAG_SET_X
-#define OP_MVN() \
- DST = OPER_8_IMM(cpustate)<<16; \
- SRC = OPER_8_IMM(cpustate)<<16; \
- REG_DB = DST; \
- REG_A |= REG_B; \
- CLK(7); \
- if (REG_A > 0) \
- { \
- write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \
- REG_X = MAKE_UINT_8(REG_X+1); \
- REG_Y = MAKE_UINT_8(REG_Y+1); \
- REG_A--; \
+#define OP_MVN() \
+ DST = OPER_8_IMM(cpustate)<<16; \
+ SRC = OPER_8_IMM(cpustate)<<16; \
+ REG_DB = DST; \
+ REG_A |= REG_B; \
+ CLK(7); \
+ if (REG_A > 0) \
+ { \
+ write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \
+ REG_X = MAKE_UINT_8(REG_X+1); \
+ REG_Y = MAKE_UINT_8(REG_Y+1); \
+ REG_A--; \
if ((REG_A&0xffff) != 0) \
{\
REG_PC -= 3; \
@@ -1360,26 +1360,26 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
{ \
REG_A = 0xff; \
REG_B = 0xff00; \
- } \
+ } \
else \
- { \
- REG_A = 0xffff; \
- } \
+ { \
+ REG_A = 0xffff; \
+ } \
} \
}
#else
-#define OP_MVN() \
- DST = OPER_8_IMM(cpustate)<<16; \
- SRC = OPER_8_IMM(cpustate)<<16; \
- REG_DB = DST; \
- REG_A |= REG_B; \
- CLK(7); \
- if (REG_A > 0) \
- { \
- write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \
- REG_X = MAKE_UINT_16(REG_X+1); \
- REG_Y = MAKE_UINT_16(REG_Y+1); \
- REG_A--; \
+#define OP_MVN() \
+ DST = OPER_8_IMM(cpustate)<<16; \
+ SRC = OPER_8_IMM(cpustate)<<16; \
+ REG_DB = DST; \
+ REG_A |= REG_B; \
+ CLK(7); \
+ if (REG_A > 0) \
+ { \
+ write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \
+ REG_X = MAKE_UINT_16(REG_X+1); \
+ REG_Y = MAKE_UINT_16(REG_Y+1); \
+ REG_A--; \
if ((REG_A&0xffff) != 0) \
{\
REG_PC -= 3; \
@@ -1390,11 +1390,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
{ \
REG_A = 0xff; \
REG_B = 0xff00; \
- } \
+ } \
else \
- { \
- REG_A = 0xffff; \
- } \
+ { \
+ REG_A = 0xffff; \
+ } \
} \
}
#endif
@@ -1402,18 +1402,18 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
/* M37710 Move Block Positive */
#undef OP_MVP
#if FLAG_SET_X
-#define OP_MVP() \
- DST = OPER_8_IMM(cpustate)<<16; \
- SRC = OPER_8_IMM(cpustate)<<16; \
- REG_DB = DST; \
- REG_A |= REG_B; \
- CLK(7); \
- if (REG_A > 0) \
- { \
- write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \
- REG_X = MAKE_UINT_8(REG_X-1); \
- REG_Y = MAKE_UINT_8(REG_Y-1); \
- REG_A--; \
+#define OP_MVP() \
+ DST = OPER_8_IMM(cpustate)<<16; \
+ SRC = OPER_8_IMM(cpustate)<<16; \
+ REG_DB = DST; \
+ REG_A |= REG_B; \
+ CLK(7); \
+ if (REG_A > 0) \
+ { \
+ write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \
+ REG_X = MAKE_UINT_8(REG_X-1); \
+ REG_Y = MAKE_UINT_8(REG_Y-1); \
+ REG_A--; \
if ((REG_A&0xffff) != 0) \
{\
REG_PC -= 3; \
@@ -1424,26 +1424,26 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
{ \
REG_A = 0xff; \
REG_B = 0xff00; \
- } \
+ } \
else \
- { \
- REG_A = 0xffff; \
- } \
+ { \
+ REG_A = 0xffff; \
+ } \
} \
}
#else
-#define OP_MVP() \
- DST = OPER_8_IMM(cpustate)<<16; \
- SRC = OPER_8_IMM(cpustate)<<16; \
- REG_DB = DST; \
- REG_A |= REG_B; \
- CLK(7); \
- if (REG_A > 0) \
- { \
- write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \
- REG_X = MAKE_UINT_16(REG_X-1); \
- REG_Y = MAKE_UINT_16(REG_Y-1); \
- REG_A--; \
+#define OP_MVP() \
+ DST = OPER_8_IMM(cpustate)<<16; \
+ SRC = OPER_8_IMM(cpustate)<<16; \
+ REG_DB = DST; \
+ REG_A |= REG_B; \
+ CLK(7); \
+ if (REG_A > 0) \
+ { \
+ write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \
+ REG_X = MAKE_UINT_16(REG_X-1); \
+ REG_Y = MAKE_UINT_16(REG_Y-1); \
+ REG_A--; \
if ((REG_A&0xffff) != 0) \
{\
REG_PC -= 3; \
@@ -1454,396 +1454,396 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
{ \
REG_A = 0xff; \
REG_B = 0xff00; \
- } \
+ } \
else \
- { \
- REG_A = 0xffff; \
- } \
+ { \
+ REG_A = 0xffff; \
+ } \
} \
}
#endif
/* M37710 No Operation */
#undef OP_NOP
-#define OP_NOP() \
+#define OP_NOP() \
CLK(CLK_OP + CLK_IMPLIED)
/* M37710 Logical OR operand to accumulator */
#undef OP_ORA
#if FLAG_SET_M
-#define OP_ORA(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+#define OP_ORA(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
FLAG_N = FLAG_Z = REG_A |= OPER_8_ ## MODE(cpustate)
#else
-#define OP_ORA(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_Z = REG_A |= OPER_16_##MODE(cpustate); \
+#define OP_ORA(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REG_A |= OPER_16_##MODE(cpustate); \
FLAG_N = NFLAG_16(REG_A)
#endif
/* M37710 Logical OR operand to B accumulator */
#undef OP_ORB
#if FLAG_SET_M
-#define OP_ORB(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+#define OP_ORB(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
FLAG_N = FLAG_Z = REG_BA |= OPER_8_ ## MODE(cpustate)
#else
-#define OP_ORB(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- FLAG_Z = REG_BA |= OPER_16_##MODE(cpustate); \
+#define OP_ORB(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REG_BA |= OPER_16_##MODE(cpustate); \
FLAG_N = NFLAG_16(REG_BA)
#endif
/* M37710 Push Effective Address */
#undef OP_PEA
-#define OP_PEA() \
- CLK(CLK_OP + CLK_R16 + CLK_W16); \
+#define OP_PEA() \
+ CLK(CLK_OP + CLK_R16 + CLK_W16); \
m37710i_push_16(cpustate, OPER_16_IMM(cpustate))
/* M37710 Push Effective Indirect Address */
#undef OP_PEI
-#define OP_PEI() \
- CLK(CLK_OP + CLK_R16 + CLK_W16 + CLK_D); \
+#define OP_PEI() \
+ CLK(CLK_OP + CLK_R16 + CLK_W16 + CLK_D); \
m37710i_push_16(cpustate, EA_DI(cpustate))
/* M37710 Push Effective PC-Relative Address */
#undef OP_PER
-#define OP_PER() \
- CLK(CLK_OP + CLK_R16 + CLK_W16 + 1); \
- SRC = OPER_16_IMM(cpustate); \
+#define OP_PER() \
+ CLK(CLK_OP + CLK_R16 + CLK_W16 + 1); \
+ SRC = OPER_16_IMM(cpustate); \
m37710i_push_16(cpustate, REG_PC + SRC)
/* M37710 Push accumulator to the stack */
#undef OP_PHA
#if FLAG_SET_M
-#define OP_PHA() \
- CLK(CLK_OP + CLK_W8 + 1); \
+#define OP_PHA() \
+ CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(cpustate, REG_A)
#else
-#define OP_PHA() \
- CLK(CLK_OP + CLK_W16 + 1); \
+#define OP_PHA() \
+ CLK(CLK_OP + CLK_W16 + 1); \
m37710i_push_16(cpustate, REG_A)
#endif
/* M37710 Push B accumulator to the stack */
#undef OP_PHAB
#if FLAG_SET_M
-#define OP_PHAB() \
- CLK(CLK_OP + CLK_W8 + 1); \
+#define OP_PHAB() \
+ CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(cpustate, REG_BA)
#else
-#define OP_PHAB() \
- CLK(CLK_OP + CLK_W16 + 1); \
+#define OP_PHAB() \
+ CLK(CLK_OP + CLK_W16 + 1); \
m37710i_push_16(cpustate, REG_BA)
#endif
/* M37710 Push index register to the stack */
#undef OP_PHX
#if FLAG_SET_X
-#define OP_PHX(REG) \
- CLK(CLK_OP + CLK_W8 + 1); \
+#define OP_PHX(REG) \
+ CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(cpustate, REG)
#else
-#define OP_PHX(REG) \
- CLK(CLK_OP + CLK_W16 + 1); \
+#define OP_PHX(REG) \
+ CLK(CLK_OP + CLK_W16 + 1); \
m37710i_push_16(cpustate, REG)
#endif
/* M37710 Push data bank register */
#undef OP_PHT
-#define OP_PHT() \
- CLK(CLK_OP + CLK_W8 + 1); \
+#define OP_PHT() \
+ CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(cpustate, REG_DB>>16)
/* M37710 Push direct register */
#undef OP_PHD
-#define OP_PHD() \
- CLK(CLK_OP + CLK_W16 + 1); \
+#define OP_PHD() \
+ CLK(CLK_OP + CLK_W16 + 1); \
m37710i_push_16(cpustate, REG_D)
/* M37710 Push program bank register */
#undef OP_PHK
-#define OP_PHK() \
- CLK(CLK_OP + CLK_W8 + 1); \
+#define OP_PHK() \
+ CLK(CLK_OP + CLK_W8 + 1); \
m37710i_push_8(cpustate, REG_PB>>16)
/* M37710 Push the Processor Status Register to the stack */
#undef OP_PHP
-#define OP_PHP() \
- CLK(CLK_OP + CLK_W8 + 1); \
- m37710i_push_8(cpustate, cpustate->ipl); \
+#define OP_PHP() \
+ CLK(CLK_OP + CLK_W8 + 1); \
+ m37710i_push_8(cpustate, cpustate->ipl); \
m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate))
/* M37710 Pull accumulator from the stack */
#undef OP_PLA
#if FLAG_SET_M
-#define OP_PLA() \
- CLK(CLK_OP + CLK_R8 + 2); \
+#define OP_PLA() \
+ CLK(CLK_OP + CLK_R8 + 2); \
FLAG_N = FLAG_Z = REG_A = m37710i_pull_8(cpustate)
#else
-#define OP_PLA() \
- CLK(CLK_OP + CLK_R16 + 2); \
- FLAG_Z = REG_A = m37710i_pull_16(cpustate); \
+#define OP_PLA() \
+ CLK(CLK_OP + CLK_R16 + 2); \
+ FLAG_Z = REG_A = m37710i_pull_16(cpustate); \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Pull B accumulator from the stack */
#undef OP_PLAB
#if FLAG_SET_M
-#define OP_PLAB() \
- CLK(CLK_OP + CLK_R8 + 2); \
+#define OP_PLAB() \
+ CLK(CLK_OP + CLK_R8 + 2); \
FLAG_N = FLAG_Z = REG_BA = m37710i_pull_8(cpustate)
#else
-#define OP_PLAB() \
- CLK(CLK_OP + CLK_R16 + 2); \
- FLAG_Z = REG_BA = m37710i_pull_16(cpustate); \
+#define OP_PLAB() \
+ CLK(CLK_OP + CLK_R16 + 2); \
+ FLAG_Z = REG_BA = m37710i_pull_16(cpustate); \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Pull index register from the stack */
#undef OP_PLX
#if FLAG_SET_X
-#define OP_PLX(REG) \
- CLK(CLK_OP + CLK_R8 + 2); \
+#define OP_PLX(REG) \
+ CLK(CLK_OP + CLK_R8 + 2); \
FLAG_N = FLAG_Z = REG = m37710i_pull_8(cpustate)
#else
-#define OP_PLX(REG) \
- CLK(CLK_OP + CLK_R16 + 2); \
- FLAG_Z = REG = m37710i_pull_16(cpustate); \
+#define OP_PLX(REG) \
+ CLK(CLK_OP + CLK_R16 + 2); \
+ FLAG_Z = REG = m37710i_pull_16(cpustate); \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Pull data bank register */
#undef OP_PLT
-#define OP_PLT() \
- CLK(CLK_OP + CLK_R8 + 2); \
- FLAG_N = FLAG_Z = m37710i_pull_8(cpustate); \
+#define OP_PLT() \
+ CLK(CLK_OP + CLK_R8 + 2); \
+ FLAG_N = FLAG_Z = m37710i_pull_8(cpustate); \
REG_DB = FLAG_Z << 16
/* M37710 Pull direct register */
#undef OP_PLD
-#define OP_PLD() \
- CLK(CLK_OP + CLK_R16 + 2); \
+#define OP_PLD() \
+ CLK(CLK_OP + CLK_R16 + 2); \
REG_D = m37710i_pull_16(cpustate)
/* M37710 Pull the Processor Status Register from the stack */
#undef OP_PLP
-#define OP_PLP() \
- CLK(CLK_OP + CLK_R8 + 2); \
- m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); \
- m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); \
+#define OP_PLP() \
+ CLK(CLK_OP + CLK_R8 + 2); \
+ m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); \
+ m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); \
m37710i_update_irqs(cpustate)
/* M37710 Reset Program status word */
#undef OP_REP
-#define OP_REP() \
- CLK(CLK_OP + CLK_R8 + 1); \
- m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) & ~OPER_8_IMM(cpustate)); \
+#define OP_REP() \
+ CLK(CLK_OP + CLK_R8 + 1); \
+ m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) & ~OPER_8_IMM(cpustate)); \
m37710i_update_irqs(cpustate)
/* M37710 Clear "M" status bit */
#undef OP_CLM
-#define OP_CLM() \
- CLK(CLK_OP + CLK_R8 + 1); \
+#define OP_CLM() \
+ CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) & ~FLAGPOS_M)
/* M37710 Rotate Left the accumulator */
#undef OP_ROL
#if FLAG_SET_M
-#define OP_ROL() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_C = (REG_A<<1) | CFLAG_AS_1(); \
+#define OP_ROL() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = (REG_A<<1) | CFLAG_AS_1(); \
FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C)
#else
-#define OP_ROL() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_C = (REG_A<<1) | CFLAG_AS_1(); \
- FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(FLAG_C); \
+#define OP_ROL() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = (REG_A<<1) | CFLAG_AS_1(); \
+ FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
FLAG_C = CFLAG_16(FLAG_C)
#endif
/* M37710 Rotate Left the B accumulator */
#undef OP_ROLB
#if FLAG_SET_M
-#define OP_ROLB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_C = (REG_BA<<1) | CFLAG_AS_1(); \
+#define OP_ROLB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = (REG_BA<<1) | CFLAG_AS_1(); \
FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C)
#else
-#define OP_ROLB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_C = (REG_BA<<1) | CFLAG_AS_1(); \
- FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(FLAG_C); \
+#define OP_ROLB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = (REG_BA<<1) | CFLAG_AS_1(); \
+ FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
FLAG_C = CFLAG_16(FLAG_C)
#endif
/* M37710 Rotate Left the accumulator by a specified amount */
#undef OP_RLA
#if FLAG_SET_M
-#define OP_RLA(MODE) \
+#define OP_RLA(MODE) \
{ int cnt = OPER_8_##MODE(cpustate); while (cnt > 0) { CLK(6); REG_A=((REG_A<<1)|(REG_A>>7&1))&0xff; cnt--; } }
#else
-#define OP_RLA(MODE) \
+#define OP_RLA(MODE) \
{ int cnt = OPER_16_##MODE(cpustate); while (cnt > 0) { CLK(6); REG_A=((REG_A<<1)|(REG_A>>15&1))&0xffff; cnt--; } }
#endif
/* M37710 Rotate Left an operand */
#undef OP_ROLM
#if FLAG_SET_M
-#define OP_ROLM(MODE) \
- CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_C = (read_8_##MODE(DST)<<1) | CFLAG_AS_1(); \
- FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
+#define OP_ROLM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_C = (read_8_##MODE(DST)<<1) | CFLAG_AS_1(); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
write_8_##MODE(DST, FLAG_Z)
#else
-#define OP_ROLM(MODE) \
- CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_C = (read_16_##MODE(DST)<<1) | CFLAG_AS_1(); \
- FLAG_Z = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(FLAG_C); \
- FLAG_C = CFLAG_16(FLAG_C); \
+#define OP_ROLM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_C = (read_16_##MODE(DST)<<1) | CFLAG_AS_1(); \
+ FLAG_Z = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
+ FLAG_C = CFLAG_16(FLAG_C); \
write_16_##MODE(DST, FLAG_Z)
#endif
/* M37710 Rotate Right the accumulator */
#undef OP_ROR
#if FLAG_SET_M
-#define OP_ROR() \
- CLK(CLK_OP + CLK_IMPLIED); \
- REG_A |= FLAG_C & 0x100; \
- FLAG_C = REG_A << 8; \
+#define OP_ROR() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REG_A |= FLAG_C & 0x100; \
+ FLAG_C = REG_A << 8; \
FLAG_N = FLAG_Z = REG_A >>= 1
#else
-#define OP_ROR() \
- CLK(CLK_OP + CLK_IMPLIED); \
- REG_A |= (FLAG_C<<8) & 0x10000; \
- FLAG_C = REG_A << 8; \
- FLAG_Z = REG_A >>= 1; \
+#define OP_ROR() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REG_A |= (FLAG_C<<8) & 0x10000; \
+ FLAG_C = REG_A << 8; \
+ FLAG_Z = REG_A >>= 1; \
FLAG_N = NFLAG_16(REG_A)
#endif
/* M37710 Rotate Right the B accumulator */
#undef OP_RORB
#if FLAG_SET_M
-#define OP_RORB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- REG_BA |= FLAG_C & 0x100; \
- FLAG_C = REG_BA << 8; \
+#define OP_RORB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REG_BA |= FLAG_C & 0x100; \
+ FLAG_C = REG_BA << 8; \
FLAG_N = FLAG_Z = REG_BA >>= 1
#else
-#define OP_RORB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- REG_BA |= (FLAG_C<<8) & 0x10000; \
- FLAG_C = REG_BA << 8; \
- FLAG_Z = REG_BA >>= 1; \
+#define OP_RORB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REG_BA |= (FLAG_C<<8) & 0x10000; \
+ FLAG_C = REG_BA << 8; \
+ FLAG_Z = REG_BA >>= 1; \
FLAG_N = NFLAG_16(REG_BA)
#endif
/* M37710 Rotate Right an operand */
#undef OP_RORM
#if FLAG_SET_M
-#define OP_RORM(MODE) \
- CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_Z = read_8_##MODE(DST) | (FLAG_C & 0x100); \
- FLAG_C = FLAG_Z << 8; \
- FLAG_N = FLAG_Z >>= 1; \
+#define OP_RORM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_Z = read_8_##MODE(DST) | (FLAG_C & 0x100); \
+ FLAG_C = FLAG_Z << 8; \
+ FLAG_N = FLAG_Z >>= 1; \
write_8_##MODE(DST, FLAG_Z)
#else
-#define OP_RORM(MODE) \
- CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- FLAG_Z = read_16_##MODE(DST) | ((FLAG_C<<8) & 0x10000); \
- FLAG_C = FLAG_Z << 8; \
- FLAG_Z >>= 1; \
- FLAG_N = NFLAG_16(FLAG_Z); \
+#define OP_RORM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ FLAG_Z = read_16_##MODE(DST) | ((FLAG_C<<8) & 0x10000); \
+ FLAG_C = FLAG_Z << 8; \
+ FLAG_Z >>= 1; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
write_16_##MODE(DST, FLAG_Z)
#endif
/* M37710 Return from Interrupt */
#undef OP_RTI
-#define OP_RTI() \
- CLK(8); \
- m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); \
- m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); \
- m37710i_jump_16(cpustate, m37710i_pull_16(cpustate)); \
- REG_PB = m37710i_pull_8(cpustate) << 16; \
- m37710i_jumping(REG_PB | REG_PC); \
+#define OP_RTI() \
+ CLK(8); \
+ m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); \
+ m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); \
+ m37710i_jump_16(cpustate, m37710i_pull_16(cpustate)); \
+ REG_PB = m37710i_pull_8(cpustate) << 16; \
+ m37710i_jumping(REG_PB | REG_PC); \
m37710i_update_irqs(cpustate)
/* M37710 Return from Subroutine Long */
#undef OP_RTL
-#define OP_RTL() \
- CLK(6); \
+#define OP_RTL() \
+ CLK(6); \
m37710i_jump_24(cpustate, m37710i_pull_24(cpustate))
/* M37710 Return from Subroutine */
#undef OP_RTS
-#define OP_RTS() \
- CLK(6); \
- DST = m37710i_pull_16(cpustate); \
+#define OP_RTS() \
+ CLK(6); \
+ DST = m37710i_pull_16(cpustate); \
m37710i_jump_16(cpustate, DST)
/* M37710 Subtract with Carry */
/* Unusual behavior: C flag is inverted */
#undef OP_SBC
#if FLAG_SET_M
-#define OP_SBC(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
- SRC = OPER_8_##MODE(cpustate); \
- FLAG_C = ~FLAG_C; \
- if(!FLAG_D) \
- { \
- FLAG_C = REG_A - SRC - CFLAG_AS_1(); \
- FLAG_V = VFLAG_SUB_8(SRC, REG_A, FLAG_C); \
- FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C); \
- FLAG_C = ~FLAG_C; \
- BREAKOUT; \
- } \
- DST = CFLAG_AS_1(); \
- FLAG_C = REG_A - SRC - DST; \
- FLAG_V = VFLAG_SUB_8(SRC, REG_A, FLAG_C); \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C-=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C-=0x60; \
- FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C); \
+#define OP_SBC(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ SRC = OPER_8_##MODE(cpustate); \
+ FLAG_C = ~FLAG_C; \
+ if(!FLAG_D) \
+ { \
+ FLAG_C = REG_A - SRC - CFLAG_AS_1(); \
+ FLAG_V = VFLAG_SUB_8(SRC, REG_A, FLAG_C); \
+ FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C); \
+ FLAG_C = ~FLAG_C; \
+ BREAKOUT; \
+ } \
+ DST = CFLAG_AS_1(); \
+ FLAG_C = REG_A - SRC - DST; \
+ FLAG_V = VFLAG_SUB_8(SRC, REG_A, FLAG_C); \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C-=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C-=0x60; \
+ FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C); \
FLAG_C = ~FLAG_C
#else
-#define OP_SBC(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- SRC = OPER_16_##MODE(cpustate); \
- FLAG_C = ~FLAG_C; \
- if(!FLAG_D) \
- { \
- FLAG_C = REG_A - SRC - CFLAG_AS_1(); \
- FLAG_V = VFLAG_SUB_16(SRC, REG_A, FLAG_C); \
- FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(REG_A); \
- FLAG_C = ~CFLAG_16(FLAG_C); \
- BREAKOUT; \
- } \
- DST = CFLAG_AS_1(); \
- FLAG_C = MAKE_UINT_8(REG_A) - MAKE_UINT_8(SRC) - DST; \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C-=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C-=0x60; \
- FLAG_Z = MAKE_UINT_8(FLAG_C); \
- DST = CFLAG_AS_1(); \
- FLAG_C = MAKE_UINT_8(REG_A>>8) - MAKE_UINT_8(SRC>>8) - DST; \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C-=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C-=0x60; \
- FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \
- FLAG_N = NFLAG_16(FLAG_Z); \
- FLAG_V = VFLAG_SUB_16(SRC, REG_A, FLAG_Z); \
- REG_A = FLAG_Z; \
+#define OP_SBC(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ SRC = OPER_16_##MODE(cpustate); \
+ FLAG_C = ~FLAG_C; \
+ if(!FLAG_D) \
+ { \
+ FLAG_C = REG_A - SRC - CFLAG_AS_1(); \
+ FLAG_V = VFLAG_SUB_16(SRC, REG_A, FLAG_C); \
+ FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(REG_A); \
+ FLAG_C = ~CFLAG_16(FLAG_C); \
+ BREAKOUT; \
+ } \
+ DST = CFLAG_AS_1(); \
+ FLAG_C = MAKE_UINT_8(REG_A) - MAKE_UINT_8(SRC) - DST; \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C-=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C-=0x60; \
+ FLAG_Z = MAKE_UINT_8(FLAG_C); \
+ DST = CFLAG_AS_1(); \
+ FLAG_C = MAKE_UINT_8(REG_A>>8) - MAKE_UINT_8(SRC>>8) - DST; \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C-=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C-=0x60; \
+ FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ FLAG_V = VFLAG_SUB_16(SRC, REG_A, FLAG_Z); \
+ REG_A = FLAG_Z; \
FLAG_C = ~FLAG_C
#endif
@@ -1851,151 +1851,151 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
/* Unusual behavior: C flag is inverted */
#undef OP_SBCB
#if FLAG_SET_M
-#define OP_SBCB(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
- SRC = OPER_8_##MODE(cpustate); \
- FLAG_C = ~FLAG_C; \
- if(!FLAG_D) \
- { \
- FLAG_C = REG_BA - SRC - CFLAG_AS_1(); \
- FLAG_V = VFLAG_SUB_8(SRC, REG_BA, FLAG_C); \
- FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C); \
- FLAG_C = ~FLAG_C; \
- BREAKOUT; \
- } \
- DST = CFLAG_AS_1(); \
- FLAG_C = REG_BA - SRC - DST; \
- FLAG_V = VFLAG_SUB_8(SRC, REG_BA, FLAG_C); \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C-=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C-=0x60; \
- FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C); \
+#define OP_SBCB(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ SRC = OPER_8_##MODE(cpustate); \
+ FLAG_C = ~FLAG_C; \
+ if(!FLAG_D) \
+ { \
+ FLAG_C = REG_BA - SRC - CFLAG_AS_1(); \
+ FLAG_V = VFLAG_SUB_8(SRC, REG_BA, FLAG_C); \
+ FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C); \
+ FLAG_C = ~FLAG_C; \
+ BREAKOUT; \
+ } \
+ DST = CFLAG_AS_1(); \
+ FLAG_C = REG_BA - SRC - DST; \
+ FLAG_V = VFLAG_SUB_8(SRC, REG_BA, FLAG_C); \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C-=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C-=0x60; \
+ FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C); \
FLAG_C = ~FLAG_C
#else
-#define OP_SBCB(MODE) \
- CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
- SRC = OPER_16_##MODE(cpustate); \
- FLAG_C = ~FLAG_C; \
- if(!FLAG_D) \
- { \
- FLAG_C = REG_BA - SRC - CFLAG_AS_1(); \
- FLAG_V = VFLAG_SUB_16(SRC, REG_BA, FLAG_C); \
- FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \
- FLAG_N = NFLAG_16(REG_BA); \
- FLAG_C = ~CFLAG_16(FLAG_C); \
- BREAKOUT; \
- } \
- DST = CFLAG_AS_1(); \
- FLAG_C = MAKE_UINT_8(REG_BA) - MAKE_UINT_8(SRC) - DST; \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C-=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C-=0x60; \
- FLAG_Z = MAKE_UINT_8(FLAG_C); \
- DST = CFLAG_AS_1(); \
- FLAG_C = MAKE_UINT_8(REG_A>>8) - MAKE_UINT_8(SRC>>8) - DST; \
- if((FLAG_C & 0xf) > 9) \
- FLAG_C-=6; \
- if((FLAG_C & 0xf0) > 0x90) \
- FLAG_C-=0x60; \
- FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \
- FLAG_N = NFLAG_16(FLAG_Z); \
- FLAG_V = VFLAG_SUB_16(SRC, REG_BA, FLAG_Z); \
- REG_BA = FLAG_Z; \
+#define OP_SBCB(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ SRC = OPER_16_##MODE(cpustate); \
+ FLAG_C = ~FLAG_C; \
+ if(!FLAG_D) \
+ { \
+ FLAG_C = REG_BA - SRC - CFLAG_AS_1(); \
+ FLAG_V = VFLAG_SUB_16(SRC, REG_BA, FLAG_C); \
+ FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(REG_BA); \
+ FLAG_C = ~CFLAG_16(FLAG_C); \
+ BREAKOUT; \
+ } \
+ DST = CFLAG_AS_1(); \
+ FLAG_C = MAKE_UINT_8(REG_BA) - MAKE_UINT_8(SRC) - DST; \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C-=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C-=0x60; \
+ FLAG_Z = MAKE_UINT_8(FLAG_C); \
+ DST = CFLAG_AS_1(); \
+ FLAG_C = MAKE_UINT_8(REG_A>>8) - MAKE_UINT_8(SRC>>8) - DST; \
+ if((FLAG_C & 0xf) > 9) \
+ FLAG_C-=6; \
+ if((FLAG_C & 0xf0) > 0x90) \
+ FLAG_C-=0x60; \
+ FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ FLAG_V = VFLAG_SUB_16(SRC, REG_BA, FLAG_Z); \
+ REG_BA = FLAG_Z; \
FLAG_C = ~FLAG_C
#endif
/* M37710 Set Carry flag */
#undef OP_SEC
-#define OP_SEC() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_SEC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
FLAG_C = CFLAG_SET
/* M37710 Set Interrupt Mask flag */
#undef OP_SEI
-#define OP_SEI() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_SEI() \
+ CLK(CLK_OP + CLK_IMPLIED); \
m37710i_set_flag_i(cpustate, IFLAG_SET)
/* M37710 Set Program status word */
#undef OP_SEP
-#define OP_SEP() \
- CLK(CLK_OP + CLK_R8 + 1); \
+#define OP_SEP() \
+ CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) | OPER_8_IMM(cpustate))
/* M37710 Set "M" status bit */
#undef OP_SEM
-#define OP_SEM() \
- CLK(CLK_OP + CLK_R8 + 1); \
+#define OP_SEM() \
+ CLK(CLK_OP + CLK_R8 + 1); \
m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) | FLAGPOS_M)
/* M37710 Store accumulator to memory */
#undef OP_STA
#if FLAG_SET_M
-#define OP_STA(MODE) \
- CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \
+#define OP_STA(MODE) \
+ CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \
write_8_##MODE(EA_##MODE(cpustate), REG_A)
#else
-#define OP_STA(MODE) \
- CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \
+#define OP_STA(MODE) \
+ CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \
write_16_##MODE(EA_##MODE(cpustate), REG_A)
#endif
/* M37710 Store B accumulator to memory */
#undef OP_STB
#if FLAG_SET_M
-#define OP_STB(MODE) \
- CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \
+#define OP_STB(MODE) \
+ CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \
write_8_##MODE(EA_##MODE(cpustate), REG_BA)
#else
-#define OP_STB(MODE) \
- CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \
+#define OP_STB(MODE) \
+ CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \
write_16_##MODE(EA_##MODE(cpustate), REG_BA)
#endif
/* M37710 Store index register to memory */
#undef OP_STX
#if FLAG_SET_X
-#define OP_STX(REG, MODE) \
- CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \
+#define OP_STX(REG, MODE) \
+ CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \
write_8_##MODE(EA_##MODE(cpustate), REG)
#else
-#define OP_STX(REG, MODE) \
- CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \
+#define OP_STX(REG, MODE) \
+ CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \
write_16_##MODE(EA_##MODE(cpustate), REG)
#endif
/* M37710 Stop the clock */
#undef OP_STP
-#define OP_STP() \
- USE_ALL_CLKS(); \
+#define OP_STP() \
+ USE_ALL_CLKS(); \
CPU_STOPPED |= STOP_LEVEL_STOP
/* M37710 Transfer accumulator to index */
#undef OP_TAX
#if FLAG_SET_M
#if FLAG_SET_X
-#define OP_TAX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG = REG_A; \
+#define OP_TAX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = REG_A; \
FLAG_N = NFLAG_8(FLAG_Z)
#else /* FLAG_SET_X */
-#define OP_TAX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG = REG_B | REG_A; \
+#define OP_TAX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = REG_B | REG_A; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif /* FLAG_SET_X */
#else /* FLAG_SET_M */
#if FLAG_SET_X
-#define OP_TAX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG = MAKE_UINT_8(REG_A); \
+#define OP_TAX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = MAKE_UINT_8(REG_A); \
FLAG_N = NFLAG_8(FLAG_Z)
#else /* FLAG_SET_X */
-#define OP_TAX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG = REG_A; \
+#define OP_TAX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = REG_A; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif /* FLAG_SET_X */
#endif /* FLAG_SET_M */
@@ -2005,26 +2005,26 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
#undef OP_TBX
#if FLAG_SET_M
#if FLAG_SET_X
-#define OP_TBX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG = REG_BA; \
+#define OP_TBX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = REG_BA; \
FLAG_N = NFLAG_8(FLAG_Z)
#else /* FLAG_SET_X */
-#define OP_TBX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG = REG_BB | REG_BA; \
+#define OP_TBX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = REG_BB | REG_BA; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif /* FLAG_SET_X */
#else /* FLAG_SET_M */
#if FLAG_SET_X
-#define OP_TBX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG = MAKE_UINT_8(REG_BA); \
+#define OP_TBX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = MAKE_UINT_8(REG_BA); \
FLAG_N = NFLAG_8(FLAG_Z)
#else /* FLAG_SET_X */
-#define OP_TBX(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG = REG_BA; \
+#define OP_TBX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = REG_BA; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif /* FLAG_SET_X */
#endif /* FLAG_SET_M */
@@ -2032,271 +2032,271 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
/* M37710 Transfer index to accumulator */
#undef OP_TXA
#if FLAG_SET_M
-#define OP_TXA(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_A = MAKE_UINT_8(REG); \
+#define OP_TXA(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_A = MAKE_UINT_8(REG); \
FLAG_N = NFLAG_8(FLAG_Z)
#else
-#define OP_TXA(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_A = REG; \
+#define OP_TXA(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_A = REG; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Transfer index to accumulator B */
#undef OP_TXB
#if FLAG_SET_M
-#define OP_TXB(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_BA = MAKE_UINT_8(REG); \
+#define OP_TXB(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_BA = MAKE_UINT_8(REG); \
FLAG_N = NFLAG_8(FLAG_Z)
#else
-#define OP_TXB(REG) \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_BA = REG; \
+#define OP_TXB(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_BA = REG; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Transfer accumulator to direct register */
#undef OP_TAD
#if FLAG_SET_M
-#define OP_TAD() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_TAD() \
+ CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_A | REG_B
#else
-#define OP_TAD() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_TAD() \
+ CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_A
#endif
/* M37710 Transfer accumulator B to direct register */
#undef OP_TBD
#if FLAG_SET_M
-#define OP_TBD() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_TBD() \
+ CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_BA | REG_BB
#else
-#define OP_TBD() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_TBD() \
+ CLK(CLK_OP + CLK_IMPLIED); \
REG_D = REG_BA
#endif
/* M37710 Transfer direct register to accumulator */
#undef OP_TDA
#if FLAG_SET_M
-#define OP_TDA() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_D; \
- FLAG_N = NFLAG_16(FLAG_Z); \
- REG_A = MAKE_UINT_8(REG_D); \
+#define OP_TDA() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_D; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ REG_A = MAKE_UINT_8(REG_D); \
REG_B = REG_D & 0xff00
#else
-#define OP_TDA() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_A = REG_D; \
+#define OP_TDA() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_A = REG_D; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Transfer direct register to accumulator B */
#undef OP_TDB
#if FLAG_SET_M
-#define OP_TDB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_D; \
- FLAG_N = NFLAG_16(FLAG_Z); \
- REG_BA = MAKE_UINT_8(REG_D); \
+#define OP_TDB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_D; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ REG_BA = MAKE_UINT_8(REG_D); \
REG_BB = REG_D & 0xff00
#else
-#define OP_TDB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_BA = REG_D; \
+#define OP_TDB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_BA = REG_D; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Transfer accumulator to stack pointer */
#undef OP_TAS
#if FLAG_SET_M
-#define OP_TAS() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_TAS() \
+ CLK(CLK_OP + CLK_IMPLIED); \
REG_S = REG_A | REG_B
#else
-#define OP_TAS() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_TAS() \
+ CLK(CLK_OP + CLK_IMPLIED); \
REG_S = REG_A
#endif
/* M37710 Transfer accumulator B to stack pointer */
#undef OP_TBS
#if FLAG_SET_M
-#define OP_TBS() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_TBS() \
+ CLK(CLK_OP + CLK_IMPLIED); \
REG_S = REG_BA | REG_BB
#else
-#define OP_TBS() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_TBS() \
+ CLK(CLK_OP + CLK_IMPLIED); \
REG_S = REG_BA
#endif
/* M37710 Transfer stack pointer to accumulator */
#undef OP_TSA
#if FLAG_SET_M
-#define OP_TSA() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_S; \
- FLAG_N = NFLAG_16(FLAG_Z); \
- REG_A = MAKE_UINT_8(REG_S); \
+#define OP_TSA() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_S; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ REG_A = MAKE_UINT_8(REG_S); \
REG_B = REG_S & 0xff00
#else
-#define OP_TSA() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_A = REG_S; \
+#define OP_TSA() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_A = REG_S; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Transfer stack pointer to accumulator B */
#undef OP_TSB
#if FLAG_SET_M
-#define OP_TSB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_S; \
- FLAG_N = NFLAG_16(FLAG_Z); \
- REG_BA = MAKE_UINT_8(REG_S); \
+#define OP_TSB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_S; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ REG_BA = MAKE_UINT_8(REG_S); \
REG_BB = REG_S & 0xff00
#else
-#define OP_TSB() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_BA = REG_S; \
+#define OP_TSB() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_BA = REG_S; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Transfer stack pointer to X */
#undef OP_TSX
#if FLAG_SET_X
-#define OP_TSX() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_X = MAKE_UINT_8(REG_S); \
+#define OP_TSX() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_X = MAKE_UINT_8(REG_S); \
FLAG_N = NFLAG_8(FLAG_Z)
#else
-#define OP_TSX() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_X = REG_S; \
+#define OP_TSX() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_X = REG_S; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Transfer X to stack pointer */
#undef OP_TXS
#if FLAG_SET_X
-#define OP_TXS() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_TXS() \
+ CLK(CLK_OP + CLK_IMPLIED); \
REG_S = MAKE_UINT_8(REG_X)
#else
-#define OP_TXS() \
- CLK(CLK_OP + CLK_IMPLIED); \
+#define OP_TXS() \
+ CLK(CLK_OP + CLK_IMPLIED); \
REG_S = REG_X
#endif
/* M37710 Transfer X to Y */
#undef OP_TXY
#if FLAG_SET_X
-#define OP_TXY() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_Y = REG_X; \
+#define OP_TXY() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_Y = REG_X; \
FLAG_N = NFLAG_8(FLAG_Z)
#else
-#define OP_TXY() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_Y = REG_X; \
+#define OP_TXY() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_Y = REG_X; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 Transfer Y to X */
#undef OP_TYX
#if FLAG_SET_X
-#define OP_TYX() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_X = REG_Y; \
+#define OP_TYX() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_X = REG_Y; \
FLAG_N = NFLAG_8(FLAG_Z)
#else
-#define OP_TYX() \
- CLK(CLK_OP + CLK_IMPLIED); \
- FLAG_Z = REG_X = REG_Y; \
+#define OP_TYX() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG_X = REG_Y; \
FLAG_N = NFLAG_16(FLAG_Z)
#endif
/* M37710 clear bit */
#undef OP_CLB
#if FLAG_SET_M
-#define OP_CLB(MODE) \
- CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- REG_IM = read_8_##MODE(DST); \
- REG_IM2 = read_8_NORM(REG_PB | REG_PC); \
- REG_PC++; \
+#define OP_CLB(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ REG_IM = read_8_##MODE(DST); \
+ REG_IM2 = read_8_NORM(REG_PB | REG_PC); \
+ REG_PC++; \
write_8_##MODE(DST, REG_IM & ~REG_IM2);
#else
-#define OP_CLB(MODE) \
- CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- REG_IM = read_16_##MODE(DST); \
- REG_IM2 = read_16_NORM(REG_PB | REG_PC); \
- REG_PC+=2; \
+#define OP_CLB(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ REG_IM = read_16_##MODE(DST); \
+ REG_IM2 = read_16_NORM(REG_PB | REG_PC); \
+ REG_PC+=2; \
write_16_##MODE(DST, REG_IM & ~REG_IM2);
#endif
/* M37710 set bit */
#undef OP_SEB
#if FLAG_SET_M
-#define OP_SEB(MODE) \
- CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- REG_IM = read_8_##MODE(DST); \
- REG_IM2 = read_8_NORM(REG_PB | REG_PC); \
- REG_PC++; \
+#define OP_SEB(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ REG_IM = read_8_##MODE(DST); \
+ REG_IM2 = read_8_NORM(REG_PB | REG_PC); \
+ REG_PC++; \
write_8_##MODE(DST, REG_IM | REG_IM2);
#else
-#define OP_SEB(MODE) \
- CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
- DST = EA_##MODE(cpustate); \
- REG_IM = read_16_##MODE(DST); \
- REG_IM2 = read_16_NORM(REG_PB | REG_PC); \
- REG_PC+=2; \
+#define OP_SEB(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(cpustate); \
+ REG_IM = read_16_##MODE(DST); \
+ REG_IM2 = read_16_NORM(REG_PB | REG_PC); \
+ REG_PC+=2; \
write_16_##MODE(DST, REG_IM | REG_IM2);
#endif
/* M37710 Wait for interrupt */
#undef OP_WAI
-#define OP_WAI() \
- USE_ALL_CLKS(); \
+#define OP_WAI() \
+ USE_ALL_CLKS(); \
CPU_STOPPED |= STOP_LEVEL_WAI
/* M37710 load data bank register */
#undef OP_LDT
-#define OP_LDT(MODE) \
- CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+#define OP_LDT(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
REG_DB = OPER_8_##MODE(cpustate)<<16;
/* M37710 prefix for B accumulator (0x42) */
/* There is a 2 cycle penalty for all instructions using this prefix */
#undef OP_PFB
-#define OP_PFB() \
- CLK(2); \
- REG_IR = read_8_IMM(REG_PB | REG_PC); \
- REG_PC++; \
+#define OP_PFB() \
+ CLK(2); \
+ REG_IR = read_8_IMM(REG_PB | REG_PC); \
+ REG_PC++; \
cpustate->opcodes42[REG_IR](cpustate);
/* M37710 prefix for multiply / divide instructions (0x89) */
#undef OP_PFXM
-#define OP_PFXM() \
- REG_IR = read_8_IMM(REG_PB | REG_PC); \
- REG_PC++; \
+#define OP_PFXM() \
+ REG_IR = read_8_IMM(REG_PB | REG_PC); \
+ REG_PC++; \
cpustate->opcodes89[REG_IR](cpustate);
/* M37710 unimplemented opcode */
#undef OP_UNIMP
-#define OP_UNIMP() \
+#define OP_UNIMP() \
logerror("error M37710: UNIMPLEMENTED OPCODE! K=%x PC=%x\n", REG_PB, REG_PPC);
/* ======================================================================== */
@@ -2314,7 +2314,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
#define TABLE_OPCODES void (*const m37710i_opcodes_M0X0[256])(m37710i_cpu_struct *cpustate)
#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M0X0[256])(m37710i_cpu_struct *cpustate)
#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M0X0[256])(m37710i_cpu_struct *cpustate)
-#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M0X0 ARGS
+#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M0X0 ARGS
#elif !FLAG_SET_M && FLAG_SET_X
@@ -2323,7 +2323,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
#define TABLE_OPCODES void (*const m37710i_opcodes_M0X1[256])(m37710i_cpu_struct *cpustate)
#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M0X1[256])(m37710i_cpu_struct *cpustate)
#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M0X1[256])(m37710i_cpu_struct *cpustate)
-#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M0X1 ARGS
+#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M0X1 ARGS
#elif FLAG_SET_M && !FLAG_SET_X
@@ -2332,7 +2332,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
#define TABLE_OPCODES void (*const m37710i_opcodes_M1X0[256])(m37710i_cpu_struct *cpustate)
#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M1X0[256])(m37710i_cpu_struct *cpustate)
#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M1X0[256])(m37710i_cpu_struct *cpustate)
-#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M1X0 ARGS
+#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M1X0 ARGS
#elif FLAG_SET_M && FLAG_SET_X
@@ -2341,7 +2341,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
#define TABLE_OPCODES void (*const m37710i_opcodes_M1X1[256])(m37710i_cpu_struct *cpustate)
#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M1X1[256])(m37710i_cpu_struct *cpustate)
#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M1X1[256])(m37710i_cpu_struct *cpustate)
-#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M1X1 ARGS
+#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M1X1 ARGS
#endif
@@ -2785,37 +2785,37 @@ TABLE_OPCODES =
// 00 01 02 03 04 05 06 07
// 08 09 0a 0b 0c 0d 0e 0f
{
- O(00), O(01), O(02), O(03), O(04), O(05), O(06), O(07), // 00
+ O(00), O(01), O(02), O(03), O(04), O(05), O(06), O(07), // 00
O(08), O(09), O(0a), O(0b), O(0c), O(0d), O(0e), O(0f),
- O(10), O(11), O(12), O(13), O(14), O(15), O(16), O(17), // 10
+ O(10), O(11), O(12), O(13), O(14), O(15), O(16), O(17), // 10
O(18), O(19), O(1a), O(1b), O(1c), O(1d), O(1e), O(1f),
- O(20), O(21), O(22), O(23), O(24), O(25), O(26), O(27), // 20
+ O(20), O(21), O(22), O(23), O(24), O(25), O(26), O(27), // 20
O(28), O(29), O(2a), O(2b), O(2c), O(2d), O(2e), O(2f),
- O(30), O(31), O(32), O(33), O(34), O(35), O(36), O(37), // 30
+ O(30), O(31), O(32), O(33), O(34), O(35), O(36), O(37), // 30
O(38), O(39), O(3a), O(3b), O(3c), O(3d), O(3e), O(3f),
- O(40), O(41), O(42), O(43), O(44), O(45), O(46), O(47), // 40
+ O(40), O(41), O(42), O(43), O(44), O(45), O(46), O(47), // 40
O(48), O(49), O(4a), O(4b), O(4c), O(4d), O(4e), O(4f),
- O(50), O(51), O(52), O(53), O(54), O(55), O(56), O(57), // 50
+ O(50), O(51), O(52), O(53), O(54), O(55), O(56), O(57), // 50
O(58), O(59), O(5a), O(5b), O(5c), O(5d), O(5e), O(5f),
- O(60), O(61), O(62), O(63), O(64), O(65), O(66), O(67), // 60
+ O(60), O(61), O(62), O(63), O(64), O(65), O(66), O(67), // 60
O(68), O(69), O(6a), O(6b), O(6c), O(6d), O(6e), O(6f),
- O(70), O(71), O(72), O(73), O(74), O(75), O(76), O(77), // 70
+ O(70), O(71), O(72), O(73), O(74), O(75), O(76), O(77), // 70
O(78), O(79), O(7a), O(7b), O(7c), O(7d), O(7e), O(7f),
- O(80), O(81), O(82), O(83), O(84), O(85), O(86), O(87), // 80
+ O(80), O(81), O(82), O(83), O(84), O(85), O(86), O(87), // 80
O(88), O(89), O(8a), O(8b), O(8c), O(8d), O(8e), O(8f),
- O(90), O(91), O(92), O(93), O(94), O(95), O(96), O(97), // 90
+ O(90), O(91), O(92), O(93), O(94), O(95), O(96), O(97), // 90
O(98), O(99), O(9a), O(9b), O(9c), O(9d), O(9e), O(9f),
- O(a0), O(a1), O(a2), O(a3), O(a4), O(a5), O(a6), O(a7), // a0
+ O(a0), O(a1), O(a2), O(a3), O(a4), O(a5), O(a6), O(a7), // a0
O(a8), O(a9), O(aa), O(ab), O(ac), O(ad), O(ae), O(af),
- O(b0), O(b1), O(b2), O(b3), O(b4), O(b5), O(b6), O(b7), // b0
+ O(b0), O(b1), O(b2), O(b3), O(b4), O(b5), O(b6), O(b7), // b0
O(b8), O(b9), O(ba), O(bb), O(bc), O(bd), O(be), O(bf),
- O(c0), O(c1), O(c2), O(c3), O(c4), O(c5), O(c6), O(c7), // c0
+ O(c0), O(c1), O(c2), O(c3), O(c4), O(c5), O(c6), O(c7), // c0
O(c8), O(c9), O(ca), O(cb), O(cc), O(cd), O(ce), O(cf),
- O(d0), O(d1), O(d2), O(d3), O(d4), O(d5), O(d6), O(d7), // d0
+ O(d0), O(d1), O(d2), O(d3), O(d4), O(d5), O(d6), O(d7), // d0
O(d8), O(d9), O(da), O(db), O(dc), O(dd), O(de), O(df),
- O(e0), O(e1), O(e2), O(e3), O(e4), O(e5), O(e6), O(e7), // e0
+ O(e0), O(e1), O(e2), O(e3), O(e4), O(e5), O(e6), O(e7), // e0
O(e8), O(e9), O(ea), O(eb), O(ec), O(ed), O(ee), O(ef),
- O(f0), O(f1), O(f2), O(f3), O(f4), O(f5), O(f6), O(f7), // f0
+ O(f0), O(f1), O(f2), O(f3), O(f4), O(f5), O(f6), O(f7), // f0
O(f8), O(f9), O(fa), O(fb), O(fc), O(fd), O(fe), O(ff)
};
@@ -2824,37 +2824,37 @@ TABLE_OPCODES2 =
// 00 01 02 03 04 05 06 07
// 08 09 0a 0b 0c 0d 0e 0f
{
- O(200),O(101),O(200),O(103),O(200),O(105),O(200),O(107), // 00
+ O(200),O(101),O(200),O(103),O(200),O(105),O(200),O(107), // 00
O(200),O(109),O(10a),O(200),O(200),O(10d),O(200),O(10f),
- O(200),O(111),O(112),O(113),O(200),O(115),O(200),O(117), // 10
+ O(200),O(111),O(112),O(113),O(200),O(115),O(200),O(117), // 10
O(200),O(119),O(11a),O(11b),O(200),O(11d),O(200),O(11f),
- O(200),O(121),O(200),O(123),O(200),O(125),O(200),O(127), // 20
+ O(200),O(121),O(200),O(123),O(200),O(125),O(200),O(127), // 20
O(200),O(129),O(12a),O(200),O(200),O(12d),O(200),O(12f),
- O(200),O(131),O(132),O(133),O(200),O(135),O(200),O(137), // 30
+ O(200),O(131),O(132),O(133),O(200),O(135),O(200),O(137), // 30
O(200),O(139),O(13a),O(13b),O(200),O(13d),O(200),O(13f),
- O(200),O(141),O(200),O(143),O(200),O(145),O(200),O(147), // 40
+ O(200),O(141),O(200),O(143),O(200),O(145),O(200),O(147), // 40
O(148),O(149),O(14a),O(200),O(200),O(14d),O(200),O(14f),
- O(200),O(151),O(152),O(153),O(200),O(155),O(200),O(157), // 50
+ O(200),O(151),O(152),O(153),O(200),O(155),O(200),O(157), // 50
O(200),O(159),O(200),O(15b),O(200),O(15d),O(200),O(15f),
- O(200),O(161),O(200),O(163),O(200),O(165),O(200),O(167), // 60
+ O(200),O(161),O(200),O(163),O(200),O(165),O(200),O(167), // 60
O(168),O(169),O(16a),O(200),O(200),O(16d),O(200),O(16f),
- O(200),O(171),O(172),O(173),O(200),O(175),O(200),O(177), // 70
+ O(200),O(171),O(172),O(173),O(200),O(175),O(200),O(177), // 70
O(200),O(179),O(200),O(17b),O(200),O(17d),O(200),O(17f),
- O(200),O(181),O(200),O(183),O(200),O(185),O(200),O(187), // 80
+ O(200),O(181),O(200),O(183),O(200),O(185),O(200),O(187), // 80
O(200),O(200),O(18a),O(200),O(200),O(18d),O(200),O(18f),
- O(200),O(191),O(192),O(193),O(200),O(195),O(200),O(197), // 90
+ O(200),O(191),O(192),O(193),O(200),O(195),O(200),O(197), // 90
O(198),O(199),O(200),O(200),O(200),O(19d),O(200),O(19f),
- O(200),O(1a1),O(200),O(1a3),O(200),O(1a5),O(200),O(1a7), // a0
+ O(200),O(1a1),O(200),O(1a3),O(200),O(1a5),O(200),O(1a7), // a0
O(1a8),O(1a9),O(1aa),O(200),O(200),O(1ad),O(200),O(1af),
- O(200),O(1b1),O(1b2),O(1b3),O(200),O(1b5),O(200),O(1b7), // b0
+ O(200),O(1b1),O(1b2),O(1b3),O(200),O(1b5),O(200),O(1b7), // b0
O(200),O(1b9),O(200),O(200),O(200),O(1bd),O(200),O(1bf),
- O(200),O(1c1),O(200),O(1c3),O(200),O(1c5),O(200),O(1c7), // c0
+ O(200),O(1c1),O(200),O(1c3),O(200),O(1c5),O(200),O(1c7), // c0
O(200),O(1c9),O(200),O(200),O(200),O(1cd),O(200),O(1cf),
- O(200),O(1d1),O(1d2),O(1d3),O(200),O(1d5),O(200),O(1d7), // d0
+ O(200),O(1d1),O(1d2),O(1d3),O(200),O(1d5),O(200),O(1d7), // d0
O(200),O(1d9),O(200),O(200),O(200),O(1dd),O(200),O(1df),
- O(200),O(1e1),O(200),O(1e3),O(200),O(1e5),O(200),O(1e7), // e0
+ O(200),O(1e1),O(200),O(1e3),O(200),O(1e5),O(200),O(1e7), // e0
O(200),O(1e9),O(200),O(200),O(200),O(1ed),O(200),O(1ef),
- O(200),O(1f1),O(1f2),O(1f3),O(200),O(1f5),O(200),O(1f7), // f0
+ O(200),O(1f1),O(1f2),O(1f3),O(200),O(1f5),O(200),O(1f7), // f0
O(200),O(1f9),O(200),O(200),O(200),O(1fd),O(200),O(1ff)
};
@@ -2863,37 +2863,37 @@ TABLE_OPCODES3 =
// 00 01 02 03 04 05 06 07
// 08 09 0a 0b 0c 0d 0e 0f
{
- O(200),O(201),O(200),O(203),O(200),O(205),O(200),O(207), // 00
+ O(200),O(201),O(200),O(203),O(200),O(205),O(200),O(207), // 00
O(200),O(209),O(200),O(200),O(200),O(20d),O(200),O(20f),
- O(200),O(211),O(212),O(213),O(200),O(215),O(200),O(217), // 10
+ O(200),O(211),O(212),O(213),O(200),O(215),O(200),O(217), // 10
O(200),O(219),O(200),O(200),O(200),O(21d),O(200),O(21f),
- O(200),O(221),O(200),O(223),O(200),O(225),O(200),O(227), // 20
+ O(200),O(221),O(200),O(223),O(200),O(225),O(200),O(227), // 20
O(228),O(229),O(200),O(200),O(200),O(22d),O(200),O(22f),
- O(200),O(231),O(232),O(233),O(200),O(235),O(200),O(237), // 30
+ O(200),O(231),O(232),O(233),O(200),O(235),O(200),O(237), // 30
O(200),O(239),O(200),O(200),O(200),O(23d),O(200),O(23f),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 40
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 40
O(200),O(249),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 50
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 50
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 60
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 60
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 70
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 70
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 80
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 80
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 90
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 90
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // a0
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // a0
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // b0
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // b0
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(2c2),O(200),O(200),O(200),O(200),O(200), // c0
+ O(200),O(200),O(2c2),O(200),O(200),O(200),O(200),O(200), // c0
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // d0
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // d0
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // e0
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // e0
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200),
- O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // f0
+ O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // f0
O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200)
};