diff options
Diffstat (limited to 'src/emu/cpu/h83002')
-rw-r--r-- | src/emu/cpu/h83002/h8.h | 224 | ||||
-rw-r--r-- | src/emu/cpu/h83002/h8_16.c | 327 | ||||
-rw-r--r-- | src/emu/cpu/h83002/h8_8.c | 268 | ||||
-rw-r--r-- | src/emu/cpu/h83002/h8disasm.c | 47 | ||||
-rw-r--r-- | src/emu/cpu/h83002/h8ops.h | 105 | ||||
-rw-r--r-- | src/emu/cpu/h83002/h8periph.c | 116 | ||||
-rw-r--r-- | src/emu/cpu/h83002/h8priv.h | 24 | ||||
-rw-r--r-- | src/emu/cpu/h83002/h8speriph.c | 177 |
8 files changed, 642 insertions, 646 deletions
diff --git a/src/emu/cpu/h83002/h8.h b/src/emu/cpu/h83002/h8.h index 0cada2d9f0e..12c68961c83 100644 --- a/src/emu/cpu/h83002/h8.h +++ b/src/emu/cpu/h83002/h8.h @@ -33,7 +33,7 @@ enum H8_PC, H8_CCR, - H8_EXR + H8_EXR }; // external input lines @@ -45,14 +45,14 @@ enum H8_IRQ3, H8_IRQ4, H8_IRQ5, - H8_IRQ6, // IRQs 6+ only available on 8-bit H8/3xx or 16-bit H8S/2394 + H8_IRQ6, // IRQs 6+ only available on 8-bit H8/3xx or 16-bit H8S/2394 H8_IRQ7, H8_NMI, - H8_METRO_TIMER_HACK, // as described. this needs to be fixed. + H8_METRO_TIMER_HACK, // as described. this needs to be fixed. - H8_SCI_0_RX, // incoming character on SCI 0 - H8_SCI_1_RX, // incoming character on SCI 1 + H8_SCI_0_RX, // incoming character on SCI 0 + H8_SCI_1_RX, // incoming character on SCI 1 }; // I/O ports @@ -60,23 +60,23 @@ enum { // digital I/O ports // ports 4-B are valid on 16-bit H8/3xx, ports 1-9 on 8-bit H8/3xx - // H8S/2394 has 12 ports named 1-6 and A-G - H8_PORT_1 = 0, // 0 - H8_PORT_2, // 1 - H8_PORT_3, // 2 - H8_PORT_4, // 3 - H8_PORT_5, // 4 - H8_PORT_6, // 5 - H8_PORT_7, // 6 - H8_PORT_8, // 7 - H8_PORT_9, // 8 - H8_PORT_A, // 9 - H8_PORT_B, // A - H8_PORT_C, // B - H8_PORT_D, // C - H8_PORT_E, // D - H8_PORT_F, // E - H8_PORT_G, // F + // H8S/2394 has 12 ports named 1-6 and A-G + H8_PORT_1 = 0, // 0 + H8_PORT_2, // 1 + H8_PORT_3, // 2 + H8_PORT_4, // 3 + H8_PORT_5, // 4 + H8_PORT_6, // 5 + H8_PORT_7, // 6 + H8_PORT_8, // 7 + H8_PORT_9, // 8 + H8_PORT_A, // 9 + H8_PORT_B, // A + H8_PORT_C, // B + H8_PORT_D, // C + H8_PORT_E, // D + H8_PORT_F, // E + H8_PORT_G, // F // analog inputs H8_ADC_0_H = 0x20, @@ -99,7 +99,7 @@ enum // serial ports H8_SERIAL_0 = 0x30, H8_SERIAL_1, - H8_SERIAL_2 + H8_SERIAL_2 }; //////////////////////////// @@ -227,87 +227,87 @@ enum #define H8S_IO_TSTR H8S_IO(0xFFC0) #define H8S_IO_TSYR H8S_IO(0xFFC1) // TPU0 -#define H8S_IO_TTCR0 H8S_IO(0xFFD0) -#define H8S_IO_TMDR0 H8S_IO(0xFFD1) -#define H8S_IO_TIOR0_H H8S_IO(0xFFD2) -#define H8S_IO_TIOR0_L H8S_IO(0xFFD3) -#define H8S_IO_TIER0 H8S_IO(0xFFD4) -#define H8S_IO_TSR0 H8S_IO(0xFFD5) -#define H8S_IO_TCNT0_H H8S_IO(0xFFD6) -#define H8S_IO_TCNT0_L H8S_IO(0xFFD7) -#define H8S_IO_TGR0A_H H8S_IO(0xFFD8) -#define H8S_IO_TGR0A_L H8S_IO(0xFFD9) -#define H8S_IO_TGR0B_H H8S_IO(0xFFDA) -#define H8S_IO_TGR0B_L H8S_IO(0xFFDB) -#define H8S_IO_TGR0C_H H8S_IO(0xFFDC) -#define H8S_IO_TGR0C_L H8S_IO(0xFFDD) -#define H8S_IO_TGR0D_H H8S_IO(0xFFDE) -#define H8S_IO_TGR0D_L H8S_IO(0xFFDF) +#define H8S_IO_TTCR0 H8S_IO(0xFFD0) +#define H8S_IO_TMDR0 H8S_IO(0xFFD1) +#define H8S_IO_TIOR0_H H8S_IO(0xFFD2) +#define H8S_IO_TIOR0_L H8S_IO(0xFFD3) +#define H8S_IO_TIER0 H8S_IO(0xFFD4) +#define H8S_IO_TSR0 H8S_IO(0xFFD5) +#define H8S_IO_TCNT0_H H8S_IO(0xFFD6) +#define H8S_IO_TCNT0_L H8S_IO(0xFFD7) +#define H8S_IO_TGR0A_H H8S_IO(0xFFD8) +#define H8S_IO_TGR0A_L H8S_IO(0xFFD9) +#define H8S_IO_TGR0B_H H8S_IO(0xFFDA) +#define H8S_IO_TGR0B_L H8S_IO(0xFFDB) +#define H8S_IO_TGR0C_H H8S_IO(0xFFDC) +#define H8S_IO_TGR0C_L H8S_IO(0xFFDD) +#define H8S_IO_TGR0D_H H8S_IO(0xFFDE) +#define H8S_IO_TGR0D_L H8S_IO(0xFFDF) // TPU1 -#define H8S_IO_TTCR1 H8S_IO(0xFFE0) -#define H8S_IO_TMDR1 H8S_IO(0xFFE1) -#define H8S_IO_TIOR1 H8S_IO(0xFFE2) -#define H8S_IO_TIER1 H8S_IO(0xFFE4) -#define H8S_IO_TSR1 H8S_IO(0xFFE5) -#define H8S_IO_TCNT1_H H8S_IO(0xFFE6) -#define H8S_IO_TCNT1_L H8S_IO(0xFFE7) -#define H8S_IO_TGR1A_H H8S_IO(0xFFE8) -#define H8S_IO_TGR1A_L H8S_IO(0xFFE9) -#define H8S_IO_TGR1B_H H8S_IO(0xFFEA) -#define H8S_IO_TGR1B_L H8S_IO(0xFFEB) +#define H8S_IO_TTCR1 H8S_IO(0xFFE0) +#define H8S_IO_TMDR1 H8S_IO(0xFFE1) +#define H8S_IO_TIOR1 H8S_IO(0xFFE2) +#define H8S_IO_TIER1 H8S_IO(0xFFE4) +#define H8S_IO_TSR1 H8S_IO(0xFFE5) +#define H8S_IO_TCNT1_H H8S_IO(0xFFE6) +#define H8S_IO_TCNT1_L H8S_IO(0xFFE7) +#define H8S_IO_TGR1A_H H8S_IO(0xFFE8) +#define H8S_IO_TGR1A_L H8S_IO(0xFFE9) +#define H8S_IO_TGR1B_H H8S_IO(0xFFEA) +#define H8S_IO_TGR1B_L H8S_IO(0xFFEB) // TPU2 -#define H8S_IO_TTCR2 H8S_IO(0xFFF0) -#define H8S_IO_TMDR2 H8S_IO(0xFFF1) -#define H8S_IO_TIOR2 H8S_IO(0xFFF2) -#define H8S_IO_TIER2 H8S_IO(0xFFF4) -#define H8S_IO_TSR2 H8S_IO(0xFFF5) -#define H8S_IO_TCNT2_H H8S_IO(0xFFF6) -#define H8S_IO_TCNT2_L H8S_IO(0xFFF7) -#define H8S_IO_TGR2A_H H8S_IO(0xFFF8) -#define H8S_IO_TGR2A_L H8S_IO(0xFFF9) -#define H8S_IO_TGR2B_H H8S_IO(0xFFFA) -#define H8S_IO_TGR2B_L H8S_IO(0xFFFB) +#define H8S_IO_TTCR2 H8S_IO(0xFFF0) +#define H8S_IO_TMDR2 H8S_IO(0xFFF1) +#define H8S_IO_TIOR2 H8S_IO(0xFFF2) +#define H8S_IO_TIER2 H8S_IO(0xFFF4) +#define H8S_IO_TSR2 H8S_IO(0xFFF5) +#define H8S_IO_TCNT2_H H8S_IO(0xFFF6) +#define H8S_IO_TCNT2_L H8S_IO(0xFFF7) +#define H8S_IO_TGR2A_H H8S_IO(0xFFF8) +#define H8S_IO_TGR2A_L H8S_IO(0xFFF9) +#define H8S_IO_TGR2B_H H8S_IO(0xFFFA) +#define H8S_IO_TGR2B_L H8S_IO(0xFFFB) // TPU3 -#define H8S_IO_TTCR3 H8S_IO(0xFE80) -#define H8S_IO_TMDR3 H8S_IO(0xFE81) -#define H8S_IO_TIOR3_H H8S_IO(0xFE82) -#define H8S_IO_TIOR3_L H8S_IO(0xFE83) -#define H8S_IO_TIER3 H8S_IO(0xFE84) -#define H8S_IO_TSR3 H8S_IO(0xFE85) -#define H8S_IO_TCNT3_H H8S_IO(0xFE86) -#define H8S_IO_TCNT3_L H8S_IO(0xFE87) -#define H8S_IO_TGR3A_H H8S_IO(0xFE88) -#define H8S_IO_TGR3A_L H8S_IO(0xFE89) -#define H8S_IO_TGR3B_H H8S_IO(0xFE8A) -#define H8S_IO_TGR3B_L H8S_IO(0xFE8B) -#define H8S_IO_TGR3C_H H8S_IO(0xFE8C) -#define H8S_IO_TGR3C_L H8S_IO(0xFE8D) -#define H8S_IO_TGR3D_H H8S_IO(0xFE8E) -#define H8S_IO_TGR3D_L H8S_IO(0xFE8F) +#define H8S_IO_TTCR3 H8S_IO(0xFE80) +#define H8S_IO_TMDR3 H8S_IO(0xFE81) +#define H8S_IO_TIOR3_H H8S_IO(0xFE82) +#define H8S_IO_TIOR3_L H8S_IO(0xFE83) +#define H8S_IO_TIER3 H8S_IO(0xFE84) +#define H8S_IO_TSR3 H8S_IO(0xFE85) +#define H8S_IO_TCNT3_H H8S_IO(0xFE86) +#define H8S_IO_TCNT3_L H8S_IO(0xFE87) +#define H8S_IO_TGR3A_H H8S_IO(0xFE88) +#define H8S_IO_TGR3A_L H8S_IO(0xFE89) +#define H8S_IO_TGR3B_H H8S_IO(0xFE8A) +#define H8S_IO_TGR3B_L H8S_IO(0xFE8B) +#define H8S_IO_TGR3C_H H8S_IO(0xFE8C) +#define H8S_IO_TGR3C_L H8S_IO(0xFE8D) +#define H8S_IO_TGR3D_H H8S_IO(0xFE8E) +#define H8S_IO_TGR3D_L H8S_IO(0xFE8F) // TPU4 -#define H8S_IO_TTCR4 H8S_IO(0xFE90) -#define H8S_IO_TMDR4 H8S_IO(0xFE91) -#define H8S_IO_TIOR4 H8S_IO(0xFE92) -#define H8S_IO_TIER4 H8S_IO(0xFE94) -#define H8S_IO_TSR4 H8S_IO(0xFE95) -#define H8S_IO_TCNT4_H H8S_IO(0xFE96) -#define H8S_IO_TCNT4_L H8S_IO(0xFE97) -#define H8S_IO_TGR4A_H H8S_IO(0xFE98) -#define H8S_IO_TGR4A_L H8S_IO(0xFE99) -#define H8S_IO_TGR4B_H H8S_IO(0xFE9A) -#define H8S_IO_TGR4B_L H8S_IO(0xFE9B) +#define H8S_IO_TTCR4 H8S_IO(0xFE90) +#define H8S_IO_TMDR4 H8S_IO(0xFE91) +#define H8S_IO_TIOR4 H8S_IO(0xFE92) +#define H8S_IO_TIER4 H8S_IO(0xFE94) +#define H8S_IO_TSR4 H8S_IO(0xFE95) +#define H8S_IO_TCNT4_H H8S_IO(0xFE96) +#define H8S_IO_TCNT4_L H8S_IO(0xFE97) +#define H8S_IO_TGR4A_H H8S_IO(0xFE98) +#define H8S_IO_TGR4A_L H8S_IO(0xFE99) +#define H8S_IO_TGR4B_H H8S_IO(0xFE9A) +#define H8S_IO_TGR4B_L H8S_IO(0xFE9B) // TPU5 -#define H8S_IO_TTCR5 H8S_IO(0xFEA0) -#define H8S_IO_TMDR5 H8S_IO(0xFEA1) -#define H8S_IO_TIOR5 H8S_IO(0xFEA2) -#define H8S_IO_TIER5 H8S_IO(0xFEA4) -#define H8S_IO_TSR5 H8S_IO(0xFEA5) -#define H8S_IO_TCNT5_H H8S_IO(0xFEA6) -#define H8S_IO_TCNT5_L H8S_IO(0xFEA7) -#define H8S_IO_TGR5A_H H8S_IO(0xFEA8) -#define H8S_IO_TGR5A_L H8S_IO(0xFEA9) -#define H8S_IO_TGR5B_H H8S_IO(0xFEAA) -#define H8S_IO_TGR5B_L H8S_IO(0xFEAB) +#define H8S_IO_TTCR5 H8S_IO(0xFEA0) +#define H8S_IO_TMDR5 H8S_IO(0xFEA1) +#define H8S_IO_TIOR5 H8S_IO(0xFEA2) +#define H8S_IO_TIER5 H8S_IO(0xFEA4) +#define H8S_IO_TSR5 H8S_IO(0xFEA5) +#define H8S_IO_TCNT5_H H8S_IO(0xFEA6) +#define H8S_IO_TCNT5_L H8S_IO(0xFEA7) +#define H8S_IO_TGR5A_H H8S_IO(0xFEA8) +#define H8S_IO_TGR5A_L H8S_IO(0xFEA9) +#define H8S_IO_TGR5B_H H8S_IO(0xFEAA) +#define H8S_IO_TGR5B_L H8S_IO(0xFEAB) // DMA #define H8S_IO_MAR1AH H8S_IO(0xFEF0) #define H8S_IO_MAR1AL H8S_IO(0xFEF2) @@ -423,19 +423,19 @@ enum #define H8S_INT_TXI2 0x5A #define H8S_INT_TEI2 0x5B -#define H8S_INT_TGI3A 48 -#define H8S_INT_TGI3B 49 -#define H8S_INT_TGI3C 50 -#define H8S_INT_TGI3D 51 -#define H8S_INT_TCI3V 52 -#define H8S_INT_TGI4A 56 -#define H8S_INT_TGI4B 57 -#define H8S_INT_TCI4V 58 -#define H8S_INT_TCI4U 59 -#define H8S_INT_TGI5A 60 -#define H8S_INT_TGI5B 61 -#define H8S_INT_TCI5V 62 -#define H8S_INT_TCI5U 63 +#define H8S_INT_TGI3A 48 +#define H8S_INT_TGI3B 49 +#define H8S_INT_TGI3C 50 +#define H8S_INT_TGI3D 51 +#define H8S_INT_TCI3V 52 +#define H8S_INT_TGI4A 56 +#define H8S_INT_TGI4B 57 +#define H8S_INT_TCI4V 58 +#define H8S_INT_TCI4U 59 +#define H8S_INT_TGI5A 60 +#define H8S_INT_TGI5B 61 +#define H8S_INT_TCI5V 62 +#define H8S_INT_TCI5U 63 DECLARE_LEGACY_CPU_DEVICE(H83002, h8_3002); DECLARE_LEGACY_CPU_DEVICE(H83007, h8_3007); diff --git a/src/emu/cpu/h83002/h8_16.c b/src/emu/cpu/h83002/h8_16.c index c19ea2b924c..19987c36a3d 100644 --- a/src/emu/cpu/h83002/h8_16.c +++ b/src/emu/cpu/h83002/h8_16.c @@ -21,7 +21,7 @@ CPU_DISASSEMBLE(h8_24); CPU_DISASSEMBLE(h8_32); -#define H8_SP (7) +#define H8_SP (7) #define h8_mem_read8(x) h8->program->read_byte(x) #define h8_mem_read16(z, x) h8->program->read_word(x) @@ -32,12 +32,12 @@ CPU_DISASSEMBLE(h8_32); // timing macros // note: we assume a system 12 - type setup where external access is 3+1 states // timing will be off somewhat for other configurations. -#define H8_IFETCH_TIMING(x) h8->cyccnt -= (x) * 4; -#define H8_BRANCH_TIMING(x) h8->cyccnt -= (x) * 4; -#define H8_STACK_TIMING(x) h8->cyccnt -= (x) * 4; -#define H8_BYTE_TIMING(x, adr) if (address24 >= 0xffff10) h8->cyccnt -= (x) * 3; else h8->cyccnt -= (x) * 4; -#define H8_WORD_TIMING(x, adr) if (address24 >= 0xffff10) h8->cyccnt -= (x) * 3; else h8->cyccnt -= (x) * 4; -#define H8_IOP_TIMING(x) h8->cyccnt -= (x); +#define H8_IFETCH_TIMING(x) h8->cyccnt -= (x) * 4; +#define H8_BRANCH_TIMING(x) h8->cyccnt -= (x) * 4; +#define H8_STACK_TIMING(x) h8->cyccnt -= (x) * 4; +#define H8_BYTE_TIMING(x, adr) if (address24 >= 0xffff10) h8->cyccnt -= (x) * 3; else h8->cyccnt -= (x) * 4; +#define H8_WORD_TIMING(x, adr) if (address24 >= 0xffff10) h8->cyccnt -= (x) * 3; else h8->cyccnt -= (x) * 4; +#define H8_IOP_TIMING(x) h8->cyccnt -= (x); INLINE UINT32 h8_mem_read32(h83xx_state *h8, offs_t address) { @@ -90,7 +90,7 @@ static UINT8 h8_get_ccr(h83xx_state *h8) static UINT8 h8_get_exr(h83xx_state *h8) { - return h8->exr; + return h8->exr; } static char *h8_get_ccr_str(h83xx_state *h8) @@ -265,8 +265,8 @@ static CPU_RESET(h8) h8->pc = h8_mem_read32(h8, 0) & 0xffffff; h8->incheckirqs = 0; - h8->exr = 0; - h8->has_exr = false; + h8->exr = 0; + h8->has_exr = false; // disable timers h8->h8TSTR = 0; @@ -282,7 +282,7 @@ static CPU_RESET(h8s_2xxx) CPU_RESET_CALL(h8); - h8->exr = 7; // set the 3 interrupt bits, clear TRACE + h8->exr = 7; // set the 3 interrupt bits, clear TRACE h8s_periph_reset(h8); h8->has_h8speriphs = true; @@ -295,12 +295,12 @@ static CPU_RESET(h8s_2394) CPU_RESET_CALL(h8); - h8->exr = 7; // set the 3 interrupt bits, clear TRACE - h8->has_exr = true; + h8->exr = 7; // set the 3 interrupt bits, clear TRACE + h8->has_exr = true; - // port 4 is fixed to input only - h8->drs[3] = 0; - h8->ddrs[3] = 0; + // port 4 is fixed to input only + h8->drs[3] = 0; + h8->ddrs[3] = 0; h8s_periph_reset(h8); h8->has_h8speriphs = true; @@ -371,25 +371,25 @@ static void h8_check_irqs(h83xx_state *h8) h8->incheckirqs = 1; - if (h8->has_exr) - { - lv = (h8->exr & 7); - } - else - { - if (h8->h8iflag == 0) - { - lv = 0; - } - else - { - if ((h8->per_regs[0xF2]&0x08)/*SYSCR*/ == 0) - { - if (h8->h8uiflag == 0) - lv = 1; - } - } - } + if (h8->has_exr) + { + lv = (h8->exr & 7); + } + else + { + if (h8->h8iflag == 0) + { + lv = 0; + } + else + { + if ((h8->per_regs[0xF2]&0x08)/*SYSCR*/ == 0) + { + if (h8->h8uiflag == 0) + lv = 1; + } + } + } // any interrupts wanted and can accept ? if(((h8->irq_req[0] != 0) || (h8->irq_req[1]!= 0) || (h8->irq_req[2] != 0)) && (lv >= 0)) @@ -465,31 +465,31 @@ static CPU_SET_INFO( h8 ) h83xx_state *h8 = get_safe_token(device); switch(state) { - case CPUINFO_INT_PC: h8->pc = info->i; break; - case CPUINFO_INT_REGISTER + H8_PC: h8->pc = info->i; break; - case CPUINFO_INT_REGISTER + H8_CCR: h8_set_ccr(h8, info->i); break; - case CPUINFO_INT_REGISTER + H8_EXR: h8_set_exr(h8, info->i); break; - - case CPUINFO_INT_REGISTER + H8_E0: h8->regs[0] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E1: h8->regs[1] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E2: h8->regs[2] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E3: h8->regs[3] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E4: h8->regs[4] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E5: h8->regs[5] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E6: h8->regs[6] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E7: h8->regs[7] = info->i; break; - - case CPUINFO_INT_INPUT_STATE + H8_IRQ0: h8_3002_InterruptRequest(h8, 12, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ1: h8_3002_InterruptRequest(h8, 13, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ2: h8_3002_InterruptRequest(h8, 14, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ3: h8_3002_InterruptRequest(h8, 15, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ4: h8_3002_InterruptRequest(h8, 16, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ5: h8_3002_InterruptRequest(h8, 17, info->i); break; - - case CPUINFO_INT_INPUT_STATE + H8_METRO_TIMER_HACK: h8_3002_InterruptRequest(h8, 24, info->i); break; - - case CPUINFO_INT_INPUT_STATE + H8_SCI_0_RX: h8_3002_InterruptRequest(h8, 53, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX: h8_3002_InterruptRequest(h8, 57, info->i); break; + case CPUINFO_INT_PC: h8->pc = info->i; break; + case CPUINFO_INT_REGISTER + H8_PC: h8->pc = info->i; break; + case CPUINFO_INT_REGISTER + H8_CCR: h8_set_ccr(h8, info->i); break; + case CPUINFO_INT_REGISTER + H8_EXR: h8_set_exr(h8, info->i); break; + + case CPUINFO_INT_REGISTER + H8_E0: h8->regs[0] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E1: h8->regs[1] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E2: h8->regs[2] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E3: h8->regs[3] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E4: h8->regs[4] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E5: h8->regs[5] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E6: h8->regs[6] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E7: h8->regs[7] = info->i; break; + + case CPUINFO_INT_INPUT_STATE + H8_IRQ0: h8_3002_InterruptRequest(h8, 12, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ1: h8_3002_InterruptRequest(h8, 13, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ2: h8_3002_InterruptRequest(h8, 14, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ3: h8_3002_InterruptRequest(h8, 15, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ4: h8_3002_InterruptRequest(h8, 16, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ5: h8_3002_InterruptRequest(h8, 17, info->i); break; + + case CPUINFO_INT_INPUT_STATE + H8_METRO_TIMER_HACK: h8_3002_InterruptRequest(h8, 24, info->i); break; + + case CPUINFO_INT_INPUT_STATE + H8_SCI_0_RX: h8_3002_InterruptRequest(h8, 53, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX: h8_3002_InterruptRequest(h8, 57, info->i); break; default: fatalerror("h8_set_info unknown request %x\n", state); @@ -502,31 +502,31 @@ static CPU_SET_INFO( h8s_2394 ) h83xx_state *h8 = get_safe_token(device); switch(state) { - case CPUINFO_INT_PC: h8->pc = info->i; break; - case CPUINFO_INT_REGISTER + H8_PC: h8->pc = info->i; break; - case CPUINFO_INT_REGISTER + H8_CCR: h8_set_ccr(h8, info->i); break; - case CPUINFO_INT_REGISTER + H8_EXR: h8_set_exr(h8, info->i); break; - - case CPUINFO_INT_REGISTER + H8_E0: h8->regs[0] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E1: h8->regs[1] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E2: h8->regs[2] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E3: h8->regs[3] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E4: h8->regs[4] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E5: h8->regs[5] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E6: h8->regs[6] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E7: h8->regs[7] = info->i; break; - - case CPUINFO_INT_INPUT_STATE + H8_IRQ0: h8_3002_InterruptRequest(h8, 16, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ1: h8_3002_InterruptRequest(h8, 17, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ2: h8_3002_InterruptRequest(h8, 18, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ3: h8_3002_InterruptRequest(h8, 19, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ4: h8_3002_InterruptRequest(h8, 20, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ5: h8_3002_InterruptRequest(h8, 21, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ6: h8_3002_InterruptRequest(h8, 22, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ7: h8_3002_InterruptRequest(h8, 23, info->i); break; - - case CPUINFO_INT_INPUT_STATE + H8_SCI_0_RX: h8_3002_InterruptRequest(h8, 81, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX: h8_3002_InterruptRequest(h8, 85, info->i); break; + case CPUINFO_INT_PC: h8->pc = info->i; break; + case CPUINFO_INT_REGISTER + H8_PC: h8->pc = info->i; break; + case CPUINFO_INT_REGISTER + H8_CCR: h8_set_ccr(h8, info->i); break; + case CPUINFO_INT_REGISTER + H8_EXR: h8_set_exr(h8, info->i); break; + + case CPUINFO_INT_REGISTER + H8_E0: h8->regs[0] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E1: h8->regs[1] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E2: h8->regs[2] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E3: h8->regs[3] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E4: h8->regs[4] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E5: h8->regs[5] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E6: h8->regs[6] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E7: h8->regs[7] = info->i; break; + + case CPUINFO_INT_INPUT_STATE + H8_IRQ0: h8_3002_InterruptRequest(h8, 16, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ1: h8_3002_InterruptRequest(h8, 17, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ2: h8_3002_InterruptRequest(h8, 18, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ3: h8_3002_InterruptRequest(h8, 19, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ4: h8_3002_InterruptRequest(h8, 20, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ5: h8_3002_InterruptRequest(h8, 21, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ6: h8_3002_InterruptRequest(h8, 22, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ7: h8_3002_InterruptRequest(h8, 23, info->i); break; + + case CPUINFO_INT_INPUT_STATE + H8_SCI_0_RX: h8_3002_InterruptRequest(h8, 81, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX: h8_3002_InterruptRequest(h8, 85, info->i); break; default: fatalerror("h8_set_info unknown request %x\n", state); @@ -881,74 +881,74 @@ CPU_GET_INFO( h8_3002 ) switch(state) { // Interface functions and variables - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(h8); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(h8); break; - case CPUINFO_FCT_EXIT: info->exit = 0; break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(h8); break; - case CPUINFO_FCT_BURN: info->burn = 0; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(h8_32); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &h8->cyccnt; break; - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(h83xx_state); break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 10; break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(h8); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(h8); break; + case CPUINFO_FCT_EXIT: info->exit = 0; break; + case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(h8); break; + case CPUINFO_FCT_BURN: info->burn = 0; break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(h8_32); break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &h8->cyccnt; break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(h83xx_state); break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 10; break; // Bus sizes - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; // Internal maps case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(h8_3002_internal_map); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map16 = NULL; break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_IO: info->internal_map16 = NULL; break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map16 = NULL; break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_IO: info->internal_map16 = NULL; break; // CPU misc parameters - case CPUINFO_STR_NAME: strcpy(info->s, "H8/3002"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_FLAGS: strcpy(info->s, h8_get_ccr_str(h8)); break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_INPUT_LINES: info->i = 16; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = -1; break; + case CPUINFO_STR_NAME: strcpy(info->s, "H8/3002"); break; + case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_FLAGS: strcpy(info->s, h8_get_ccr_str(h8)); break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_INPUT_LINES: info->i = 16; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = -1; break; // CPU main state - case CPUINFO_INT_PC: info->i = h8->pc; break; - case CPUINFO_INT_PREVIOUSPC: info->i = h8->ppc; break; - - case CPUINFO_INT_REGISTER + H8_PC: info->i = h8->pc; break; - case CPUINFO_INT_REGISTER + H8_CCR: info->i = h8_get_ccr(h8); break; - case CPUINFO_INT_REGISTER + H8_EXR: info->i = h8_get_exr(h8); break; - - case CPUINFO_INT_REGISTER + H8_E0: info->i = h8->regs[0]; break; - case CPUINFO_INT_REGISTER + H8_E1: info->i = h8->regs[1]; break; - case CPUINFO_INT_REGISTER + H8_E2: info->i = h8->regs[2]; break; - case CPUINFO_INT_REGISTER + H8_E3: info->i = h8->regs[3]; break; - case CPUINFO_INT_REGISTER + H8_E4: info->i = h8->regs[4]; break; - case CPUINFO_INT_REGISTER + H8_E5: info->i = h8->regs[5]; break; - case CPUINFO_INT_REGISTER + H8_E6: info->i = h8->regs[6]; break; - case CPUINFO_INT_REGISTER + H8_E7: info->i = h8->regs[7]; break; + case CPUINFO_INT_PC: info->i = h8->pc; break; + case CPUINFO_INT_PREVIOUSPC: info->i = h8->ppc; break; + + case CPUINFO_INT_REGISTER + H8_PC: info->i = h8->pc; break; + case CPUINFO_INT_REGISTER + H8_CCR: info->i = h8_get_ccr(h8); break; + case CPUINFO_INT_REGISTER + H8_EXR: info->i = h8_get_exr(h8); break; + + case CPUINFO_INT_REGISTER + H8_E0: info->i = h8->regs[0]; break; + case CPUINFO_INT_REGISTER + H8_E1: info->i = h8->regs[1]; break; + case CPUINFO_INT_REGISTER + H8_E2: info->i = h8->regs[2]; break; + case CPUINFO_INT_REGISTER + H8_E3: info->i = h8->regs[3]; break; + case CPUINFO_INT_REGISTER + H8_E4: info->i = h8->regs[4]; break; + case CPUINFO_INT_REGISTER + H8_E5: info->i = h8->regs[5]; break; + case CPUINFO_INT_REGISTER + H8_E6: info->i = h8->regs[6]; break; + case CPUINFO_INT_REGISTER + H8_E7: info->i = h8->regs[7]; break; // CPU debug stuff - case CPUINFO_STR_REGISTER + H8_PC: sprintf(info->s, "PC :%08x", h8->pc); break; - case CPUINFO_STR_REGISTER + H8_CCR: sprintf(info->s, "CCR :%08x", h8_get_ccr(h8)); break; - case CPUINFO_STR_REGISTER + H8_EXR: sprintf(info->s, "EXR :%02x", h8_get_exr(h8)); break; - - case CPUINFO_STR_REGISTER + H8_E0: sprintf(info->s, "ER0 :%08x", h8->regs[0]); break; - case CPUINFO_STR_REGISTER + H8_E1: sprintf(info->s, "ER1 :%08x", h8->regs[1]); break; - case CPUINFO_STR_REGISTER + H8_E2: sprintf(info->s, "ER2 :%08x", h8->regs[2]); break; - case CPUINFO_STR_REGISTER + H8_E3: sprintf(info->s, "ER3 :%08x", h8->regs[3]); break; - case CPUINFO_STR_REGISTER + H8_E4: sprintf(info->s, "ER4 :%08x", h8->regs[4]); break; - case CPUINFO_STR_REGISTER + H8_E5: sprintf(info->s, "ER5 :%08x", h8->regs[5]); break; - case CPUINFO_STR_REGISTER + H8_E6: sprintf(info->s, "ER6 :%08x", h8->regs[6]); break; - case CPUINFO_STR_REGISTER + H8_E7: sprintf(info->s, " SP :%08x", h8->regs[7]); break; + case CPUINFO_STR_REGISTER + H8_PC: sprintf(info->s, "PC :%08x", h8->pc); break; + case CPUINFO_STR_REGISTER + H8_CCR: sprintf(info->s, "CCR :%08x", h8_get_ccr(h8)); break; + case CPUINFO_STR_REGISTER + H8_EXR: sprintf(info->s, "EXR :%02x", h8_get_exr(h8)); break; + + case CPUINFO_STR_REGISTER + H8_E0: sprintf(info->s, "ER0 :%08x", h8->regs[0]); break; + case CPUINFO_STR_REGISTER + H8_E1: sprintf(info->s, "ER1 :%08x", h8->regs[1]); break; + case CPUINFO_STR_REGISTER + H8_E2: sprintf(info->s, "ER2 :%08x", h8->regs[2]); break; + case CPUINFO_STR_REGISTER + H8_E3: sprintf(info->s, "ER3 :%08x", h8->regs[3]); break; + case CPUINFO_STR_REGISTER + H8_E4: sprintf(info->s, "ER4 :%08x", h8->regs[4]); break; + case CPUINFO_STR_REGISTER + H8_E5: sprintf(info->s, "ER5 :%08x", h8->regs[5]); break; + case CPUINFO_STR_REGISTER + H8_E6: sprintf(info->s, "ER6 :%08x", h8->regs[6]); break; + case CPUINFO_STR_REGISTER + H8_E7: sprintf(info->s, " SP :%08x", h8->regs[7]); break; } } @@ -957,8 +957,8 @@ CPU_GET_INFO( h8_3044 ) switch (state) { case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(h8_3044_internal_map); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(h8_24); break; - case CPUINFO_STR_NAME: strcpy(info->s, "H8/3044"); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(h8_24); break; + case CPUINFO_STR_NAME: strcpy(info->s, "H8/3044"); break; default: CPU_GET_INFO_CALL(h8_3002); } @@ -969,8 +969,8 @@ CPU_GET_INFO( h8_3007 ) switch (state) { case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(h8_3007_internal_map); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8_3007); break; - case CPUINFO_STR_NAME: strcpy(info->s, "H8/3007"); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8_3007); break; + case CPUINFO_STR_NAME: strcpy(info->s, "H8/3007"); break; default: CPU_GET_INFO_CALL(h8_3002); } @@ -981,9 +981,9 @@ CPU_GET_INFO( h8s_2241 ) switch (state) { case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(h8s_2241_internal_map); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break; - case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2xxx); break; - case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2241"); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break; + case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2xxx); break; + case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2241"); break; default: CPU_GET_INFO_CALL(h8_3002); } @@ -994,9 +994,9 @@ CPU_GET_INFO( h8s_2246 ) switch (state) { case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(h8s_2246_internal_map); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break; - case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2xxx); break; - case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2246"); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break; + case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2xxx); break; + case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2246"); break; default: CPU_GET_INFO_CALL(h8_3002); } @@ -1007,9 +1007,9 @@ CPU_GET_INFO( h8s_2323 ) switch (state) { case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(h8s_2323_internal_map); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break; - case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2xxx); break; - case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2323"); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break; + case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2xxx); break; + case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2323"); break; default: CPU_GET_INFO_CALL(h8_3002); } @@ -1020,10 +1020,10 @@ CPU_GET_INFO( h8s_2394 ) switch (state) { case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(h8s_2394_internal_map); break; - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(h8s_2394); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break; - case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2394); break; - case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2394"); break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(h8s_2394); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break; + case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2394); break; + case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2394"); break; default: CPU_GET_INFO_CALL(h8_3002); } @@ -1034,10 +1034,10 @@ CPU_GET_INFO( h8s_2655 ) switch (state) { case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(h8s_2655_internal_map); break; - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(h8s_2394); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break; - case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2xxx); break; - case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2655"); break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(h8s_2394); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8s_2xxx); break; + case CPUINFO_FCT_RESET: info->reset= CPU_RESET_NAME(h8s_2xxx); break; + case CPUINFO_STR_NAME: strcpy(info->s, "H8S/2655"); break; default: CPU_GET_INFO_CALL(h8_3002); } @@ -1052,4 +1052,3 @@ DEFINE_LEGACY_CPU_DEVICE(H8S2246, h8s_2246); DEFINE_LEGACY_CPU_DEVICE(H8S2323, h8s_2323); DEFINE_LEGACY_CPU_DEVICE(H8S2394, h8s_2394); DEFINE_LEGACY_CPU_DEVICE(H8S2655, h8s_2655); - diff --git a/src/emu/cpu/h83002/h8_8.c b/src/emu/cpu/h83002/h8_8.c index dcfef2cca4d..7d6da1fd4a7 100644 --- a/src/emu/cpu/h83002/h8_8.c +++ b/src/emu/cpu/h83002/h8_8.c @@ -16,18 +16,18 @@ CPU_DISASSEMBLE(h8); -#define H8_SP (7) +#define H8_SP (7) -#define h8_mem_read8(x) h8->program->read_byte(x) -#define h8_mem_write8(x, y) h8->program->write_byte(x, y) +#define h8_mem_read8(x) h8->program->read_byte(x) +#define h8_mem_write8(x, y) h8->program->write_byte(x, y) // timing macros -#define H8_IFETCH_TIMING(x) h8->cyccnt -= (x) * 4; -#define H8_BRANCH_TIMING(x) h8->cyccnt -= (x) * 4; -#define H8_STACK_TIMING(x) h8->cyccnt -= (x) * 4; -#define H8_BYTE_TIMING(x, adr) if (address24 >= 0xff90) h8->cyccnt -= (x) * 3; else h8->cyccnt -= (x) * 4; -#define H8_WORD_TIMING(x, adr) if (address24 >= 0xff90) h8->cyccnt -= (x) * 3; else h8->cyccnt -= (x) * 4; -#define H8_IOP_TIMING(x) h8->cyccnt -= (x); +#define H8_IFETCH_TIMING(x) h8->cyccnt -= (x) * 4; +#define H8_BRANCH_TIMING(x) h8->cyccnt -= (x) * 4; +#define H8_STACK_TIMING(x) h8->cyccnt -= (x) * 4; +#define H8_BYTE_TIMING(x, adr) if (address24 >= 0xff90) h8->cyccnt -= (x) * 3; else h8->cyccnt -= (x) * 4; +#define H8_WORD_TIMING(x, adr) if (address24 >= 0xff90) h8->cyccnt -= (x) * 3; else h8->cyccnt -= (x) * 4; +#define H8_IOP_TIMING(x) h8->cyccnt -= (x); static TIMER_CALLBACK( h8_timer_0_cb ); static TIMER_CALLBACK( h8_timer_1_cb ); @@ -106,7 +106,7 @@ static UINT8 h8_get_ccr(h83xx_state *h8) static UINT8 h8_get_exr(h83xx_state *h8) { - return h8->exr; + return h8->exr; } static char *h8_get_ccr_str(h83xx_state *h8) @@ -295,8 +295,8 @@ static void h8_GenException(h83xx_state *h8, UINT8 vectornr) h8->pc = h8_mem_read16(h8, vectornr * 2) & 0xffff; // these timings are still approximations but much better than before - H8_IFETCH_TIMING(8); // 24 cycles - H8_STACK_TIMING(3); // 12 cycles + H8_IFETCH_TIMING(8); // 24 cycles + H8_STACK_TIMING(3); // 12 cycles } static int h8_get_priority(h83xx_state *h8, UINT8 bit) @@ -443,7 +443,7 @@ static void timer_8bit_expire(h83xx_state *h8, int t, int sel) switch ((h8->TCR[t]>>3) & 3) { - case 0: // no clear + case 0: // no clear break; case 1: // clear on match A @@ -462,7 +462,7 @@ static void timer_8bit_expire(h83xx_state *h8, int t, int sel) } break; - case 3: // clear on external reset input signal (not implemented) + case 3: // clear on external reset input signal (not implemented) logerror("H8: external reset not implemented for 8-bit timers\n"); break; } @@ -476,32 +476,32 @@ static CPU_SET_INFO( h8 ) h83xx_state *h8 = get_safe_token(device); switch(state) { - case CPUINFO_INT_PC: h8->pc = info->i; break; - case CPUINFO_INT_REGISTER + H8_PC: h8->pc = info->i; break; - case CPUINFO_INT_REGISTER + H8_CCR: h8_set_ccr(h8, info->i); break; - case CPUINFO_INT_REGISTER + H8_EXR: h8_set_exr(h8, info->i); break; - - case CPUINFO_INT_REGISTER + H8_E0: h8->regs[0] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E1: h8->regs[1] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E2: h8->regs[2] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E3: h8->regs[3] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E4: h8->regs[4] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E5: h8->regs[5] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E6: h8->regs[6] = info->i; break; - case CPUINFO_INT_REGISTER + H8_E7: h8->regs[7] = info->i; break; - - case CPUINFO_INT_INPUT_STATE + H8_NMI: h8_300_InterruptRequest(h8, 3, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ0: h8_300_InterruptRequest(h8, 4, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ1: h8_300_InterruptRequest(h8, 5, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ2: h8_300_InterruptRequest(h8, 6, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ3: h8_300_InterruptRequest(h8, 7, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ4: h8_300_InterruptRequest(h8, 8, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ5: h8_300_InterruptRequest(h8, 9, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ6: h8_300_InterruptRequest(h8, 10, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_IRQ7: h8_300_InterruptRequest(h8, 11, info->i); break; - - case CPUINFO_INT_INPUT_STATE + H8_SCI_0_RX: h8_300_InterruptRequest(h8, 28, info->i); break; - case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX: h8_300_InterruptRequest(h8, 32, info->i); break; + case CPUINFO_INT_PC: h8->pc = info->i; break; + case CPUINFO_INT_REGISTER + H8_PC: h8->pc = info->i; break; + case CPUINFO_INT_REGISTER + H8_CCR: h8_set_ccr(h8, info->i); break; + case CPUINFO_INT_REGISTER + H8_EXR: h8_set_exr(h8, info->i); break; + + case CPUINFO_INT_REGISTER + H8_E0: h8->regs[0] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E1: h8->regs[1] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E2: h8->regs[2] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E3: h8->regs[3] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E4: h8->regs[4] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E5: h8->regs[5] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E6: h8->regs[6] = info->i; break; + case CPUINFO_INT_REGISTER + H8_E7: h8->regs[7] = info->i; break; + + case CPUINFO_INT_INPUT_STATE + H8_NMI: h8_300_InterruptRequest(h8, 3, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ0: h8_300_InterruptRequest(h8, 4, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ1: h8_300_InterruptRequest(h8, 5, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ2: h8_300_InterruptRequest(h8, 6, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ3: h8_300_InterruptRequest(h8, 7, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ4: h8_300_InterruptRequest(h8, 8, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ5: h8_300_InterruptRequest(h8, 9, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ6: h8_300_InterruptRequest(h8, 10, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_IRQ7: h8_300_InterruptRequest(h8, 11, info->i); break; + + case CPUINFO_INT_INPUT_STATE + H8_SCI_0_RX: h8_300_InterruptRequest(h8, 28, info->i); break; + case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX: h8_300_InterruptRequest(h8, 32, info->i); break; default: fatalerror("h8_set_info unknown request %x\n", state); @@ -521,76 +521,76 @@ static READ8_HANDLER( h8330_itu_r ) switch(reg) { - case 0x8d: // serial Rx 1 + case 0x8d: // serial Rx 1 val = h8->io->read_byte(H8_SERIAL_1); break; - case 0x92: // FRC H + case 0x92: // FRC H frc = h8->device->total_cycles() / divider[h8->per_regs[0x96]]; frc %= 65536; return frc>>8; - case 0x93: // FRC L + case 0x93: // FRC L frc = h8->device->total_cycles() / divider[h8->per_regs[0x96]]; frc %= 65536; return frc&0xff; - case 0xb2: // port 1 data + case 0xb2: // port 1 data val = h8->io->read_byte(H8_PORT_1); break; - case 0xb3: // port 2 data + case 0xb3: // port 2 data val = h8->io->read_byte(H8_PORT_2); break; - case 0xb6: // port 3 data + case 0xb6: // port 3 data val = h8->io->read_byte(H8_PORT_3); break; - case 0xb7: // port 4 data + case 0xb7: // port 4 data val = h8->io->read_byte(H8_PORT_4); break; - case 0xba: // port 5 data + case 0xba: // port 5 data val = h8->io->read_byte(H8_PORT_5); break; - case 0xbb: // port 6 data + case 0xbb: // port 6 data val = h8->io->read_byte(H8_PORT_6); break; - case 0xbe: // port 7 data + case 0xbe: // port 7 data val = h8->io->read_byte(H8_PORT_7); break; - case 0xbf: // port 8 data + case 0xbf: // port 8 data val = h8->io->read_byte(H8_PORT_8); break; - case 0xc1: // port 9 data + case 0xc1: // port 9 data val = h8->io->read_byte(H8_PORT_9); break; - case 0xdc: // serial status + case 0xdc: // serial status val = 0x87; break; - case 0xdd: // serial Rx 0 + case 0xdd: // serial Rx 0 val = h8->io->read_byte(H8_SERIAL_0); break; - case 0xe0: // ADC 0 low byte + case 0xe0: // ADC 0 low byte val = h8->io->read_byte(H8_ADC_0_L); break; - case 0xe1: // ADC 0 high byte + case 0xe1: // ADC 0 high byte val = h8->io->read_byte(H8_ADC_0_H); break; - case 0xe2: // ADC 1 low byte + case 0xe2: // ADC 1 low byte val = h8->io->read_byte(H8_ADC_1_L); break; - case 0xe3: // ADC 1 high byte + case 0xe3: // ADC 1 high byte val = h8->io->read_byte(H8_ADC_1_H); break; - case 0xe4: // ADC 2 low byte + case 0xe4: // ADC 2 low byte val = h8->io->read_byte(H8_ADC_2_L); break; - case 0xe5: // ADC 2 high byte + case 0xe5: // ADC 2 high byte val = h8->io->read_byte(H8_ADC_2_H); break; - case 0xe6: // ADC 3 low byte + case 0xe6: // ADC 3 low byte val = h8->io->read_byte(H8_ADC_3_L); break; - case 0xe7: // ADC 3 high byte + case 0xe7: // ADC 3 high byte val = h8->io->read_byte(H8_ADC_3_H); break; - case 0xe8: // ADCSR: A/D control/status - val = 0x80; // return conversion completed + case 0xe8: // ADCSR: A/D control/status + val = 0x80; // return conversion completed break; default: val = h8->per_regs[reg]; @@ -612,37 +612,37 @@ static WRITE8_HANDLER( h8330_itu_w ) case 0x80: printf("%02x to flash control or external\n", data); break; - case 0x8b: // serial Tx 1 + case 0x8b: // serial Tx 1 h8->io->write_byte(H8_SERIAL_1, data); break; - case 0xb2: // port 1 data + case 0xb2: // port 1 data h8->io->write_byte(H8_PORT_1, data); break; - case 0xb3: // port 2 data + case 0xb3: // port 2 data h8->io->write_byte(H8_PORT_2, data); break; - case 0xb6: // port 3 data + case 0xb6: // port 3 data h8->io->write_byte(H8_PORT_3, data); break; - case 0xb7: // port 4 data + case 0xb7: // port 4 data h8->io->write_byte(H8_PORT_4, data); break; - case 0xba: // port 5 data + case 0xba: // port 5 data h8->io->write_byte(H8_PORT_5, data); break; - case 0xbb: // port 6 data + case 0xbb: // port 6 data h8->io->write_byte(H8_PORT_6, data); break; - case 0xbe: // port 7 data + case 0xbe: // port 7 data h8->io->write_byte(H8_PORT_7, data); break; - case 0xbf: // port 8 data + case 0xbf: // port 8 data h8->io->write_byte(H8_PORT_8, data); break; - case 0xc1: // port 9 data + case 0xc1: // port 9 data h8->io->write_byte(H8_PORT_9, data); break; - case 0xdb: // serial Tx 0 + case 0xdb: // serial Tx 0 h8->io->write_byte(H8_SERIAL_0, data); break; @@ -662,7 +662,7 @@ static WRITE8_HANDLER( h8330_itu_w ) break; case 0xc8: - h8->TCR[0] = data; + h8->TCR[0] = data; recalc_8bit_timer(h8, 0); break; case 0xc9: @@ -692,7 +692,7 @@ static WRITE8_HANDLER( h8330_itu_w ) break; case 0xd0: - h8->TCR[1] = data; + h8->TCR[1] = data; recalc_8bit_timer(h8, 1); break; case 0xd1: @@ -755,74 +755,74 @@ CPU_GET_INFO( h8_3334 ) switch(state) { // Interface functions and variables - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(h8); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8bit); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(h8bit); break; - case CPUINFO_FCT_EXIT: info->exit = 0; break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(h8); break; - case CPUINFO_FCT_BURN: info->burn = 0; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(h8); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &h8->cyccnt; break; - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(h83xx_state); break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 10; break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(h8); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(h8bit); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(h8bit); break; + case CPUINFO_FCT_EXIT: info->exit = 0; break; + case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(h8); break; + case CPUINFO_FCT_BURN: info->burn = 0; break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(h8); break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &h8->cyccnt; break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(h83xx_state); break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 10; break; // Bus sizes - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; // Internal maps case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(h8_3334_internal_map); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = NULL; break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_IO: info->internal_map16 = NULL; break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map8 = NULL; break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_IO: info->internal_map16 = NULL; break; // CPU misc parameters - case CPUINFO_STR_NAME: strcpy(info->s, "H8/3334"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_FLAGS: strcpy(info->s, h8_get_ccr_str(h8)); break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_INPUT_LINES: info->i = 16; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = -1; break; + case CPUINFO_STR_NAME: strcpy(info->s, "H8/3334"); break; + case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_FLAGS: strcpy(info->s, h8_get_ccr_str(h8)); break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_INPUT_LINES: info->i = 16; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = -1; break; // CPU main state - case CPUINFO_INT_PC: info->i = h8->pc; break; - case CPUINFO_INT_PREVIOUSPC: info->i = h8->ppc; break; - - case CPUINFO_INT_REGISTER + H8_PC: info->i = h8->pc; break; - case CPUINFO_INT_REGISTER + H8_CCR: info->i = h8_get_ccr(h8); break; - case CPUINFO_INT_REGISTER + H8_EXR: info->i = h8_get_exr(h8); break; - - case CPUINFO_INT_REGISTER + H8_E0: info->i = h8->regs[0]; break; - case CPUINFO_INT_REGISTER + H8_E1: info->i = h8->regs[1]; break; - case CPUINFO_INT_REGISTER + H8_E2: info->i = h8->regs[2]; break; - case CPUINFO_INT_REGISTER + H8_E3: info->i = h8->regs[3]; break; - case CPUINFO_INT_REGISTER + H8_E4: info->i = h8->regs[4]; break; - case CPUINFO_INT_REGISTER + H8_E5: info->i = h8->regs[5]; break; - case CPUINFO_INT_REGISTER + H8_E6: info->i = h8->regs[6]; break; - case CPUINFO_INT_REGISTER + H8_E7: info->i = h8->regs[7]; break; + case CPUINFO_INT_PC: info->i = h8->pc; break; + case CPUINFO_INT_PREVIOUSPC: info->i = h8->ppc; break; + + case CPUINFO_INT_REGISTER + H8_PC: info->i = h8->pc; break; + case CPUINFO_INT_REGISTER + H8_CCR: info->i = h8_get_ccr(h8); break; + case CPUINFO_INT_REGISTER + H8_EXR: info->i = h8_get_exr(h8); break; + + case CPUINFO_INT_REGISTER + H8_E0: info->i = h8->regs[0]; break; + case CPUINFO_INT_REGISTER + H8_E1: info->i = h8->regs[1]; break; + case CPUINFO_INT_REGISTER + H8_E2: info->i = h8->regs[2]; break; + case CPUINFO_INT_REGISTER + H8_E3: info->i = h8->regs[3]; break; + case CPUINFO_INT_REGISTER + H8_E4: info->i = h8->regs[4]; break; + case CPUINFO_INT_REGISTER + H8_E5: info->i = h8->regs[5]; break; + case CPUINFO_INT_REGISTER + H8_E6: info->i = h8->regs[6]; break; + case CPUINFO_INT_REGISTER + H8_E7: info->i = h8->regs[7]; break; // CPU debug stuff - case CPUINFO_STR_REGISTER + H8_PC: sprintf(info->s, "PC :%08x", h8->pc); break; - case CPUINFO_STR_REGISTER + H8_CCR: sprintf(info->s, "CCR :%08x", h8_get_ccr(h8)); break; - case CPUINFO_STR_REGISTER + H8_EXR: sprintf(info->s, "EXR :%02x", h8_get_exr(h8)); break; - - case CPUINFO_STR_REGISTER + H8_E0: sprintf(info->s, " R0 :%08x", h8->regs[0]); break; - case CPUINFO_STR_REGISTER + H8_E1: sprintf(info->s, " R1 :%08x", h8->regs[1]); break; - case CPUINFO_STR_REGISTER + H8_E2: sprintf(info->s, " R2 :%08x", h8->regs[2]); break; - case CPUINFO_STR_REGISTER + H8_E3: sprintf(info->s, " R3 :%08x", h8->regs[3]); break; - case CPUINFO_STR_REGISTER + H8_E4: sprintf(info->s, " R4 :%08x", h8->regs[4]); break; - case CPUINFO_STR_REGISTER + H8_E5: sprintf(info->s, " R5 :%08x", h8->regs[5]); break; - case CPUINFO_STR_REGISTER + H8_E6: sprintf(info->s, " R6 :%08x", h8->regs[6]); break; - case CPUINFO_STR_REGISTER + H8_E7: sprintf(info->s, " SP :%08x", h8->regs[7]); break; + case CPUINFO_STR_REGISTER + H8_PC: sprintf(info->s, "PC :%08x", h8->pc); break; + case CPUINFO_STR_REGISTER + H8_CCR: sprintf(info->s, "CCR :%08x", h8_get_ccr(h8)); break; + case CPUINFO_STR_REGISTER + H8_EXR: sprintf(info->s, "EXR :%02x", h8_get_exr(h8)); break; + + case CPUINFO_STR_REGISTER + H8_E0: sprintf(info->s, " R0 :%08x", h8->regs[0]); break; + case CPUINFO_STR_REGISTER + H8_E1: sprintf(info->s, " R1 :%08x", h8->regs[1]); break; + case CPUINFO_STR_REGISTER + H8_E2: sprintf(info->s, " R2 :%08x", h8->regs[2]); break; + case CPUINFO_STR_REGISTER + H8_E3: sprintf(info->s, " R3 :%08x", h8->regs[3]); break; + case CPUINFO_STR_REGISTER + H8_E4: sprintf(info->s, " R4 :%08x", h8->regs[4]); break; + case CPUINFO_STR_REGISTER + H8_E5: sprintf(info->s, " R5 :%08x", h8->regs[5]); break; + case CPUINFO_STR_REGISTER + H8_E6: sprintf(info->s, " R6 :%08x", h8->regs[6]); break; + case CPUINFO_STR_REGISTER + H8_E7: sprintf(info->s, " SP :%08x", h8->regs[7]); break; } } diff --git a/src/emu/cpu/h83002/h8disasm.c b/src/emu/cpu/h83002/h8disasm.c index 5756665cf43..31007dd876e 100644 --- a/src/emu/cpu/h83002/h8disasm.c +++ b/src/emu/cpu/h83002/h8disasm.c @@ -12,14 +12,14 @@ #include "debugger.h" #include "h8.h" -static const char *const bit_instr[8] = {"bset", "bnot", "bclr", "btst", "bor", "bxor", "band", "bld"}; -static const char *const bit_instr2[8] = {"bset", "bnot", "bclr", "btst", "bior", "bixor", "biand", "bild"}; -static const char *const imm32l_instr[8] = {"mov", "add", "cmp", "sub", "or", "xor", "and", "?"}; -static const char *const branch_instr[16] = {"bt", "bf", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc", "bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble"}; +static const char *const bit_instr[8] = {"bset", "bnot", "bclr", "btst", "bor", "bxor", "band", "bld"}; +static const char *const bit_instr2[8] = {"bset", "bnot", "bclr", "btst", "bior", "bixor", "biand", "bild"}; +static const char *const imm32l_instr[8] = {"mov", "add", "cmp", "sub", "or", "xor", "and", "?"}; +static const char *const branch_instr[16] = {"bt", "bf", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc", "bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble"}; -static const char *const reg_names32[8] = {"ER0", "ER1", "ER2", "ER3", "ER4", "ER5", "ER6", "SP"}; -static const char *const reg_names16[16] = {"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "E0", "E1", "E2", "E3", "E4", "E5", "E6", "E7"}; -static const char *const reg_names8[16] = {"R0H", "R1H", "R2H", "R3H", "R4H", "R5H", "R6H", "R7H","R0L", "R1L", "R2L", "R3L", "R4L", "R5L", "R6L", "R7L"}; +static const char *const reg_names32[8] = {"ER0", "ER1", "ER2", "ER3", "ER4", "ER5", "ER6", "SP"}; +static const char *const reg_names16[16] = {"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "E0", "E1", "E2", "E3", "E4", "E5", "E6", "E7"}; +static const char *const reg_names8[16] = {"R0H", "R1H", "R2H", "R3H", "R4H", "R5H", "R6H", "R7H","R0L", "R1L", "R2L", "R3L", "R4L", "R5L", "R6L", "R7L"}; static UINT32 h8disasm_0(UINT32 address, UINT32 opcode, char *output, const UINT8 *oprom); static UINT32 h8disasm_1(UINT32 address, UINT32 opcode, char *output, const UINT8 *oprom); @@ -203,25 +203,25 @@ static UINT32 h8disasm_0(UINT32 pc, UINT32 opcode, char *buffer, const UINT8 *op case 0x6b: // stc.w CCR,@abs - if ((data16&0xff) == 0x00) // 16 bit absolute + if ((data16&0xff) == 0x00) // 16 bit absolute { ext16 = h8_mem_read16(4); sprintf(buffer, "%4.4x ldc.w @%04x, ccr", opcode, ext16); size = 6; } - else if ((data16&0xff) == 0x20) // 24 bit absolute + else if ((data16&0xff) == 0x20) // 24 bit absolute { sdata32 = h8_mem_read32(4) & 0xffffff; sprintf(buffer, "%4.4x ldc.w @%06x, ccr", opcode, sdata32); size = 8; } - else if ((data16&0xff) == 0x80) // 16 bit absolute + else if ((data16&0xff) == 0x80) // 16 bit absolute { ext16 = h8_mem_read16(4); sprintf(buffer, "%4.4x stc.w ccr, @%04x", opcode, ext16); size = 6; } - else if ((data16&0xff) == 0xa0) // 24 bit absolute + else if ((data16&0xff) == 0xa0) // 24 bit absolute { sdata32 = h8_mem_read32(4) & 0xffffff; sprintf(buffer, "%4.4x stc.w ccr, @%06x", opcode, sdata32); @@ -422,13 +422,13 @@ static UINT32 h8disasm_0(UINT32 pc, UINT32 opcode, char *buffer, const UINT8 *op size = 4; switch((data16>>8)&0xff) { - case 0x64: // or.l ERs, ERd + case 0x64: // or.l ERs, ERd sprintf(buffer, "%4.4x or.l %s, %s", opcode, reg_names32[(data16>>4) & 0x7], reg_names32[data16 & 0x7]); break; - case 0x65: // xor.l ERs, ERd + case 0x65: // xor.l ERs, ERd sprintf(buffer, "%4.4x xor.l %s, %s", opcode, reg_names32[(data16>>4) & 0x7], reg_names32[data16 & 0x7]); break; - case 0x66: // and.l ERs, ERd + case 0x66: // and.l ERs, ERd sprintf(buffer, "%4.4x and.l %s, %s", opcode, reg_names32[(data16>>4) & 0x7], reg_names32[data16 & 0x7]); break; default: @@ -448,9 +448,9 @@ static UINT32 h8disasm_0(UINT32 pc, UINT32 opcode, char *buffer, const UINT8 *op sprintf(buffer, "%4.4x stc ccr, %s", opcode, reg_names8[opcode & 0xf]); } else if(((opcode>>4) & 0xf) == 1) // H8S stc exr, rd - { + { sprintf(buffer, "%4.4x stc exr, %s", opcode, reg_names8[opcode & 0xf]); - } + } else { sprintf(buffer, "%4.4x default", opcode); @@ -464,9 +464,9 @@ static UINT32 h8disasm_0(UINT32 pc, UINT32 opcode, char *buffer, const UINT8 *op sprintf(buffer, "%4.4x ldc %s, ccr", opcode, reg_names8[opcode & 0xf]); } else if(((opcode>>4) & 0xf) == 1) // H8S ldr rd, exr - { + { sprintf(buffer, "%4.4x ldc %s, exr", opcode, reg_names8[opcode & 0xf]); - } + } else { sprintf(buffer, "%4.4x default", opcode); @@ -1309,7 +1309,7 @@ static UINT32 h8disasm_6(UINT32 address, UINT32 opcode, char *buffer, const UINT sprintf(buffer, "%4.4x mov.b @%8.8x, %s", opcode, data32&addr_mask, reg_names8[opcode & 0xf]); size = 6; break; - case 0x3: // bclr #imm, imm:32 + case 0x3: // bclr #imm, imm:32 data32=h8_mem_read32(2); data16=h8_mem_read16(6); switch ((data16 >> 8) & 0xff) @@ -1541,7 +1541,7 @@ static UINT32 h8disasm_7(UINT32 address, UINT32 opcode, char *buffer, const UINT size = 4; switch(data16>>8) { - case 0x60: // bset/bnot/bclr.b rn, @erd + case 0x60: // bset/bnot/bclr.b rn, @erd case 0x61: case 0x62: if (((opcode & 0x8f)!=0)||((data16 & 0x0f)!=0)) @@ -1552,7 +1552,7 @@ static UINT32 h8disasm_7(UINT32 address, UINT32 opcode, char *buffer, const UINT sprintf(buffer, "%4.4x %s.b %s, @%s", opcode, bit_instr[(data16>>8)&7], reg_names16[(data16>>4)&0xf], reg_names32[(opcode>>4) & 0x7]); break; - case 0x67: // bst/bist.b #xx:3, @erd + case 0x67: // bst/bist.b #xx:3, @erd if (((opcode & 0x8f)!=0)||((data16 & 0x0f)!=0)) { sprintf(buffer, "%4.4x default", opcode); @@ -1564,7 +1564,7 @@ static UINT32 h8disasm_7(UINT32 address, UINT32 opcode, char *buffer, const UINT sprintf(buffer, "%4.4x bst.b #%1.1x, @%s", opcode, (data16>>4)&7, reg_names32[(opcode>>4) & 0x7]); break; - case 0x70: // bset/bnot/bclr.b #xx:3, @erd + case 0x70: // bset/bnot/bclr.b #xx:3, @erd case 0x71: case 0x72: if (((opcode & 0x8f)!=0)||((data16 & 0x8f)!=0)) @@ -1575,7 +1575,7 @@ static UINT32 h8disasm_7(UINT32 address, UINT32 opcode, char *buffer, const UINT sprintf(buffer, "%4.4x %s.b #%1.1x, @%s", opcode, bit_instr[(data16>>8)&7], (data16>>4)&7, reg_names32[(opcode>>4) & 0x7]); break; - case 0x77: // bld #xx:3, @rd + case 0x77: // bld #xx:3, @rd sprintf(buffer, "%4.4x bld #%d, @%s", opcode, (data16>>4)&7, reg_names32[(opcode>>4) & 0x7]); break; } @@ -1617,4 +1617,3 @@ CPU_DISASSEMBLE(h8_32) { return h8_disasm(buffer, pc, oprom, opram, 0xffffffff); } - diff --git a/src/emu/cpu/h83002/h8ops.h b/src/emu/cpu/h83002/h8ops.h index 6112f3e72a4..23df45a2e1e 100644 --- a/src/emu/cpu/h83002/h8ops.h +++ b/src/emu/cpu/h83002/h8ops.h @@ -334,7 +334,7 @@ static void h8_group0(h83xx_state *h8, UINT16 opcode) break; case 0x6b: - if ((ext16&0xff) == 0x00) // 16 bit absolute + if ((ext16&0xff) == 0x00) // 16 bit absolute { address24=h8_mem_read16(h8, h8->pc); h8->pc += 2; @@ -345,7 +345,7 @@ static void h8_group0(h83xx_state *h8, UINT16 opcode) H8_IFETCH_TIMING(4); H8_BYTE_TIMING(1, address24); } - else if ((ext16&0xff) == 0x20) // 24 bit absolute + else if ((ext16&0xff) == 0x20) // 24 bit absolute { address24=h8_mem_read32(h8, h8->pc); h8->pc += 4; @@ -354,7 +354,7 @@ static void h8_group0(h83xx_state *h8, UINT16 opcode) H8_IFETCH_TIMING(4); H8_BYTE_TIMING(1, address24); } - else if ((ext16&0xff) == 0x80) // 16 bit absolute + else if ((ext16&0xff) == 0x80) // 16 bit absolute { address24=h8_mem_read16(h8, h8->pc); h8->pc += 2; @@ -364,7 +364,7 @@ static void h8_group0(h83xx_state *h8, UINT16 opcode) H8_IFETCH_TIMING(3); H8_BYTE_TIMING(1, address24); } - else if ((ext16&0xff) == 0xa0) // 24 bit absolute + else if ((ext16&0xff) == 0xa0) // 24 bit absolute { address24=h8_mem_read32(h8, h8->pc); h8->pc += 4; @@ -402,13 +402,13 @@ static void h8_group0(h83xx_state *h8, UINT16 opcode) dstreg = ext16 & 0x7; switch((ext16>>8)&0xff) { - case 0x64: // or.l ERs, ERd + case 0x64: // or.l ERs, ERd udata32 = h8_or32(h8, h8_getreg32(h8, (ext16>>4) & 0x7), h8_getreg32(h8, dstreg)); break; - case 0x65: // xor.l ERs, ERd + case 0x65: // xor.l ERs, ERd udata32 = h8_xor32(h8, h8_getreg32(h8, (ext16>>4) & 0x7), h8_getreg32(h8, dstreg)); break; - case 0x66: // and.l ERs, ERd + case 0x66: // and.l ERs, ERd udata32 = h8_and32(h8, h8_getreg32(h8, (ext16>>4) & 0x7), h8_getreg32(h8, dstreg)); break; default: @@ -599,7 +599,7 @@ static void h8_group0(h83xx_state *h8, UINT16 opcode) sdata8 = ((opcode>>4) & 0xf); // check LDM or STM - if (ext16 & 0x80) // STM + if (ext16 & 0x80) // STM { srcreg = (ext16 & 7); for (int i = 0; i <= sdata8; i++) @@ -613,7 +613,7 @@ static void h8_group0(h83xx_state *h8, UINT16 opcode) H8_IOP_TIMING(2); } } - else // LDM + else // LDM { srcreg = (ext16 & 7); for (int i = 0; i <= sdata8; i++) @@ -628,23 +628,23 @@ static void h8_group0(h83xx_state *h8, UINT16 opcode) } } break; - case 0x8: // sleep + case 0x8: // sleep H8_IFETCH_TIMING(1); break; case 0xc: // mulxs ext16 = h8_mem_read16(h8, h8->pc); h8->pc+=2; - if(((ext16>>8) & 0xf) == 0) // .b (8x8 = 16) + if(((ext16>>8) & 0xf) == 0) // .b (8x8 = 16) { - sdata16 = h8_getreg8(h8, (ext16 & 0xf)+8); // Rd - always the low 8 bits of Rd - sdata8 = h8_getreg8(h8, (ext16>>4) & 0xf); // Rs + sdata16 = h8_getreg8(h8, (ext16 & 0xf)+8); // Rd - always the low 8 bits of Rd + sdata8 = h8_getreg8(h8, (ext16>>4) & 0xf); // Rs sdata16 = h8_mulxs8(h8, sdata8, sdata16); h8_setreg16(h8, ext16 & 0xf, sdata16); H8_IFETCH_TIMING(2); H8_IOP_TIMING(12); } - else if(((ext16>>8) & 0xf) == 2) // .w + else if(((ext16>>8) & 0xf) == 2) // .w { sdata32 = h8_getreg32(h8, ext16 & 0x7); sdata16 = h8_getreg16(h8, (ext16>>4) & 0xf); @@ -703,10 +703,10 @@ static void h8_group0(h83xx_state *h8, UINT16 opcode) H8_IFETCH_TIMING(1); } else if(((opcode>>4) & 0xf) == 1) - { + { h8_setreg8(h8, opcode & 0xf, h8_get_exr(h8)); H8_IFETCH_TIMING(1); - } + } else { logerror("H8/3xx: Unk. group 0 2 %x\n", opcode); @@ -722,11 +722,11 @@ static void h8_group0(h83xx_state *h8, UINT16 opcode) H8_IFETCH_TIMING(1); } else if(((opcode>>4) & 0xf) == 1) - { + { udata8 = h8_getreg8(h8, opcode & 0xf); h8_set_exr(h8, udata8); H8_IFETCH_TIMING(1); - } + } else { logerror("H8/3xx: Unk. group 0 3 %x\n", opcode); @@ -1466,40 +1466,40 @@ static void h8_group1(h83xx_state *h8, UINT16 opcode) case 0xb: switch((opcode>>4)& 0xf) { - case 0: // subs.l #1, rN (decrement without touching flags) + case 0: // subs.l #1, rN (decrement without touching flags) dstreg = opcode & 0x7; udata32 = h8_getreg32(h8, dstreg); udata32--; h8_setreg32(h8, dstreg, udata32); H8_IFETCH_TIMING(1); break; - case 5: // dec.w #1, rN + case 5: // dec.w #1, rN dstreg = opcode & 0xf; udata16 = h8_dec16(h8, h8_getreg16(h8, dstreg)); h8_setreg16(h8, dstreg, udata16); H8_IFETCH_TIMING(1); break; - case 7: // dec.l #1, rN + case 7: // dec.l #1, rN dstreg = opcode & 0x7; udata32 = h8_dec32(h8, h8_getreg32(h8, dstreg)); h8_setreg32(h8, dstreg, udata32); H8_IFETCH_TIMING(1); break; - case 8: // subs.l #2, rN (decrement without touching flags) + case 8: // subs.l #2, rN (decrement without touching flags) dstreg = opcode & 0x7; udata32 = h8_getreg32(h8, dstreg); udata32-=2; h8_setreg32(h8, dstreg, udata32); H8_IFETCH_TIMING(1); break; - case 9: // subs.l #4, rN (decrement without touching flags) + case 9: // subs.l #4, rN (decrement without touching flags) dstreg = opcode & 0x7; udata32 = h8_getreg32(h8, dstreg); udata32-=4; h8_setreg32(h8, dstreg, udata32); H8_IFETCH_TIMING(1); break; - case 0xd: // dec.w #2, rN + case 0xd: // dec.w #2, rN dstreg = opcode & 0xf; udata16 = h8_dec16(h8, h8_getreg16(h8, dstreg)); if (h8->h8vflag) @@ -1512,7 +1512,7 @@ static void h8_group1(h83xx_state *h8, UINT16 opcode) h8_setreg16(h8, dstreg, udata16); H8_IFETCH_TIMING(1); break; - case 0xf: // dec.l #2, rN + case 0xf: // dec.l #2, rN dstreg = opcode & 0x7; udata32 = h8_dec32(h8, h8_getreg32(h8, dstreg)); if (h8->h8vflag) @@ -1782,9 +1782,9 @@ static void h8_group6(h83xx_state *h8, UINT16 opcode) switch((opcode>>8)&0xf) { - case 0: udata8 = h8_bset8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8); H8_IFETCH_TIMING(1); break; - case 2: udata8 = h8_bclr8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8); H8_IFETCH_TIMING(1); break; - case 3: h8_btst8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; + case 0: udata8 = h8_bset8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8); H8_IFETCH_TIMING(1); break; + case 2: udata8 = h8_bclr8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8); H8_IFETCH_TIMING(1); break; + case 3: h8_btst8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; default: logerror("H8/3xx: Unk. group 6 def 0-3-0 %x\n", opcode); h8->h8err = 1; @@ -1891,7 +1891,7 @@ static void h8_group6(h83xx_state *h8, UINT16 opcode) H8_IFETCH_TIMING(1); H8_BYTE_TIMING(1, address24); break; - case 0x1: // btst #xx, @aa:16 or btst Rn, @aa:16 + case 0x1: // btst #xx, @aa:16 or btst Rn, @aa:16 sdata16 = h8_mem_read16(h8, h8->pc); h8->pc += 2; address24 = sdata16 & H8_ADDR_MASK; @@ -1934,14 +1934,14 @@ static void h8_group6(h83xx_state *h8, UINT16 opcode) H8_IFETCH_TIMING(2); H8_BYTE_TIMING(1, address24); break; - case 0x3: // bclr #x, @imm:24 + case 0x3: // bclr #x, @imm:24 address24=h8_mem_read32(h8, h8->pc); h8->pc += 4; udata16 = h8_mem_read16(h8, h8->pc); h8->pc += 2; switch ((udata16 >> 8) & 0xff) { - case 0x60 : // bset Rn, @abs:24 + case 0x60 : // bset Rn, @abs:24 udata8 = h8_mem_read8(address24); udata8 = h8_bset8(h8, h8_getreg8(h8, (udata16 >> 4) & 0xf), udata8); h8_mem_write8(address24, udata8); @@ -2188,14 +2188,14 @@ static void h8_group7(h83xx_state *h8, UINT16 opcode) { switch((opcode>>8)&0x7) { - case 0: udata8 = h8_bset8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8); H8_IFETCH_TIMING(1); break; - case 1: udata8 = h8_bnot8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8); H8_IFETCH_TIMING(1); break; - case 2: udata8 = h8_bclr8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8);H8_IFETCH_TIMING(1);break; - case 3: h8_btst8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; - case 4: h8_bor8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; - case 5: h8_bxor8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; - case 6: h8_band8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; - case 7: h8_bld8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; + case 0: udata8 = h8_bset8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8); H8_IFETCH_TIMING(1); break; + case 1: udata8 = h8_bnot8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8); H8_IFETCH_TIMING(1); break; + case 2: udata8 = h8_bclr8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8);H8_IFETCH_TIMING(1);break; + case 3: h8_btst8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; + case 4: h8_bor8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; + case 5: h8_bxor8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; + case 6: h8_band8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; + case 7: h8_bld8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; default: logerror("H8/3xx: Unk. group 7 0-7 def %x\n", opcode); h8->h8err = 1; @@ -2206,7 +2206,7 @@ static void h8_group7(h83xx_state *h8, UINT16 opcode) { switch((opcode>>8)&7) { - case 7: h8_bild8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; + case 7: h8_bild8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break; default: logerror("H8/3xx: Unk. group 7 0-7-1 def %x\n", opcode); h8->h8err = 1; @@ -2283,7 +2283,7 @@ static void h8_group7(h83xx_state *h8, UINT16 opcode) switch((opcode>>4)&7) { - case 0: dst16 = h8_mov16(h8, udata16); h8_setreg16(h8, dstreg, dst16); H8_IFETCH_TIMING(2);break; + case 0: dst16 = h8_mov16(h8, udata16); h8_setreg16(h8, dstreg, dst16); H8_IFETCH_TIMING(2);break; case 1: dst16 = h8_add16(h8, udata16, dst16); h8_setreg16(h8, dstreg, dst16); H8_IFETCH_TIMING(2); break; case 2: h8_cmp16(h8, udata16, dst16); H8_IFETCH_TIMING(2); break; case 3: dst16 = h8_sub16(h8, udata16, dst16); h8_setreg16(h8, dstreg, dst16); H8_IFETCH_TIMING(2); break; @@ -2314,7 +2314,7 @@ static void h8_group7(h83xx_state *h8, UINT16 opcode) switch((opcode>>4)&7) { - case 0: dst32 = h8_mov32(h8, udata32); h8_setreg32(h8, dstreg, dst32); H8_IFETCH_TIMING(3); break; + case 0: dst32 = h8_mov32(h8, udata32); h8_setreg32(h8, dstreg, dst32); H8_IFETCH_TIMING(3); break; case 1: dst32 = h8_add32(h8, udata32, dst32); h8_setreg32(h8, dstreg, dst32); H8_IFETCH_TIMING(3); break; case 2: h8_cmp32(h8, udata32, dst32); H8_IFETCH_TIMING(3); break; case 3: dst32 = h8_sub32(h8, udata32, dst32); h8_setreg32(h8, dstreg, dst32); H8_IFETCH_TIMING(3); break; @@ -2332,7 +2332,7 @@ static void h8_group7(h83xx_state *h8, UINT16 opcode) case 0xb: switch (opcode & 0xff) { - case 0xd4: // eepmov.w + case 0xd4: // eepmov.w { ext16 = h8_mem_read16(h8, h8->pc); h8->pc += 2; @@ -2360,7 +2360,7 @@ static void h8_group7(h83xx_state *h8, UINT16 opcode) } break; - case 0x5c: // eepmov.b + case 0x5c: // eepmov.b { ext16 = h8_mem_read16(h8, h8->pc); h8->pc += 2; @@ -2447,20 +2447,20 @@ static void h8_group7(h83xx_state *h8, UINT16 opcode) { // bset/bnot/bclr.b Rn, @ERd case 0x60: - if (((opcode & 0x8f)!=0)||((ext16 & 0x0f)!=0)) { h8->h8err=1; break; } + if (((opcode & 0x8f)!=0)||((ext16 & 0x0f)!=0)) { h8->h8err=1; break; } h8_mem_write8(address24, h8_bset8(h8, h8_getreg16(h8, (ext16>>4)&0xf)&7, h8_mem_read8(address24))); break; case 0x61: - if (((opcode & 0x8f)!=0)||((ext16 & 0x0f)!=0)) { h8->h8err=1; break; } + if (((opcode & 0x8f)!=0)||((ext16 & 0x0f)!=0)) { h8->h8err=1; break; } h8_mem_write8(address24, h8_bnot8(h8, h8_getreg16(h8, (ext16>>4)&0xf)&7, h8_mem_read8(address24))); break; case 0x62: - if (((opcode & 0x8f)!=0)||((ext16 & 0x0f)!=0)) { h8->h8err=1; break; } + if (((opcode & 0x8f)!=0)||((ext16 & 0x0f)!=0)) { h8->h8err=1; break; } h8_mem_write8(address24, h8_bclr8(h8, h8_getreg16(h8, (ext16>>4)&0xf)&7, h8_mem_read8(address24))); break; - case 0x67: // bst/bist.b #Imm:3, @ERd - if (((opcode & 0x8f)!=0)||((ext16 & 0x0f)!=0)) { h8->h8err=1; break; } + case 0x67: // bst/bist.b #Imm:3, @ERd + if (((opcode & 0x8f)!=0)||((ext16 & 0x0f)!=0)) { h8->h8err=1; break; } if ((ext16 & 0x80)!=0) { h8_mem_write8(address24, h8_bist8(h8, (ext16>>4)&7, h8_mem_read8(address24))); @@ -2473,15 +2473,15 @@ static void h8_group7(h83xx_state *h8, UINT16 opcode) // bset/bnot/bclr.b #Imm:3, @ERd case 0x70: - if (((opcode & 0x8f)!=0)||((ext16 & 0x8f)!=0)) { h8->h8err=1; break; } + if (((opcode & 0x8f)!=0)||((ext16 & 0x8f)!=0)) { h8->h8err=1; break; } h8_mem_write8(address24, h8_bset8(h8, (ext16>>4)&7, h8_mem_read8(address24))); break; case 0x71: - if (((opcode & 0x8f)!=0)||((ext16 & 0x8f)!=0)) { h8->h8err=1; break; } + if (((opcode & 0x8f)!=0)||((ext16 & 0x8f)!=0)) { h8->h8err=1; break; } h8_mem_write8(address24, h8_bnot8(h8, (ext16>>4)&7, h8_mem_read8(address24))); break; case 0x72: - if (((opcode & 0x8f)!=0)||((ext16 & 0x8f)!=0)) { h8->h8err=1; break; } + if (((opcode & 0x8f)!=0)||((ext16 & 0x8f)!=0)) { h8->h8err=1; break; } h8_mem_write8(address24, h8_bclr8(h8, (ext16>>4)&7, h8_mem_read8(address24))); break; } @@ -4260,4 +4260,3 @@ static int h8_branch(h83xx_state *h8, UINT8 condition) } return taken; } - diff --git a/src/emu/cpu/h83002/h8periph.c b/src/emu/cpu/h83002/h8periph.c index a9c292b2742..edd9d651275 100644 --- a/src/emu/cpu/h83002/h8periph.c +++ b/src/emu/cpu/h83002/h8periph.c @@ -13,25 +13,25 @@ #include "h8.h" #include "h8priv.h" -#define H8_REG_START (0x00ffff10) +#define H8_REG_START (0x00ffff10) // timer registers -#define TSTR (0x60) -#define TIER0 (0x66) +#define TSTR (0x60) +#define TIER0 (0x66) #define TIER1 (0x70) #define TIER2 (0x7a) #define TIER3 (0x84) #define TIER4 (0x94) -#define TSR0 (0x67) -#define TSR1 (0x71) -#define TSR2 (0x7b) -#define TSR3 (0x85) -#define TSR4 (0x95) -#define TCR0 (0x64) -#define TCR1 (0x6e) -#define TCR2 (0x78) -#define TCR3 (0x82) -#define TCR4 (0x92) +#define TSR0 (0x67) +#define TSR1 (0x71) +#define TSR2 (0x7b) +#define TSR3 (0x85) +#define TSR4 (0x95) +#define TCR0 (0x64) +#define TCR1 (0x6e) +#define TCR2 (0x78) +#define TCR3 (0x82) +#define TCR4 (0x92) static const UINT8 tsr[5] = { TSR0, TSR1, TSR2, TSR3, TSR4 }; static const UINT8 tier[5] = { TIER0, TIER1, TIER2, TIER3, TIER4 }; @@ -292,7 +292,7 @@ static UINT8 h8_ISR_r(h83xx_state *h8) int i; for (i = 0; i < 6; i++) - if (h8->irq_req[0] & (1 << (12+i))) res |= (1 << i); + if (h8->irq_req[0] & (1 << (12+i))) res |= (1 << i); return res; } @@ -301,7 +301,7 @@ static void h8_ISR_w(h83xx_state *h8, UINT8 val) { int i; for (i = 0; i < 6; i++) - if ((~val) & (1 << i)) h8->irq_req[0] &= ~(1 << (12+i)); + if ((~val) & (1 << i)) h8->irq_req[0] &= ~(1 << (12+i)); } @@ -324,14 +324,14 @@ UINT8 h8_register_read8(h83xx_state *h8, UINT32 address) { case 0xb4: // serial port A status val = h8->per_regs[reg]; - val |= 0xc4; // transmit finished, receive ready, no errors + val |= 0xc4; // transmit finished, receive ready, no errors break; case 0xb5: // serial port A receive val = h8->io->read_byte(H8_SERIAL_0); break; case 0xbc: // serial port B status val = h8->per_regs[reg]; - val |= 0xc4; // transmit finished, receive ready, no errors + val |= 0xc4; // transmit finished, receive ready, no errors break; case 0xbd: // serial port B receive val = h8->io->read_byte(H8_SERIAL_1); @@ -360,28 +360,28 @@ UINT8 h8_register_read8(h83xx_state *h8, UINT32 address) case 0xe7: val = h8->io->read_byte(H8_ADC_3_L); break; - case 0xe8: // adc status + case 0xe8: // adc status val = 0x80; break; - case 0xc7: // port 4 data + case 0xc7: // port 4 data val = h8->io->read_byte(H8_PORT_4); break; - case 0xcb: // port 6 data + case 0xcb: // port 6 data val = h8->io->read_byte(H8_PORT_6); break; - case 0xce: // port 7 data + case 0xce: // port 7 data val = h8->io->read_byte(H8_PORT_7); break; - case 0xcf: // port 8 data + case 0xcf: // port 8 data val = h8->io->read_byte(H8_PORT_8); break; - case 0xd2: // port 9 data + case 0xd2: // port 9 data val = h8->io->read_byte(H8_PORT_9); break; - case 0xd3: // port a data + case 0xd3: // port a data val = h8->io->read_byte(H8_PORT_A); break; - case 0xd6: // port b data + case 0xd6: // port b data val = h8->io->read_byte(H8_PORT_B); break; case 0xf6: @@ -412,12 +412,12 @@ void h8_register_write8(h83xx_state *h8, UINT32 address, UINT8 val) switch (reg) { - case 0xb3: // serial 0 send + case 0xb3: // serial 0 send h8->io->write_byte(H8_SERIAL_0, val); h8_3002_InterruptRequest(h8, 54, 1); h8_3002_InterruptRequest(h8, 55, 1); break; - case 0xbb: // serial 1 send + case 0xbb: // serial 1 send h8->io->write_byte(H8_SERIAL_1, val); h8_3002_InterruptRequest(h8, 58, 1); h8_3002_InterruptRequest(h8, 59, 1); @@ -425,22 +425,22 @@ void h8_register_write8(h83xx_state *h8, UINT32 address, UINT8 val) case 0xc7: h8->io->write_byte(H8_PORT_4, val); break; - case 0xcb: // port 6 data + case 0xcb: // port 6 data h8->io->write_byte(H8_PORT_6, val); break; - case 0xce: // port 7 data + case 0xce: // port 7 data h8->io->write_byte(H8_PORT_7, val); break; - case 0xcf: // port 8 data + case 0xcf: // port 8 data h8->io->write_byte(H8_PORT_8, val); break; - case 0xd2: // port 9 data + case 0xd2: // port 9 data h8->io->write_byte(H8_PORT_9, val); break; - case 0xd3: // port a data + case 0xd3: // port a data h8->io->write_byte(H8_PORT_A, val); break; - case 0xd6: // port b data + case 0xd6: // port b data h8->io->write_byte(H8_PORT_B, val); break; case 0xf6: @@ -492,7 +492,7 @@ static void h8itu_3007_timer_expire(h83xx_state *h8, int tnum) } h8->per_regs[0x64] |= 1<<tnum; - if(h8->per_regs[0x64] & (4<<tnum)) // interrupt enable + if(h8->per_regs[0x64] & (4<<tnum)) // interrupt enable { //logerror("h8/3007 timer %d GRA INTERRUPT\n",tnum); h8_3002_InterruptRequest(h8, 24+tnum*4, 1); @@ -514,7 +514,7 @@ static void h8itu_3007_timer_expire(h83xx_state *h8, int tnum) } h8->per_regs[0x65] |= 1<<tnum; - if(h8->per_regs[0x65] & (4<<tnum)) // interrupt enable + if(h8->per_regs[0x65] & (4<<tnum)) // interrupt enable { //logerror("h8/3007 timer %d GRB INTERRUPT\n",tnum); h8_3002_InterruptRequest(h8, 25+tnum*4, 1); @@ -525,7 +525,7 @@ static void h8itu_3007_timer_expire(h83xx_state *h8, int tnum) { //logerror("h8/3007 timer %d OVF match, restarting\n",tnum); h8->per_regs[0x66] |= 1<<tnum; - if(h8->per_regs[0x66] & (4<<tnum)) // interrupt enable + if(h8->per_regs[0x66] & (4<<tnum)) // interrupt enable { //logerror("h8/3007 timer %d OVF INTERRUPT\n",tnum); h8_3002_InterruptRequest(h8, 26+tnum*4, 1); @@ -619,14 +619,14 @@ UINT8 h8_3007_register_read8(h83xx_state *h8, UINT32 address) { case 0xb4: // serial port A status val = h8->per_regs[reg]; - val |= 0xc4; // transmit finished, receive ready, no errors + val |= 0xc4; // transmit finished, receive ready, no errors break; case 0xb5: // serial port A receive val = h8->io->read_byte(H8_SERIAL_0); break; case 0xbc: // serial port B status val = h8->per_regs[reg]; - val |= 0xc4; // transmit finished, receive ready, no errors + val |= 0xc4; // transmit finished, receive ready, no errors break; case 0xbd: // serial port B receive val = h8->io->read_byte(H8_SERIAL_1); @@ -655,29 +655,29 @@ UINT8 h8_3007_register_read8(h83xx_state *h8, UINT32 address) case 0xe7: val = h8->io->read_byte(H8_ADC_3_L); break; - case 0xe8: // adc status + case 0xe8: // adc status val = 0x80; break; - case 0xd3: // port 4 data + case 0xd3: // port 4 data val = h8->io->read_byte(H8_PORT_4); break; - case 0xd5: // port 6 data + case 0xd5: // port 6 data val = h8->io->read_byte(H8_PORT_6); break; - case 0xd6: // port 7 data + case 0xd6: // port 7 data val = h8->io->read_byte(H8_PORT_7); break; - case 0xd7: // port 8 data + case 0xd7: // port 8 data val = h8->io->read_byte(H8_PORT_8); break; - case 0xd8: // port 9 data + case 0xd8: // port 9 data val = h8->io->read_byte(H8_PORT_9); break; - case 0xd9: // port a data + case 0xd9: // port a data val = h8->io->read_byte(H8_PORT_A); break; - case 0xda: // port b data + case 0xda: // port b data val = h8->io->read_byte(H8_PORT_B); break; default: @@ -716,22 +716,22 @@ void h8_3007_register_write8(h83xx_state *h8, UINT32 address, UINT8 val) case 0xd3: h8->io->write_byte(H8_PORT_4, val); break; - case 0xd5: // port 6 data + case 0xd5: // port 6 data h8->io->write_byte(H8_PORT_6, val); break; - case 0xd6: // port 7 data + case 0xd6: // port 7 data h8->io->write_byte(H8_PORT_7, val); break; - case 0xd7: // port 8 data + case 0xd7: // port 8 data h8->io->write_byte(H8_PORT_8, val); break; - case 0xd8: // port 9 data + case 0xd8: // port 9 data h8->io->write_byte(H8_PORT_9, val); break; - case 0xd9: // port a data + case 0xd9: // port a data h8->io->write_byte(H8_PORT_A, val); break; - case 0xda: // port b data + case 0xda: // port b data h8->io->write_byte(H8_PORT_B, val); break; } @@ -742,9 +742,9 @@ UINT8 h8_3007_register1_read8(h83xx_state *h8, UINT32 address) { switch (address) { - case 0xfee012: return h8->per_regs[0xF2]; // SYSCR - case 0xfee016: return h8_ISR_r(h8); // ISR - case 0xfee018: return h8->per_regs[0xF8]; // IPRA + case 0xfee012: return h8->per_regs[0xF2]; // SYSCR + case 0xfee016: return h8_ISR_r(h8); // ISR + case 0xfee018: return h8->per_regs[0xF8]; // IPRA } logerror("cpu '%s' (PC=%08X): unmapped I/O(1) byte read from %08X\n",h8->device->tag(),h8->pc,address); @@ -755,9 +755,9 @@ void h8_3007_register1_write8(h83xx_state *h8, UINT32 address, UINT8 val) { switch (address) { - case 0xfee012: h8->per_regs[0xF2] = val; return; // SYSCR - case 0xfee016: h8_ISR_w(h8, val); return; // ISR - case 0xfee018: h8->per_regs[0xF8] = val; return; // IPRA + case 0xfee012: h8->per_regs[0xF2] = val; return; // SYSCR + case 0xfee016: h8_ISR_w(h8, val); return; // ISR + case 0xfee018: h8->per_regs[0xF8] = val; return; // IPRA } logerror("cpu '%s' (PC=%08X): unmapped I/O(1) byte write to %08X = %02X\n",h8->device->tag(),h8->pc,address,val); } diff --git a/src/emu/cpu/h83002/h8priv.h b/src/emu/cpu/h83002/h8priv.h index c3f65de49b5..3b2c7369fd6 100644 --- a/src/emu/cpu/h83002/h8priv.h +++ b/src/emu/cpu/h83002/h8priv.h @@ -51,7 +51,7 @@ struct h83xx_state UINT8 h8uflag, h8uiflag; UINT8 incheckirqs; - bool has_exr; + bool has_exr; device_irq_acknowledge_callback irq_cb; legacy_cpu_device *device; @@ -76,12 +76,12 @@ struct h83xx_state H8S2XXX_TPU tpu[6]; H8S2XXX_SCI sci[3]; - int tpu_max; + int tpu_max; - UINT8 ddrs[H8_MAX_PORTS], drs[H8_MAX_PORTS], pcrs[H8_MAX_PORTS], odrs[H8_MAX_PORTS]; + UINT8 ddrs[H8_MAX_PORTS], drs[H8_MAX_PORTS], pcrs[H8_MAX_PORTS], odrs[H8_MAX_PORTS]; int mode_8bit; - bool has_h8speriphs; + bool has_h8speriphs; }; // defined in h8speriph.c @@ -95,14 +95,14 @@ INLINE h83xx_state *get_safe_token(device_t *device) { assert(device != NULL); assert(device->type() == H83002 || - device->type() == H83007 || - device->type() == H83044 || - device->type() == H83334 || - device->type() == H8S2241 || - device->type() == H8S2246 || - device->type() == H8S2323 || - device->type() == H8S2394 || - device->type() == H8S2655); + device->type() == H83007 || + device->type() == H83044 || + device->type() == H83334 || + device->type() == H8S2241 || + device->type() == H8S2246 || + device->type() == H8S2323 || + device->type() == H8S2394 || + device->type() == H8S2655); return (h83xx_state *)downcast<legacy_cpu_device *>(device)->token(); } diff --git a/src/emu/cpu/h83002/h8speriph.c b/src/emu/cpu/h83002/h8speriph.c index a755972f27c..97cdb25b77d 100644 --- a/src/emu/cpu/h83002/h8speriph.c +++ b/src/emu/cpu/h83002/h8speriph.c @@ -95,10 +95,10 @@ const UINT8 H8S_RESET_H8S_IO_2323[0x1C0] = // values from "rej09b0220_h8s2329.pd 0x00, 0xC0, 0x00, 0x00, 0x40, 0xC0, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, // FFF0 }; -#define SCR_TIE 0x80 -#define SCR_RIE 0x40 -#define SCR_TE 0x20 -#define SCR_RE 0x10 +#define SCR_TIE 0x80 +#define SCR_RIE 0x40 +#define SCR_TE 0x20 +#define SCR_RE 0x10 #define SSR_TDRE 0x80 #define SSR_RDRF 0x40 @@ -184,42 +184,42 @@ enum PIN_PG0, PIN_PG1, PIN_PG2, PIN_PG3, PIN_PG4 }; -#define PIN_TIOCA0 PIN_P10 -#define PIN_TIOCB0 PIN_P11 -#define PIN_TIOCC0 PIN_P12 -#define PIN_TIOCD0 PIN_P13 -#define PIN_TIOCA1 PIN_P14 -#define PIN_TIOCB1 PIN_P15 -#define PIN_TIOCA2 PIN_P16 -#define PIN_TIOCB2 PIN_P17 - -#define PIN_TCLKA PIN_P12 -#define PIN_TCLKB PIN_P13 -#define PIN_TCLKC PIN_P15 -#define PIN_TCLKD PIN_P17 - -#define PIN_TXD0 PIN_P30 -#define PIN_TXD1 PIN_P31 -#define PIN_RXD0 PIN_P32 -#define PIN_RXD1 PIN_P33 -#define PIN_SCK0 PIN_P34 -#define PIN_SCK1 PIN_P35 - -#define PIN_TIOCA3 PIN_P20 -#define PIN_TIOCB3 PIN_P21 -#define PIN_TIOCC3 PIN_P22 -#define PIN_TIOCD3 PIN_P23 -#define PIN_TIOCA4 PIN_P24 -#define PIN_TIOCB4 PIN_P25 -#define PIN_TIOCA5 PIN_P26 -#define PIN_TIOCB5 PIN_P27 - -#define PIN_TMRI0 PIN_P22 -#define PIN_TMCI0 PIN_P23 -#define PIN_TMRI1 PIN_P24 -#define PIN_TMCI1 PIN_P25 -#define PIN_TMO0 PIN_P26 -#define PIN_TMO1 PIN_P27 +#define PIN_TIOCA0 PIN_P10 +#define PIN_TIOCB0 PIN_P11 +#define PIN_TIOCC0 PIN_P12 +#define PIN_TIOCD0 PIN_P13 +#define PIN_TIOCA1 PIN_P14 +#define PIN_TIOCB1 PIN_P15 +#define PIN_TIOCA2 PIN_P16 +#define PIN_TIOCB2 PIN_P17 + +#define PIN_TCLKA PIN_P12 +#define PIN_TCLKB PIN_P13 +#define PIN_TCLKC PIN_P15 +#define PIN_TCLKD PIN_P17 + +#define PIN_TXD0 PIN_P30 +#define PIN_TXD1 PIN_P31 +#define PIN_RXD0 PIN_P32 +#define PIN_RXD1 PIN_P33 +#define PIN_SCK0 PIN_P34 +#define PIN_SCK1 PIN_P35 + +#define PIN_TIOCA3 PIN_P20 +#define PIN_TIOCB3 PIN_P21 +#define PIN_TIOCC3 PIN_P22 +#define PIN_TIOCD3 PIN_P23 +#define PIN_TIOCA4 PIN_P24 +#define PIN_TIOCB4 PIN_P25 +#define PIN_TIOCA5 PIN_P26 +#define PIN_TIOCB5 PIN_P27 + +#define PIN_TMRI0 PIN_P22 +#define PIN_TMCI0 PIN_P23 +#define PIN_TMRI1 PIN_P24 +#define PIN_TMCI1 PIN_P25 +#define PIN_TMO0 PIN_P26 +#define PIN_TMO1 PIN_P27 const int TPU_0_DIV[] = { 1, 4, 16, 64, 0, 0, 0,0 }; const int TPU_1_DIV[] = { 1, 4, 16, 64, 0, 0, 256, 0 }; @@ -1319,7 +1319,7 @@ void h8s_onchip_reg_write_8(h83xx_state *h8, int offset, UINT8 data) case H8S_IO_BRR0 : h8->per_regs[offset] = data; h8s_sci_rate(h8, 0); h8s_sci_start(h8, 0); break; // SCI 1 case H8S_IO_SSR1 : h8->per_regs[offset] = data; if ((data & H8S_SSR_TDRE) == 0) h8s_sci_execute(h8, 1); break; - case H8S_IO_SCR1 : h8->per_regs[offset] = data; if (data & H8S_SCR_RIE) h8s2xxx_interrupt_request(h8, h8s_sci_entry(1)->int_rx); break; + case H8S_IO_SCR1 : h8->per_regs[offset] = data; if (data & H8S_SCR_RIE) h8s2xxx_interrupt_request(h8, h8s_sci_entry(1)->int_rx); break; case H8S_IO_BRR1 : h8->per_regs[offset] = data; h8s_sci_rate(h8, 1); h8s_sci_start(h8, 1); break; // SCI 2 case H8S_IO_SSR2 : h8->per_regs[offset] = data; if ((data & H8S_SSR_TDRE) == 0) h8s_sci_execute(h8, 2); break; @@ -1390,7 +1390,7 @@ void h8s_onchip_reg_write_8_ddr(h83xx_state *h8, int offset, UINT8 data) case H8S_IO_BRR0 : h8->per_regs[offset] = data; h8s_sci_rate(h8, 0); h8s_sci_start(h8, 0); break; // SCI 1 case H8S_IO_SSR1 : h8->per_regs[offset] = data; if ((data & H8S_SSR_TDRE) == 0) h8s_sci_execute(h8, 1); break; - case H8S_IO_SCR1 : h8->per_regs[offset] = data; if (data & H8S_SCR_RIE) h8s2xxx_interrupt_request(h8, h8s_sci_entry(1)->int_rx); break; + case H8S_IO_SCR1 : h8->per_regs[offset] = data; if (data & H8S_SCR_RIE) h8s2xxx_interrupt_request(h8, h8s_sci_entry(1)->int_rx); break; case H8S_IO_BRR1 : h8->per_regs[offset] = data; h8s_sci_rate(h8, 1); h8s_sci_start(h8, 1); break; // SCI 2 case H8S_IO_SSR2 : h8->per_regs[offset] = data; if ((data & H8S_SSR_TDRE) == 0) h8s_sci_execute(h8, 2); break; @@ -1408,28 +1408,28 @@ void h8s_onchip_reg_write_8_ddr(h83xx_state *h8, int offset, UINT8 data) case H8S_IO_TCORB1 : h8s_tmr_x_write_tcorb( h8, 1, data); break; case H8S_IO_IER: - case H8S_IO_IFR: + case H8S_IO_IFR: h8->per_regs[offset] = data; - break; + break; - case H8S_IO_P1DDR : case H8S_IO_P2DDR : case H8S_IO_P3DDR : case H8S_IO_P5DDR : case H8S_IO_P6DDR : - case H8S_IO_PADDR : case H8S_IO_PBDDR : case H8S_IO_PCDDR : case H8S_IO_PDDDR : case H8S_IO_PEDDR : - case H8S_IO_PFDDR : case H8S_IO_PGDDR : - h8->ddrs[offset - H8S_IO_P1DDR] = data; - break; + case H8S_IO_P1DDR : case H8S_IO_P2DDR : case H8S_IO_P3DDR : case H8S_IO_P5DDR : case H8S_IO_P6DDR : + case H8S_IO_PADDR : case H8S_IO_PBDDR : case H8S_IO_PCDDR : case H8S_IO_PDDDR : case H8S_IO_PEDDR : + case H8S_IO_PFDDR : case H8S_IO_PGDDR : + h8->ddrs[offset - H8S_IO_P1DDR] = data; + break; case H8S_IO_P1DR : case H8S_IO_P2DR : case H8S_IO_P3DR : case H8S_IO_P5DR : case H8S_IO_P6DR : case H8S_IO_PADR : case H8S_IO_PBDR : case H8S_IO_PCDR : case H8S_IO_PDDR : case H8S_IO_PEDR : - case H8S_IO_PFDR : case H8S_IO_PGDR : - { - int port = (offset - H8S_IO_P1DR); - h8->drs[port] = data; - h8->io->write_byte(H8_PORT_1 + port, data & h8->ddrs[port]); - } - break; + case H8S_IO_PFDR : case H8S_IO_PGDR : + { + int port = (offset - H8S_IO_P1DR); + h8->drs[port] = data; + h8->io->write_byte(H8_PORT_1 + port, data & h8->ddrs[port]); + } + break; // ... - // TPU + // TPU case H8S_IO_TSTR : h8s_tpu_write_tstr( h8, data); break; // DMA case H8S_IO_DMABCRL : @@ -1532,9 +1532,9 @@ UINT8 h8s_onchip_reg_read_8(h83xx_state *h8, int offset) case H8S_IO_PORTA : case H8S_IO_PORTB : case H8S_IO_PORTC : case H8S_IO_PORTD : case H8S_IO_PORTE : case H8S_IO_PORTF : data = h8->io->read_byte( H8S_IO_ADDR( offset)); break; // ... - case H8S_IO_P1DR : case H8S_IO_P2DR : case H8S_IO_P3DR : case H8S_IO_P4DR : case H8S_IO_P5DR : - case H8S_IO_PADR : case H8S_IO_PBDR : case H8S_IO_PCDR : case H8S_IO_PDDR : case H8S_IO_PEDR : - case H8S_IO_PFDR : case H8S_IO_PGDR : data = h8->io->read_byte( H8S_IO_ADDR( offset)); break; + case H8S_IO_P1DR : case H8S_IO_P2DR : case H8S_IO_P3DR : case H8S_IO_P4DR : case H8S_IO_P5DR : + case H8S_IO_PADR : case H8S_IO_PBDR : case H8S_IO_PCDR : case H8S_IO_PDDR : case H8S_IO_PEDR : + case H8S_IO_PFDR : case H8S_IO_PGDR : data = h8->io->read_byte( H8S_IO_ADDR( offset)); break; // TMR 0 case H8S_IO_TCNT0 : data = h8s_tmr_x_read_tcnt( h8, 0); break; // TMR 1 @@ -1552,7 +1552,7 @@ UINT8 h8s_onchip_reg_read_8_ddr(h83xx_state *h8, int offset) UINT8 data; switch (offset) { - #if 0 + #if 0 // SCI 0 case H8S_IO_SSR0 : data = H8S_SSR_TDRE | H8S_SSR_TEND; break; case H8S_IO_RDR0 : data = h8->io->read_byte( H8S_IO_ADDR( offset)); break; @@ -1565,38 +1565,38 @@ UINT8 h8s_onchip_reg_read_8_ddr(h83xx_state *h8, int offset) if (!(h8->per_regs[H8S_IO_SCR2] & H8S_SCR_TE)) data |= H8S_SSR_TDRE; } break; - #endif - - case H8S_IO_IFR: - data = h8->per_regs[offset]; - break; - - // ports - case H8S_IO_PORT1 : case H8S_IO_PORT2 : case H8S_IO_PORT3 : case H8S_IO_PORT4 : case H8S_IO_PORT5 : case H8S_IO_PORT6 : - case H8S_IO_PORTA : case H8S_IO_PORTB : case H8S_IO_PORTC : case H8S_IO_PORTD : case H8S_IO_PORTE : case H8S_IO_PORTF : - case H8S_IO_PORTG : - { - int port = (offset - H8S_IO_PORT1); - data = h8->drs[port] & h8->ddrs[port]; // result = data register for DDR "1" bits, live read for DDR "0" bits - data |= (h8->io->read_byte(H8_PORT_1 + port) & (h8->ddrs[port] ^ 0xff)); - } - break; + #endif + + case H8S_IO_IFR: + data = h8->per_regs[offset]; + break; + + // ports + case H8S_IO_PORT1 : case H8S_IO_PORT2 : case H8S_IO_PORT3 : case H8S_IO_PORT4 : case H8S_IO_PORT5 : case H8S_IO_PORT6 : + case H8S_IO_PORTA : case H8S_IO_PORTB : case H8S_IO_PORTC : case H8S_IO_PORTD : case H8S_IO_PORTE : case H8S_IO_PORTF : + case H8S_IO_PORTG : + { + int port = (offset - H8S_IO_PORT1); + data = h8->drs[port] & h8->ddrs[port]; // result = data register for DDR "1" bits, live read for DDR "0" bits + data |= (h8->io->read_byte(H8_PORT_1 + port) & (h8->ddrs[port] ^ 0xff)); + } + break; // the manual is ambivalent, but the invqix code very much implies that reading DR also reads the pin states - case H8S_IO_P1DR : case H8S_IO_P2DR : case H8S_IO_P3DR : case H8S_IO_P5DR : case H8S_IO_P6DR : - case H8S_IO_PADR : case H8S_IO_PBDR : case H8S_IO_PCDR : case H8S_IO_PDDR : case H8S_IO_PEDR : - case H8S_IO_PFDR : case H8S_IO_PGDR : - { - int port = (offset - H8S_IO_P1DR); - data = h8->drs[port] & h8->ddrs[port]; - data |= (h8->io->read_byte(H8_PORT_1 + port) & (h8->ddrs[port] ^ 0xff)); - } - break; + case H8S_IO_P1DR : case H8S_IO_P2DR : case H8S_IO_P3DR : case H8S_IO_P5DR : case H8S_IO_P6DR : + case H8S_IO_PADR : case H8S_IO_PBDR : case H8S_IO_PCDR : case H8S_IO_PDDR : case H8S_IO_PEDR : + case H8S_IO_PFDR : case H8S_IO_PGDR : + { + int port = (offset - H8S_IO_P1DR); + data = h8->drs[port] & h8->ddrs[port]; + data |= (h8->io->read_byte(H8_PORT_1 + port) & (h8->ddrs[port] ^ 0xff)); + } + break; // ADCSR - case H8S_IO_ADCSR: data = ADCSR_ADF; break; + case H8S_IO_ADCSR: data = ADCSR_ADF; break; - // TMR 0 + // TMR 0 case H8S_IO_TCNT0 : data = h8s_tmr_x_read_tcnt( h8, 0); break; // TMR 1 case H8S_IO_TCNT1 : data = h8s_tmr_x_read_tcnt( h8, 1); break; @@ -1741,4 +1741,3 @@ UINT16 h8s2655_per_regs_read_16(h83xx_state *h8, int offset) { return h8s_onchip_reg_read_16(h8, offset); } - |