diff options
Diffstat (limited to 'src/emu/cpu/am29000/am29ops.h')
-rw-r--r-- | src/emu/cpu/am29000/am29ops.h | 208 |
1 files changed, 104 insertions, 104 deletions
diff --git a/src/emu/cpu/am29000/am29ops.h b/src/emu/cpu/am29000/am29ops.h index d496bbb63e2..49a75fe7b91 100644 --- a/src/emu/cpu/am29000/am29ops.h +++ b/src/emu/cpu/am29000/am29ops.h @@ -9,52 +9,52 @@ DEFINES ***************************************************************************/ -#define IFLAG_ILLEGAL (1 << 0) -#define IFLAG_SUPERVISOR_ONLY (1 << 1) -#define IFLAG_RA_PRESENT (1 << 2) -#define IFLAG_RB_PRESENT (1 << 3) -#define IFLAG_RC_PRESENT (1 << 4) - -#define IFLAG_SPR_ACCESS (1 << 6) -#define IFLAG_MEMORY_ACCESS (1 << 8) -#define IFLAG_CONTROL (1 << 9) - - -#define GET_RA_VAL (am29000->r[RA]) -#define GET_RB_VAL (am29000->r[RB]) - -#define RA (get_abs_reg(am29000, am29000->exec_ir >> 8, am29000->ipa)) -#define RB (get_abs_reg(am29000, am29000->exec_ir >> 0, am29000->ipb)) -#define RC (get_abs_reg(am29000, am29000->exec_ir >> 16, am29000->ipc)) - -#define INST_SA ((am29000->exec_ir >> 8) & 0xff) -#define INST_VN ((am29000->exec_ir >> 16) & 0xff) -#define INST_M_BIT (am29000->exec_ir & (1 << 24)) -#define INST_CE_BIT (am29000->exec_ir & (1 << 23)) -#define INST_AS_BIT (am29000->exec_ir & (1 << 22)) -#define INST_PA_BIT (am29000->exec_ir & (1 << 21)) -#define INST_SB_BIT (am29000->exec_ir & (1 << 20)) -#define INST_UA_BIT (am29000->exec_ir & (1 << 19)) -#define INST_OPT_MASK (7) -#define INST_OPT_SHIFT (16) -#define INST_OPT_FIELD (((am29000->exec_ir) >> INST_OPT_SHIFT) & INST_OPT_MASK) -#define INST_CNTL_MASK (0x7f) -#define INST_CNTL_SHIFT (16) - -#define I8 (am29000->exec_ir & 0xff) -#define I16 (((am29000->exec_ir >> 8) & 0xff00) | (am29000->exec_ir & 0xff)) -#define I16_ZEX ((UINT32)(I16)) -#define I16_SEX ((INT32)(INT16)I16) -#define I16_OEX (0xffff0000 | I16) - -#define JMP_ZEX (I16 << 2) -#define JMP_SEX ((INT32)(INT16)(((am29000->exec_ir >> 8) & 0xff00) | (am29000->exec_ir & 0xff)) << 2) - -#define BOOLEAN_MASK (1 << 31) -#define BOOLEAN_TRUE (1 << 31) -#define BOOLEAN_FALSE (0) - -#define UNHANDLED_OP fatalerror("Am29000: Unhandled inst %s at %x\n", __FUNCTION__, am29000->exec_pc); +#define IFLAG_ILLEGAL (1 << 0) +#define IFLAG_SUPERVISOR_ONLY (1 << 1) +#define IFLAG_RA_PRESENT (1 << 2) +#define IFLAG_RB_PRESENT (1 << 3) +#define IFLAG_RC_PRESENT (1 << 4) + +#define IFLAG_SPR_ACCESS (1 << 6) +#define IFLAG_MEMORY_ACCESS (1 << 8) +#define IFLAG_CONTROL (1 << 9) + + +#define GET_RA_VAL (am29000->r[RA]) +#define GET_RB_VAL (am29000->r[RB]) + +#define RA (get_abs_reg(am29000, am29000->exec_ir >> 8, am29000->ipa)) +#define RB (get_abs_reg(am29000, am29000->exec_ir >> 0, am29000->ipb)) +#define RC (get_abs_reg(am29000, am29000->exec_ir >> 16, am29000->ipc)) + +#define INST_SA ((am29000->exec_ir >> 8) & 0xff) +#define INST_VN ((am29000->exec_ir >> 16) & 0xff) +#define INST_M_BIT (am29000->exec_ir & (1 << 24)) +#define INST_CE_BIT (am29000->exec_ir & (1 << 23)) +#define INST_AS_BIT (am29000->exec_ir & (1 << 22)) +#define INST_PA_BIT (am29000->exec_ir & (1 << 21)) +#define INST_SB_BIT (am29000->exec_ir & (1 << 20)) +#define INST_UA_BIT (am29000->exec_ir & (1 << 19)) +#define INST_OPT_MASK (7) +#define INST_OPT_SHIFT (16) +#define INST_OPT_FIELD (((am29000->exec_ir) >> INST_OPT_SHIFT) & INST_OPT_MASK) +#define INST_CNTL_MASK (0x7f) +#define INST_CNTL_SHIFT (16) + +#define I8 (am29000->exec_ir & 0xff) +#define I16 (((am29000->exec_ir >> 8) & 0xff00) | (am29000->exec_ir & 0xff)) +#define I16_ZEX ((UINT32)(I16)) +#define I16_SEX ((INT32)(INT16)I16) +#define I16_OEX (0xffff0000 | I16) + +#define JMP_ZEX (I16 << 2) +#define JMP_SEX ((INT32)(INT16)(((am29000->exec_ir >> 8) & 0xff00) | (am29000->exec_ir & 0xff)) << 2) + +#define BOOLEAN_MASK (1 << 31) +#define BOOLEAN_TRUE (1 << 31) +#define BOOLEAN_FALSE (0) + +#define UNHANDLED_OP fatalerror("Am29000: Unhandled inst %s at %x\n", __FUNCTION__, am29000->exec_pc); /*************************************************************************** @@ -72,29 +72,29 @@ struct op_info ALU FLAG CALCULATION ***************************************************************************/ -#define SET_ALU_Z(r) am29000->alu &= ~ALU_Z; \ +#define SET_ALU_Z(r) am29000->alu &= ~ALU_Z; \ am29000->alu |= (r == 0) << ALU_Z_SHIFT; -#define SET_ALU_N(r) am29000->alu &= ~ALU_N; \ +#define SET_ALU_N(r) am29000->alu &= ~ALU_N; \ am29000->alu |= ((UINT32)r & 0x80000000) >> (31 - ALU_N_SHIFT); -#define CALC_C_ADD(r, a) ((UINT32)(r) < (UINT32)(a)) +#define CALC_C_ADD(r, a) ((UINT32)(r) < (UINT32)(a)) -#define SET_ALU_C_ADD(r, a) am29000->alu &= ~ALU_C; \ +#define SET_ALU_C_ADD(r, a) am29000->alu &= ~ALU_C; \ am29000->alu |= CALC_C_ADD(r, a) << ALU_C_SHIFT; -#define CALC_C_SUB(a, b) (!((UINT32)(a) < (UINT32)(b))) +#define CALC_C_SUB(a, b) (!((UINT32)(a) < (UINT32)(b))) -#define SET_ALU_C_SUB(a, b) am29000->alu &= ~ALU_C; \ +#define SET_ALU_C_SUB(a, b) am29000->alu &= ~ALU_C; \ am29000->alu |= CALC_C_SUB(a, b) << ALU_C_SHIFT; -#define SET_ALU_V_ADD(r, a, b) am29000->alu &= ~ALU_V; \ +#define SET_ALU_V_ADD(r, a, b) am29000->alu &= ~ALU_V; \ am29000->alu |= (((INT32)(~((a) ^ (b)) & ((a) ^ (r))) < 0)) << ALU_V_SHIFT; -#define SET_ALU_V_SUB(r, a, b) am29000->alu &= ~ALU_V; \ +#define SET_ALU_V_SUB(r, a, b) am29000->alu &= ~ALU_V; \ am29000->alu |= ((INT32)(((a) ^ (b)) & ((a) ^ (r))) < 0) << ALU_V_SHIFT; -#define GET_CARRY ((am29000->alu >> ALU_C_SHIFT) & 1) +#define GET_CARRY ((am29000->alu >> ALU_C_SHIFT) & 1) @@ -104,32 +104,32 @@ static UINT32 read_spr(am29000_state *am29000, UINT32 idx) switch (idx) { - case SPR_VAB: val = am29000->vab; break; - case SPR_OPS: val = am29000->ops; break; - case SPR_CPS: val = am29000->cps; break; - case SPR_CFG: val = am29000->cfg; break; - case SPR_CHA: val = am29000->cha; break; - case SPR_CHD: val = am29000->chd; break; - case SPR_CHC: val = am29000->chc; break; - case SPR_RBP: val = am29000->rbp; break; - case SPR_TMC: val = am29000->tmc; break; - case SPR_TMR: val = am29000->tmr; break; - case SPR_PC0: val = am29000->pc0; break; - case SPR_PC1: val = am29000->pc1; break; - case SPR_PC2: val = am29000->pc2; break; - case SPR_MMU: val = am29000->mmu; break; - case SPR_LRU: val = am29000->lru; break; - case SPR_IPC: val = am29000->ipc; break; - case SPR_IPA: val = am29000->ipa; break; - case SPR_IPB: val = am29000->ipb; break; - case SPR_Q: val = am29000->q; break; - case SPR_ALU: val = am29000->alu; break; - case SPR_BP: val = GET_ALU_BP; break; - case SPR_FC: val = GET_ALU_FC; break; - case SPR_CR: val = GET_CHC_CR; break; - case SPR_FPE: val = am29000->fpe; break; - case SPR_INTE: val = am29000->inte; break; - case SPR_FPS: val = am29000->fps; break; + case SPR_VAB: val = am29000->vab; break; + case SPR_OPS: val = am29000->ops; break; + case SPR_CPS: val = am29000->cps; break; + case SPR_CFG: val = am29000->cfg; break; + case SPR_CHA: val = am29000->cha; break; + case SPR_CHD: val = am29000->chd; break; + case SPR_CHC: val = am29000->chc; break; + case SPR_RBP: val = am29000->rbp; break; + case SPR_TMC: val = am29000->tmc; break; + case SPR_TMR: val = am29000->tmr; break; + case SPR_PC0: val = am29000->pc0; break; + case SPR_PC1: val = am29000->pc1; break; + case SPR_PC2: val = am29000->pc2; break; + case SPR_MMU: val = am29000->mmu; break; + case SPR_LRU: val = am29000->lru; break; + case SPR_IPC: val = am29000->ipc; break; + case SPR_IPA: val = am29000->ipa; break; + case SPR_IPB: val = am29000->ipb; break; + case SPR_Q: val = am29000->q; break; + case SPR_ALU: val = am29000->alu; break; + case SPR_BP: val = GET_ALU_BP; break; + case SPR_FC: val = GET_ALU_FC; break; + case SPR_CR: val = GET_CHC_CR; break; + case SPR_FPE: val = am29000->fpe; break; + case SPR_INTE: val = am29000->inte; break; + case SPR_FPS: val = am29000->fps; break; default: logerror("Unknown SPR read (%d)\n", idx); } @@ -142,56 +142,56 @@ static void write_spr(am29000_state *am29000, UINT32 idx, UINT32 val) { switch (idx) { - case SPR_VAB: am29000->vab = val & (VAB_MASK << VAB_SHIFT); + case SPR_VAB: am29000->vab = val & (VAB_MASK << VAB_SHIFT); break; - case SPR_OPS: am29000->ops = val & (CPS_CA | CPS_IP | CPS_TE | CPS_TP | CPS_TU | CPS_FZ | CPS_LK | CPS_RE | + case SPR_OPS: am29000->ops = val & (CPS_CA | CPS_IP | CPS_TE | CPS_TP | CPS_TU | CPS_FZ | CPS_LK | CPS_RE | CPS_WM | CPS_PD | CPS_PI | CPS_SM | (CPS_IM_MASK << CPS_IM_SHIFT) | CPS_DI | CPS_DA); break; - case SPR_CPS: am29000->cps = val & (CPS_CA | CPS_IP | CPS_TE | CPS_TP | CPS_TU | CPS_FZ | CPS_LK | CPS_RE | + case SPR_CPS: am29000->cps = val & (CPS_CA | CPS_IP | CPS_TE | CPS_TP | CPS_TU | CPS_FZ | CPS_LK | CPS_RE | CPS_WM | CPS_PD | CPS_PI | CPS_SM | (CPS_IM_MASK << CPS_IM_SHIFT) | CPS_DI | CPS_DA); break; - case SPR_CFG: am29000->cfg = val & (CFG_DW | CFG_VF | CFG_RV | CFG_BO | CFG_CP | CFG_CD); + case SPR_CFG: am29000->cfg = val & (CFG_DW | CFG_VF | CFG_RV | CFG_BO | CFG_CP | CFG_CD); am29000->cfg |= PROCESSOR_REL_FIELD << CFG_PRL_SHIFT; break; - case SPR_CHA: am29000->cha = val; + case SPR_CHA: am29000->cha = val; break; - case SPR_CHD: am29000->chd = val; + case SPR_CHD: am29000->chd = val; break; - case SPR_CHC: am29000->chc = val; + case SPR_CHC: am29000->chc = val; break; - case SPR_RBP: am29000->rbp = val & RBP_MASK; + case SPR_RBP: am29000->rbp = val & RBP_MASK; break; - case SPR_TMC: am29000->tmc = val & TCV_MASK; + case SPR_TMC: am29000->tmc = val & TCV_MASK; break; - case SPR_TMR: am29000->tmr = val & (TMR_OV | TMR_IN | TMR_IE | TMR_TRV_MASK); + case SPR_TMR: am29000->tmr = val & (TMR_OV | TMR_IN | TMR_IE | TMR_TRV_MASK); break; - case SPR_PC0: am29000->pc0 = val & PC_MASK; + case SPR_PC0: am29000->pc0 = val & PC_MASK; break; - case SPR_PC1: am29000->pc1 = val & PC_MASK; + case SPR_PC1: am29000->pc1 = val & PC_MASK; break; - case SPR_PC2: am29000->pc2 = val & PC_MASK; + case SPR_PC2: am29000->pc2 = val & PC_MASK; break; - case SPR_MMU: am29000->mmu = val & ((MMU_PS_MASK << MMU_PS_SHIFT) | MMU_PID_MASK); + case SPR_MMU: am29000->mmu = val & ((MMU_PS_MASK << MMU_PS_SHIFT) | MMU_PID_MASK); break; - case SPR_LRU: am29000->lru = val & (LRU_MASK << LRU_SHIFT); + case SPR_LRU: am29000->lru = val & (LRU_MASK << LRU_SHIFT); break; - case SPR_IPC: am29000->ipc = val;// & IPX_MASK; + case SPR_IPC: am29000->ipc = val;// & IPX_MASK; break; - case SPR_IPA: am29000->ipa = val;// & IPX_MASK; + case SPR_IPA: am29000->ipa = val;// & IPX_MASK; break; - case SPR_IPB: am29000->ipb = val;// & IPX_MASK; + case SPR_IPB: am29000->ipb = val;// & IPX_MASK; break; - case SPR_Q: am29000->q = val; + case SPR_Q: am29000->q = val; break; - case SPR_ALU: am29000->alu = val & (ALU_DF | ALU_V | ALU_N | ALU_Z | ALU_C | (ALU_BP_MASK << ALU_BP_SHIFT) | (ALU_FC_MASK << ALU_FC_SHIFT)); + case SPR_ALU: am29000->alu = val & (ALU_DF | ALU_V | ALU_N | ALU_Z | ALU_C | (ALU_BP_MASK << ALU_BP_SHIFT) | (ALU_FC_MASK << ALU_FC_SHIFT)); break; - case SPR_BP: am29000->alu &= ~(ALU_BP_MASK << ALU_BP_SHIFT); + case SPR_BP: am29000->alu &= ~(ALU_BP_MASK << ALU_BP_SHIFT); am29000->alu |= (val & ALU_BP_MASK) << ALU_BP_SHIFT; break; - case SPR_FC: am29000->alu &= ~(ALU_FC_MASK << ALU_FC_SHIFT); + case SPR_FC: am29000->alu &= ~(ALU_FC_MASK << ALU_FC_SHIFT); am29000->alu |= (val & ALU_FC_MASK) << ALU_FC_SHIFT; break; - case SPR_CR: am29000->chc &= ~(CHC_CR_MASK << CHC_CR_SHIFT); + case SPR_CR: am29000->chc &= ~(CHC_CR_MASK << CHC_CR_SHIFT); am29000->chc |= (val & CHC_CR_MASK) << CHC_CR_SHIFT; break; // case SPR_FPE: |