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-rw-r--r--src/devices/bus/a7800/a78_slot.cpp2
-rw-r--r--src/devices/bus/amiga/zorro/buddha.cpp26
-rw-r--r--src/devices/bus/apricot/keyboard/hle.cpp6
-rw-r--r--src/devices/bus/coco/coco_t4426.cpp6
-rw-r--r--src/devices/cpu/drcbex64.cpp2
-rw-r--r--src/devices/cpu/i960/i960.cpp16
-rw-r--r--src/devices/cpu/m68000/m68kcpu.h2
-rw-r--r--src/devices/cpu/m68000/makefile4
-rw-r--r--src/devices/cpu/m6805/m6805.cpp4
-rw-r--r--src/devices/cpu/m6805/m6805.h4
-rw-r--r--src/devices/cpu/mb86235/mb86235.cpp6
-rw-r--r--src/devices/cpu/mb86235/mb86235.h26
-rw-r--r--src/devices/cpu/mb86235/mb86235drc.cpp338
-rw-r--r--src/devices/cpu/mb86235/mb86235fe.cpp312
-rw-r--r--src/devices/cpu/powerpc/ppccom.cpp4
-rw-r--r--src/devices/cpu/powerpc/ppcdrc.cpp12
-rw-r--r--src/devices/cpu/tms32025/tms32025.cpp2
-rw-r--r--src/devices/machine/68230pit.cpp10
-rw-r--r--src/devices/machine/68230pit.h90
-rw-r--r--src/devices/machine/netlist.cpp2
-rw-r--r--src/devices/machine/netlist.h6
-rw-r--r--src/devices/machine/z80scc.h2
-rw-r--r--src/devices/sound/dac76.cpp2
-rw-r--r--src/devices/sound/votrax.cpp32
-rw-r--r--src/devices/video/ef9369.cpp2
-rw-r--r--src/devices/video/ef9369.h4
-rw-r--r--src/devices/video/zeus2.cpp10
27 files changed, 466 insertions, 466 deletions
diff --git a/src/devices/bus/a7800/a78_slot.cpp b/src/devices/bus/a7800/a78_slot.cpp
index 4bf77f178ae..a9208c91764 100644
--- a/src/devices/bus/a7800/a78_slot.cpp
+++ b/src/devices/bus/a7800/a78_slot.cpp
@@ -432,7 +432,7 @@ image_init_result a78_cart_slot_device::call_load()
m_type = A78_ABSOLUTE;
// (for now) mirror ram implies no bankswitch format is used
else if ((mapper & 0x0080) == 0x0080)
- m_type = A78_TYPE8;
+ m_type = A78_TYPE8;
logerror("Cart type: 0x%x\n", m_type);
diff --git a/src/devices/bus/amiga/zorro/buddha.cpp b/src/devices/bus/amiga/zorro/buddha.cpp
index 87a1f0e9a90..bbfe7adf82b 100644
--- a/src/devices/bus/amiga/zorro/buddha.cpp
+++ b/src/devices/bus/amiga/zorro/buddha.cpp
@@ -6,19 +6,19 @@
Zorro-II IDE controller
- The 'speed' register is used to select the IDE timing according to
- the following table (bits 7-5 are used):
-
- 0 497ns 7c to select, IOR/IOW after 172ns 2c
- 1 639ns 9c to select, IOR/IOW after 243ns 3c
- 2 781ns 11c to select, IOR/IOW after 314ns 4c
- 3 355ns 5c to select, IOR/IOW after 101ns 1c
- 4 355ns 5c to select, IOR/IOW after 172ns 2c
- 5 355ns 5c to select, IOR/IOW after 243ns 3c
- 6 1065ns 15c to select, IOR/IOW after 314ns 4c
- 7 355ns 5c to select, IOR/IOW after 101ns 1c
-
- c = clock cycles. This isn't emulated.
+ The 'speed' register is used to select the IDE timing according to
+ the following table (bits 7-5 are used):
+
+ 0 497ns 7c to select, IOR/IOW after 172ns 2c
+ 1 639ns 9c to select, IOR/IOW after 243ns 3c
+ 2 781ns 11c to select, IOR/IOW after 314ns 4c
+ 3 355ns 5c to select, IOR/IOW after 101ns 1c
+ 4 355ns 5c to select, IOR/IOW after 172ns 2c
+ 5 355ns 5c to select, IOR/IOW after 243ns 3c
+ 6 1065ns 15c to select, IOR/IOW after 314ns 4c
+ 7 355ns 5c to select, IOR/IOW after 101ns 1c
+
+ c = clock cycles. This isn't emulated.
***************************************************************************/
diff --git a/src/devices/bus/apricot/keyboard/hle.cpp b/src/devices/bus/apricot/keyboard/hle.cpp
index 72d8abc771d..ff2f9ffe28e 100644
--- a/src/devices/bus/apricot/keyboard/hle.cpp
+++ b/src/devices/bus/apricot/keyboard/hle.cpp
@@ -5,9 +5,9 @@
ACT Apricot Keyboard (HLE)
TODO:
- - MicroScreen emulation
- - Mouse emulation
- - LEDs
+ - MicroScreen emulation
+ - Mouse emulation
+ - LEDs
Keyboard to System:
- 01-60: Key make codes
diff --git a/src/devices/bus/coco/coco_t4426.cpp b/src/devices/bus/coco/coco_t4426.cpp
index 4a1185e1d0c..601e6887413 100644
--- a/src/devices/bus/coco/coco_t4426.cpp
+++ b/src/devices/bus/coco/coco_t4426.cpp
@@ -71,7 +71,7 @@
#define UART_TAG "acia"
#define PIA_TAG "pia"
-#define CARTSLOT_TAG "t4426"
+#define CARTSLOT_TAG "t4426"
/***************************************************************************
IMPLEMENTATION
@@ -85,8 +85,8 @@ MACHINE_CONFIG_END
ROM_START( coco_t4426 )
ROM_REGION(0x8000, CARTSLOT_TAG, ROMREGION_ERASE00)
- // First of 8 banked ROM:s TODO: Add the banking and the other ROM:s
- ROM_LOAD("tercoED4426-0-8549-5.3.bin", 0x0000, 0x2000, CRC(45665428) SHA1(ff49a79275772c4c4ab1ae29db662c9b10a744a7))
+ // First of 8 banked ROM:s TODO: Add the banking and the other ROM:s
+ ROM_LOAD("tercoED4426-0-8549-5.3.bin", 0x0000, 0x2000, CRC(45665428) SHA1(ff49a79275772c4c4ab1ae29db662c9b10a744a7))
// Main cartridge ROM
ROM_LOAD("tercoPMOS4426-8549-4.31.bin", 0x2000, 0x1000, CRC(bc65c45c) SHA1(e50cfd1d61e29fe05eb795d8bf6303e7b91ed8e5))
diff --git a/src/devices/cpu/drcbex64.cpp b/src/devices/cpu/drcbex64.cpp
index fd4afc729a3..2cc08888eb2 100644
--- a/src/devices/cpu/drcbex64.cpp
+++ b/src/devices/cpu/drcbex64.cpp
@@ -289,7 +289,7 @@ static uint8_t float_register_map[REG_F_COUNT] =
{
#ifdef X64_WINDOWS_ABI
REG_XMM6, REG_XMM7, REG_XMM8, REG_XMM9, REG_XMM10, REG_XMM11, REG_XMM12, REG_XMM13, REG_XMM14, REG_XMM15
-#else
+#else
// on AMD x64 ABI, XMM0-7 are FP function args. since this code has no args, and we
// save/restore them around CALLC, they should be safe for our use.
REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3, REG_XMM4, REG_XMM5, REG_XMM6, REG_XMM7
diff --git a/src/devices/cpu/i960/i960.cpp b/src/devices/cpu/i960/i960.cpp
index 83ebbe93797..9bc4386d182 100644
--- a/src/devices/cpu/i960/i960.cpp
+++ b/src/devices/cpu/i960/i960.cpp
@@ -105,8 +105,8 @@ uint32_t i960_cpu_device::get_ea(uint32_t opcode)
switch(mode) {
case 0x4:
return m_r[abase];
-
- case 0x5: // address of this instruction + the offset dword + 8
+
+ case 0x5: // address of this instruction + the offset dword + 8
// which in reality is "address of next instruction + the offset dword"
ret = m_direct->read_dword(m_IP);
m_IP += 4;
@@ -657,7 +657,7 @@ void i960_cpu_device::execute_op(uint32_t opcode)
m_icount--;
bxx(opcode, 7);
break;
-
+
case 0x18: // faultno
m_icount--;
if(!(m_AC & 7)) {
@@ -1126,10 +1126,10 @@ void i960_cpu_device::execute_op(uint32_t opcode)
cmp_s(t1, t2);
set_ri(opcode, t2-1);
break;
-
+
case 0xc: // scanbyte
m_icount -= 2;
- m_AC &= ~7; // clear CC
+ m_AC &= ~7; // clear CC
t1 = get_1_ri(opcode);
t2 = get_2_ri(opcode);
if ((t1 & 0xff000000) == (t2 & 0xff000000) ||
@@ -1379,15 +1379,15 @@ void i960_cpu_device::execute_op(uint32_t opcode)
switch((opcode >> 7) & 0xf) {
case 0x0: // calls
t1 = get_1_ri(opcode);
- t2 = m_program->read_dword(m_SAT + 152); // get pointer to system procedure table
+ t2 = m_program->read_dword(m_SAT + 152); // get pointer to system procedure table
t2 = m_program->read_dword(t2 + 48 + (t1 * 4));
if ((t2 & 3) != 0)
{
fatalerror("I960: system calls that jump into supervisor mode aren't yet supported\n");
}
- do_call(t2, 0, m_r[I960_SP]);
+ do_call(t2, 0, m_r[I960_SP]);
break;
-
+
case 0xd: // flushreg
if (m_rcache_pos > 4)
{
diff --git a/src/devices/cpu/m68000/m68kcpu.h b/src/devices/cpu/m68000/m68kcpu.h
index d8c977cca7b..4326735cd1b 100644
--- a/src/devices/cpu/m68000/m68kcpu.h
+++ b/src/devices/cpu/m68000/m68kcpu.h
@@ -697,7 +697,7 @@ static inline uint32_t m68ki_ic_readimm16(m68000_base_device *m68k, uint32_t add
uint32_t data = m68k->read32(address & ~3);
- //printf("m68k: doing cache fill at %08x (tag %08x idx %d)\n", address, tag, idx);
+ //printf("m68k: doing cache fill at %08x (tag %08x idx %d)\n", address, tag, idx);
// if no buserror occurred, validate the tag
if (!m68k->mmu_tmp_buserror_occurred)
diff --git a/src/devices/cpu/m68000/makefile b/src/devices/cpu/m68000/makefile
index be25a067a78..e98bbe8778e 100644
--- a/src/devices/cpu/m68000/makefile
+++ b/src/devices/cpu/m68000/makefile
@@ -23,7 +23,7 @@ clean:
-@rm -f m68kmake$(EXE)
-@rm -f m68kmake.o
-@rm -f m68kops.*
-
+
m68kmake.o: m68kmake.cpp
$(SILENT) $(CC) -x c++ -std=c++11 -o "$@" -c "$<"
@@ -31,7 +31,7 @@ m68kmake$(EXE) : m68kmake.o
@echo Linking $@...
$(SILENT) $(CXX) -lstdc++ $^ -o $@
-m68kops.cpp: m68kmake$(EXE) m68k_in.cpp
+m68kops.cpp: m68kmake$(EXE) m68k_in.cpp
@echo Generating M68K source files...
$(SILENT) ./m68kmake$(EXE) . m68k_in.cpp
diff --git a/src/devices/cpu/m6805/m6805.cpp b/src/devices/cpu/m6805/m6805.cpp
index 95c18c417a7..278505b8c1e 100644
--- a/src/devices/cpu/m6805/m6805.cpp
+++ b/src/devices/cpu/m6805/m6805.cpp
@@ -421,7 +421,7 @@ m6805_base_device::m6805_base_device(const machine_config &mconfig, const char *
{
}
-
+
void m6805_base_device::device_start()
{
@@ -1110,7 +1110,7 @@ void m68705_new_device::device_start()
m_portA_cb_w.resolve_safe();
m_portB_cb_w.resolve_safe();
m_portC_cb_w.resolve_safe();
-
+
m_portA_cb_r.resolve_safe(0xff);
m_portB_cb_r.resolve_safe(0xff);
m_portC_cb_r.resolve_safe(0xff);
diff --git a/src/devices/cpu/m6805/m6805.h b/src/devices/cpu/m6805/m6805.h
index 63920b758b4..24b75f57158 100644
--- a/src/devices/cpu/m6805/m6805.h
+++ b/src/devices/cpu/m6805/m6805.h
@@ -438,9 +438,9 @@ protected:
// device-level overrides
virtual void device_start() override;
-// virtual void execute_set_input(int inputnum, int state) override;
+// virtual void execute_set_input(int inputnum, int state) override;
-// virtual void interrupt() override;
+// virtual void interrupt() override;
};
// ======================> hd63705_device
diff --git a/src/devices/cpu/mb86235/mb86235.cpp b/src/devices/cpu/mb86235/mb86235.cpp
index 5e22794da28..44a1d596310 100644
--- a/src/devices/cpu/mb86235/mb86235.cpp
+++ b/src/devices/cpu/mb86235/mb86235.cpp
@@ -17,7 +17,7 @@
#include "mb86235fe.h"
-#define ENABLE_DRC 0
+#define ENABLE_DRC 0
#define CACHE_SIZE (1 * 1024 * 1024)
@@ -243,7 +243,7 @@ void mb86235_device::fifoin_w(uint64_t data)
printf("FIFOIN push %08X%08X\n", (uint32_t)(data >> 32), (uint32_t)(data));
m_core->fifoin.data[m_core->fifoin.wpos] = data;
-
+
m_core->fifoin.wpos++;
m_core->fifoin.wpos &= FIFOIN_SIZE-1;
m_core->fifoin.num++;
@@ -285,4 +285,4 @@ bool mb86235_device::is_fifoout0_empty()
#else
return false;
#endif
-} \ No newline at end of file
+}
diff --git a/src/devices/cpu/mb86235/mb86235.h b/src/devices/cpu/mb86235/mb86235.h
index dac55fe382a..99c008ae88e 100644
--- a/src/devices/cpu/mb86235/mb86235.h
+++ b/src/devices/cpu/mb86235/mb86235.h
@@ -19,19 +19,19 @@ class mb86235_frontend;
-#define OP_USERFLAG_FIFOIN 0x1
-#define OP_USERFLAG_FIFOOUT0 0x2
-#define OP_USERFLAG_FIFOOUT1 0x4
-#define OP_USERFLAG_REPEAT 0x8
-#define OP_USERFLAG_REPEATED_OP 0x10
-#define OP_USERFLAG_PR_MASK 0x300
-#define OP_USERFLAG_PR_INC 0x100
-#define OP_USERFLAG_PR_DEC 0x200
-#define OP_USERFLAG_PR_ZERO 0x300
-#define OP_USERFLAG_PW_MASK 0xc00
-#define OP_USERFLAG_PW_INC 0x400
-#define OP_USERFLAG_PW_DEC 0x800
-#define OP_USERFLAG_PW_ZERO 0xc00
+#define OP_USERFLAG_FIFOIN 0x1
+#define OP_USERFLAG_FIFOOUT0 0x2
+#define OP_USERFLAG_FIFOOUT1 0x4
+#define OP_USERFLAG_REPEAT 0x8
+#define OP_USERFLAG_REPEATED_OP 0x10
+#define OP_USERFLAG_PR_MASK 0x300
+#define OP_USERFLAG_PR_INC 0x100
+#define OP_USERFLAG_PR_DEC 0x200
+#define OP_USERFLAG_PR_ZERO 0x300
+#define OP_USERFLAG_PW_MASK 0xc00
+#define OP_USERFLAG_PW_INC 0x400
+#define OP_USERFLAG_PW_DEC 0x800
+#define OP_USERFLAG_PW_ZERO 0xc00
class mb86235_device : public cpu_device
diff --git a/src/devices/cpu/mb86235/mb86235drc.cpp b/src/devices/cpu/mb86235/mb86235drc.cpp
index 1ea7ac6b708..0a27c23eafc 100644
--- a/src/devices/cpu/mb86235/mb86235drc.cpp
+++ b/src/devices/cpu/mb86235/mb86235drc.cpp
@@ -16,8 +16,8 @@
#include "cpu/drcumlsh.h"
/*
- TODO:
- - check jump condition before parallel ALU/MUL (flags!)
+ TODO:
+ - check jump condition before parallel ALU/MUL (flags!)
*/
@@ -38,55 +38,55 @@ using namespace uml;
#define EXECUTE_RESET_CACHE 3
-#define AR(reg) mem(&m_core->ar[(reg)])
-#define AA(reg) m_regmap[(reg)]
-#define AB(reg) m_regmap[(reg)+8]
-#define MA(reg) m_regmap[(reg)+16]
-#define MB(reg) m_regmap[(reg)+24]
-#define FLAGS_AZ mem(&m_core->flags.az)
-#define FLAGS_AN mem(&m_core->flags.an)
-#define FLAGS_AV mem(&m_core->flags.av)
-#define FLAGS_AU mem(&m_core->flags.au)
-#define FLAGS_AD mem(&m_core->flags.ad)
-#define FLAGS_ZC mem(&m_core->flags.zc)
-#define FLAGS_IL mem(&m_core->flags.il)
-#define FLAGS_NR mem(&m_core->flags.nr)
-#define FLAGS_ZD mem(&m_core->flags.zd)
-#define FLAGS_MN mem(&m_core->flags.mn)
-#define FLAGS_MZ mem(&m_core->flags.mz)
-#define FLAGS_MV mem(&m_core->flags.mv)
-#define FLAGS_MU mem(&m_core->flags.mu)
-#define FLAGS_MD mem(&m_core->flags.md)
-
-#define PRP mem(&m_core->prp)
-#define PWP mem(&m_core->pwp)
-#define RPC mem(&m_core->rpc)
-#define LPC mem(&m_core->lpc)
-
-#define AZ_CALC_REQUIRED ((desc->regreq[1] & 0x1) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AN_CALC_REQUIRED ((desc->regreq[1] & 0x2) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AV_CALC_REQUIRED ((desc->regreq[1] & 0x4) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AU_CALC_REQUIRED ((desc->regreq[1] & 0x8) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define AD_CALC_REQUIRED ((desc->regreq[1] & 0x10) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define ZC_CALC_REQUIRED ((desc->regreq[1] & 0x20) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define IL_CALC_REQUIRED ((desc->regreq[1] & 0x40) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define NR_CALC_REQUIRED ((desc->regreq[1] & 0x80) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define ZD_CALC_REQUIRED ((desc->regreq[1] & 0x100) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MN_CALC_REQUIRED ((desc->regreq[1] & 0x200) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MZ_CALC_REQUIRED ((desc->regreq[1] & 0x400) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MV_CALC_REQUIRED ((desc->regreq[1] & 0x800) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MU_CALC_REQUIRED ((desc->regreq[1] & 0x1000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-#define MD_CALC_REQUIRED ((desc->regreq[1] & 0x2000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
-
-#define FIFOIN_RPOS mem(&m_core->fifoin.rpos)
-#define FIFOIN_WPOS mem(&m_core->fifoin.wpos)
-#define FIFOIN_NUM mem(&m_core->fifoin.num)
-#define FIFOOUT0_RPOS mem(&m_core->fifoout0.rpos)
-#define FIFOOUT0_WPOS mem(&m_core->fifoout0.wpos)
-#define FIFOOUT0_NUM mem(&m_core->fifoout0.num)
-#define FIFOOUT1_RPOS mem(&m_core->fifoout1.rpos)
-#define FIFOOUT1_WPOS mem(&m_core->fifoout1.wpos)
-#define FIFOOUT1_NUM mem(&m_core->fifoout1.num)
+#define AR(reg) mem(&m_core->ar[(reg)])
+#define AA(reg) m_regmap[(reg)]
+#define AB(reg) m_regmap[(reg)+8]
+#define MA(reg) m_regmap[(reg)+16]
+#define MB(reg) m_regmap[(reg)+24]
+#define FLAGS_AZ mem(&m_core->flags.az)
+#define FLAGS_AN mem(&m_core->flags.an)
+#define FLAGS_AV mem(&m_core->flags.av)
+#define FLAGS_AU mem(&m_core->flags.au)
+#define FLAGS_AD mem(&m_core->flags.ad)
+#define FLAGS_ZC mem(&m_core->flags.zc)
+#define FLAGS_IL mem(&m_core->flags.il)
+#define FLAGS_NR mem(&m_core->flags.nr)
+#define FLAGS_ZD mem(&m_core->flags.zd)
+#define FLAGS_MN mem(&m_core->flags.mn)
+#define FLAGS_MZ mem(&m_core->flags.mz)
+#define FLAGS_MV mem(&m_core->flags.mv)
+#define FLAGS_MU mem(&m_core->flags.mu)
+#define FLAGS_MD mem(&m_core->flags.md)
+
+#define PRP mem(&m_core->prp)
+#define PWP mem(&m_core->pwp)
+#define RPC mem(&m_core->rpc)
+#define LPC mem(&m_core->lpc)
+
+#define AZ_CALC_REQUIRED ((desc->regreq[1] & 0x1) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AN_CALC_REQUIRED ((desc->regreq[1] & 0x2) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AV_CALC_REQUIRED ((desc->regreq[1] & 0x4) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AU_CALC_REQUIRED ((desc->regreq[1] & 0x8) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define AD_CALC_REQUIRED ((desc->regreq[1] & 0x10) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define ZC_CALC_REQUIRED ((desc->regreq[1] & 0x20) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define IL_CALC_REQUIRED ((desc->regreq[1] & 0x40) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define NR_CALC_REQUIRED ((desc->regreq[1] & 0x80) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define ZD_CALC_REQUIRED ((desc->regreq[1] & 0x100) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MN_CALC_REQUIRED ((desc->regreq[1] & 0x200) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MZ_CALC_REQUIRED ((desc->regreq[1] & 0x400) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MV_CALC_REQUIRED ((desc->regreq[1] & 0x800) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MU_CALC_REQUIRED ((desc->regreq[1] & 0x1000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+#define MD_CALC_REQUIRED ((desc->regreq[1] & 0x2000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
+
+#define FIFOIN_RPOS mem(&m_core->fifoin.rpos)
+#define FIFOIN_WPOS mem(&m_core->fifoin.wpos)
+#define FIFOIN_NUM mem(&m_core->fifoin.num)
+#define FIFOOUT0_RPOS mem(&m_core->fifoout0.rpos)
+#define FIFOOUT0_WPOS mem(&m_core->fifoout0.wpos)
+#define FIFOOUT0_NUM mem(&m_core->fifoout0.num)
+#define FIFOOUT1_RPOS mem(&m_core->fifoout1.rpos)
+#define FIFOOUT1_WPOS mem(&m_core->fifoout1.wpos)
+#define FIFOOUT1_NUM mem(&m_core->fifoout1.num)
inline void mb86235_device::alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const char *name)
@@ -631,17 +631,17 @@ void mb86235_device::generate_ea(drcuml_block *block, compiler_state *compiler,
switch (md)
{
- case 0x0: // @ARx
+ case 0x0: // @ARx
UML_MOV(block, I0, AR(arx));
break;
- case 0x1: // @ARx++
+ case 0x1: // @ARx++
UML_MOV(block, I0, AR(arx));
UML_ADD(block, AR(arx), AR(arx), 1);
break;
- case 0x4: // @ARx+ARy
+ case 0x4: // @ARx+ARy
UML_ADD(block, I0, AR(arx), AR(ary));
break;
- case 0xa: // @ARx+disp12
+ case 0xa: // @ARx+disp12
UML_ADD(block, I0, AR(arx), disp);
break;
@@ -672,11 +672,11 @@ void mb86235_device::generate_reg_read(drcuml_block *block, compiler_state *comp
UML_MOV(block, dst, AB(reg & 7));
break;
- case 0x30: // PR
+ case 0x30: // PR
UML_LOAD(block, dst, m_core->pr, PRP, SIZE_DWORD, SCALE_x4);
break;
- case 0x31: // FI
+ case 0x31: // FI
UML_CALLH(block, *m_read_fifo_in);
UML_MOV(block, dst, I0);
break;
@@ -702,15 +702,15 @@ void mb86235_device::generate_reg_write(drcuml_block *block, compiler_state *com
UML_MOV(block, AA(reg & 7), src);
break;
- case 0x10: // EB
+ case 0x10: // EB
UML_MOV(block, mem(&m_core->eb), src);
break;
- case 0x13: // EO
+ case 0x13: // EO
UML_MOV(block, mem(&m_core->eo), src);
break;
- case 0x14: // SP
+ case 0x14: // SP
UML_MOV(block, mem(&m_core->sp), src);
break;
@@ -729,28 +729,28 @@ void mb86235_device::generate_reg_write(drcuml_block *block, compiler_state *com
UML_MOV(block, AB(reg & 7), src);
break;
- case 0x30: // PR
+ case 0x30: // PR
UML_STORE(block, m_core->pr, PWP, src, SIZE_DWORD, SCALE_x4);
break;
- case 0x32: // FO0
+ case 0x32: // FO0
UML_MOV(block, I0, src);
UML_CALLH(block, *m_write_fifo_out0);
break;
- case 0x34: // PDR
+ case 0x34: // PDR
UML_MOV(block, mem(&m_core->pdr), src);
break;
- case 0x35: // DDR
+ case 0x35: // DDR
UML_MOV(block, mem(&m_core->ddr), src);
break;
- case 0x36: // PRP
+ case 0x36: // PRP
UML_MOV(block, PRP, src);
break;
- case 0x37: // PWP
+ case 0x37: // PWP
UML_MOV(block, PWP, src);
break;
@@ -788,9 +788,9 @@ bool mb86235_device::aluop_has_result(int aluop)
{
switch (aluop)
{
- case 0x04: // FCMP
- case 0x07: // NOP
- case 0x14: // CMP
+ case 0x04: // FCMP
+ case 0x07: // NOP
+ case 0x14: // CMP
return false;
default:
@@ -874,7 +874,7 @@ bool mb86235_device::generate_opcode(drcuml_block *block, compiler_state *compil
UML_LABEL(block, not_full);
}
-
+
switch ((opcode >> 61) & 7)
{
@@ -900,7 +900,7 @@ bool mb86235_device::generate_opcode(drcuml_block *block, compiler_state *compil
if (mul_temp) UML_MOV(block, get_alu_output((opcode >> 27) & 0x1f), mem(&m_core->multemp));
break;
}
- case 2: // ALU / MUL / control
+ case 2: // ALU / MUL / control
{
generate_pre_control(block, compiler, desc);
generate_alu(block, compiler, desc, (opcode >> 42) & 0x7ffff, false);
@@ -979,17 +979,17 @@ bool mb86235_device::generate_opcode(drcuml_block *block, compiler_state *compil
{
switch ((desc->userflags & OP_USERFLAG_PR_MASK) >> 8)
{
- case 1: // PR++
+ case 1: // PR++
UML_ADD(block, PRP, PRP, 1);
UML_CMP(block, PRP, 24);
UML_MOVc(block, COND_GE, PRP, 0);
break;
- case 2: // PR--
+ case 2: // PR--
UML_SUB(block, PRP, PRP, 1);
UML_CMP(block, PRP, 0);
UML_MOVc(block, COND_L, PRP, 23);
break;
- case 3: // PR#0
+ case 3: // PR#0
UML_MOV(block, PRP, 0);
break;
}
@@ -999,17 +999,17 @@ bool mb86235_device::generate_opcode(drcuml_block *block, compiler_state *compil
{
switch ((desc->userflags & OP_USERFLAG_PW_MASK) >> 10)
{
- case 1: // PW++
+ case 1: // PW++
UML_ADD(block, PWP, PWP, 1);
UML_CMP(block, PWP, 24);
UML_MOVc(block, COND_GE, PWP, 0);
break;
- case 2: // PW--
+ case 2: // PW--
UML_SUB(block, PWP, PWP, 1);
UML_CMP(block, PWP, 0);
UML_MOVc(block, COND_L, PWP, 23);
break;
- case 3: // PW#0
+ case 3: // PW#0
UML_MOV(block, PWP, 0);
break;
}
@@ -1047,7 +1047,7 @@ void mb86235_device::generate_alumul_input(drcuml_block *block, compiler_state *
else
UML_MOV(block, dst, AA(reg & 7));
break;
-
+
case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
if (mul)
UML_MOV(block, dst, MB(reg & 7));
@@ -1055,51 +1055,51 @@ void mb86235_device::generate_alumul_input(drcuml_block *block, compiler_state *
UML_MOV(block, dst, AB(reg & 7));
break;
- case 0x10: // PR
- case 0x11: // PR++
- case 0x12: // PR--
- case 0x13: // PR#0
+ case 0x10: // PR
+ case 0x11: // PR++
+ case 0x12: // PR--
+ case 0x13: // PR#0
UML_LOAD(block, dst, m_core->pr, PRP, SIZE_DWORD, SCALE_x4);
break;
- case 0x18: // 0 / -1.0E+0
+ case 0x18: // 0 / -1.0E+0
if (fp)
UML_MOV(block, dst, 0xbf800000);
else
UML_MOV(block, dst, 0);
break;
- case 0x19: // 1 / 0.0E+0
+ case 0x19: // 1 / 0.0E+0
if (fp)
UML_MOV(block, dst, 0);
else
UML_MOV(block, dst, 1);
break;
- case 0x1a: // -1 / 0.5+0
+ case 0x1a: // -1 / 0.5+0
if (fp)
UML_MOV(block, dst, 0x3f000000);
else
UML_MOV(block, dst, -1);
break;
- case 0x1b: // 1.0E+0
+ case 0x1b: // 1.0E+0
UML_MOV(block, dst, 0x3f800000);
break;
- case 0x1c: // 1.5E+0
+ case 0x1c: // 1.5E+0
UML_MOV(block, dst, 0x3fc00000);
break;
- case 0x1d: // 2.0E+0
+ case 0x1d: // 2.0E+0
UML_MOV(block, dst, 0x40000000);
break;
- case 0x1e: // 3.0E+0
+ case 0x1e: // 3.0E+0
UML_MOV(block, dst, 0x40400000);
break;
- case 0x1f: // 5.0E+0
+ case 0x1f: // 5.0E+0
UML_MOV(block, dst, 0x40a00000);
break;
@@ -1159,9 +1159,9 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
int io = aluop & 0x1f;
int op = (aluop >> 14) & 0x1f;
- switch (op)
+ switch (op)
{
- case 0x00: // FADD
+ case 0x00: // FADD
generate_alumul_input(block, compiler, desc, i2, I0, true, false);
UML_FSCOPYI(block, F0, I0);
UML_FSCOPYI(block, F1, get_alu1_input(i1));
@@ -1176,7 +1176,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
// TODO: AD flag
break;
- case 0x02: // FSUB
+ case 0x02: // FSUB
generate_alumul_input(block, compiler, desc, i2, I0, true, false);
UML_FSCOPYI(block, F0, I0);
UML_FSCOPYI(block, F1, get_alu1_input(i1));
@@ -1191,7 +1191,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
// TODO: AD flag
break;
- case 0x04: // FCMP
+ case 0x04: // FCMP
generate_alumul_input(block, compiler, desc, i2, I0, true, false);
UML_FSCOPYI(block, F0, I0);
UML_FSCOPYI(block, F1, get_alu1_input(i1));
@@ -1203,14 +1203,14 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
// TODO: AD flag
break;
- case 0x05: // FABS
+ case 0x05: // FABS
UML_AND(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), get_alu1_input(i1), 0x7fffffff);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, FLAGS_AZ);
if (AN_CALC_REQUIRED) UML_MOV(block, FLAGS_AN, 0);
// TODO: AD flag
break;
- case 0x06: // FABC
+ case 0x06: // FABC
generate_alumul_input(block, compiler, desc, i2, I0, true, false);
UML_AND(block, I0, I0, 0x7fffffff);
UML_AND(block, I1, get_alu1_input(i1), 0x7fffffff);
@@ -1223,10 +1223,10 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
// TODO: AD flag
break;
- case 0x07: // NOP
+ case 0x07: // NOP
break;
- case 0x0d: // CIF
+ case 0x0d: // CIF
generate_alumul_input(block, compiler, desc, i1, I1, true, false);
UML_FSFRINT(block, F0, I1, SIZE_DWORD);
if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
@@ -1236,7 +1236,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
UML_ICOPYFS(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), F0);
break;
- case 0x0e: // CFI
+ case 0x0e: // CFI
{
code_label truncate = compiler->labelnum++;
code_label end = compiler->labelnum++;
@@ -1248,7 +1248,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
UML_LABEL(block, truncate);
UML_FSTOINT(block, I0, F0, SIZE_DWORD, ROUND_TRUNC);
UML_LABEL(block, end);
-
+
UML_CMP(block, I0, 0xff800000);
UML_MOVc(block, COND_L, I0, 0xff800000);
if (AV_CALC_REQUIRED) UML_MOVc(block, COND_L, FLAGS_AV, 1);
@@ -1263,7 +1263,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
break;
}
- case 0x10: // ADD
+ case 0x10: // ADD
generate_alumul_input(block, compiler, desc, i2, I1, false, false);
UML_ADD(block, I0, I1, get_alu1_input(i1));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, FLAGS_AZ);
@@ -1277,7 +1277,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), I0);
break;
- case 0x12: // SUB
+ case 0x12: // SUB
generate_alumul_input(block, compiler, desc, i2, I1, false, false);
UML_SUB(block, I0, I1, get_alu1_input(i1));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, FLAGS_AZ);
@@ -1291,7 +1291,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), I0);
break;
- case 0x14: // CMP
+ case 0x14: // CMP
generate_alumul_input(block, compiler, desc, i2, I1, false, false);
UML_SUB(block, I0, I1, get_alu1_input(i1));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, FLAGS_AZ);
@@ -1305,11 +1305,11 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
}
break;
- case 0x16: // ATR
+ case 0x16: // ATR
UML_MOV(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), get_alu1_input(i1));
break;
- case 0x18: // AND
+ case 0x18: // AND
generate_alumul_input(block, compiler, desc, i2, I0, false, false);
UML_AND(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), I0, get_alu1_input(i1));
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, FLAGS_AN);
@@ -1318,7 +1318,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
if (AU_CALC_REQUIRED) UML_MOV(block, FLAGS_AU, 0);
break;
- case 0x1c: // LSR
+ case 0x1c: // LSR
generate_alumul_input(block, compiler, desc, i1, I0, false, false);
UML_SHR(block, I0, I0, i2);
if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
@@ -1330,7 +1330,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), I0);
break;
- case 0x1d: // LSL
+ case 0x1d: // LSL
generate_alumul_input(block, compiler, desc, i1, I0, false, false);
UML_SHL(block, I0, I0, i2);
if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
@@ -1438,13 +1438,13 @@ void mb86235_device::generate_branch_target(drcuml_block *block, compiler_state
{
case 0x0: break;
case 0x1: break;
- case 0x2: // ARx
+ case 0x2: // ARx
{
int reg = (ef2 >> 6) & 7;
UML_MOV(block, I0, AR(reg));
break;
}
- case 0x4: // Axx
+ case 0x4: // Axx
{
int reg = (ef2 >> 6) & 7;
if (ef2 & 0x400)
@@ -1464,59 +1464,59 @@ void mb86235_device::generate_condition(drcuml_block *block, compiler_state *com
{
switch (cc)
{
- case 0x00: // MN
+ case 0x00: // MN
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_MN, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x01: // MZ
+ case 0x01: // MZ
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_MZ, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x02: // MV
+ case 0x02: // MV
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_MV, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x03: // MU
+ case 0x03: // MU
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_MU, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x04: // ZD
+ case 0x04: // ZD
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_ZD, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x05: // NR
+ case 0x05: // NR
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_NR, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x06: // IL
+ case 0x06: // IL
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_IL, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x07: // ZC
+ case 0x07: // ZC
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_ZC, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x08: // AN
+ case 0x08: // AN
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_AN, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x09: // AZ
+ case 0x09: // AZ
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_AZ, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x0a: // AV
+ case 0x0a: // AV
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_AV, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x0b: // AU
+ case 0x0b: // AU
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_AU, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x0c: // MD
+ case 0x0c: // MD
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_MD, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
- case 0x0d: // AD
+ case 0x0d: // AD
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_AD, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
@@ -1533,22 +1533,22 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
int ef1 = (op >> 16) & 0x3f;
int ef2 = op & 0xffff;
int cop = (op >> 22) & 0x1f;
-// int rel12 = (op & 0x800) ? (0xfffff000 | (op & 0xfff)) : (op & 0xfff);
+// int rel12 = (op & 0x800) ? (0xfffff000 | (op & 0xfff)) : (op & 0xfff);
switch (cop)
{
- case 0x00: // NOP
+ case 0x00: // NOP
break;
- case 0x03: //
- if (ef1 == 1) // CLRFI
+ case 0x03: //
+ if (ef1 == 1) // CLRFI
UML_CALLH(block, *m_clear_fifo_in);
- else if (ef1 == 2) // CLRFO
+ else if (ef1 == 2) // CLRFO
{
UML_CALLH(block, *m_clear_fifo_out0);
UML_CALLH(block, *m_clear_fifo_out1);
}
- else if (ef1 == 3) // CLRF
+ else if (ef1 == 3) // CLRF
{
UML_CALLH(block, *m_clear_fifo_in);
UML_CALLH(block, *m_clear_fifo_out0);
@@ -1556,11 +1556,11 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
}
break;
- case 0x08: // SETM #imm16
+ case 0x08: // SETM #imm16
UML_MOV(block, mem(&m_core->mod), ef2);
break;
- case 0x10: // DBcc
+ case 0x10: // DBcc
{
code_label skip_label = compiler->labelnum++;
@@ -1571,7 +1571,7 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
break;
}
- case 0x11: // DBNcc
+ case 0x11: // DBNcc
{
code_label skip_label = compiler->labelnum++;
@@ -1582,14 +1582,14 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
break;
}
- case 0x12: // DJMP
+ case 0x12: // DJMP
{
generate_branch_target(block, compiler, desc, (op >> 12) & 0xf, ef2);
generate_branch(block, compiler, desc);
break;
}
- case 0x1a: // DCALL
+ case 0x1a: // DCALL
{
// push PC
code_label no_overflow = compiler->labelnum++;
@@ -1601,13 +1601,13 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
UML_LABEL(block, no_overflow);
UML_STORE(block, m_core->pcs, mem(&m_core->pcs_ptr), desc->pc + 2, SIZE_DWORD, SCALE_x4);
UML_ADD(block, mem(&m_core->pcs_ptr), mem(&m_core->pcs_ptr), 1);
-
+
generate_branch_target(block, compiler, desc, (op >> 12) & 0xf, ef2);
generate_branch(block, compiler, desc);
break;
}
- case 0x1b: // DRET
+ case 0x1b: // DRET
{
// pop PC
code_label no_underflow = compiler->labelnum++;
@@ -1619,7 +1619,7 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
UML_LABEL(block, no_underflow);
UML_SUB(block, mem(&m_core->pcs_ptr), mem(&m_core->pcs_ptr), 1);
UML_LOAD(block, I0, m_core->pcs, mem(&m_core->pcs_ptr), SIZE_DWORD, SCALE_x4);
-
+
generate_branch(block, compiler, desc);
break;
}
@@ -1642,7 +1642,7 @@ void mb86235_device::generate_xfer1(drcuml_block *block, compiler_state *compile
int ary = (opcode >> 4) & 7;
int disp5 = (opcode >> 7) & 0x1f;
int trm = (opcode >> 26) & 1;
-// int dir = (opcode >> 25) & 1;
+// int dir = (opcode >> 25) & 1;
if (trm == 0)
{
@@ -1660,7 +1660,7 @@ void mb86235_device::generate_xfer1(drcuml_block *block, compiler_state *compile
else
{
generate_ea(block, compiler, desc, md, sr & 7, ary, disp5);
- if (sr & 0x20) // RAM-B
+ if (sr & 0x20) // RAM-B
{
UML_SHL(block, I0, I0, 2);
UML_READ(block, I1, I0, SIZE_DWORD, SPACE_IO);
@@ -1678,7 +1678,7 @@ void mb86235_device::generate_xfer1(drcuml_block *block, compiler_state *compile
else
{
generate_ea(block, compiler, desc, md, dr & 7, ary, disp5);
- if (dr & 0x20) // RAM-B
+ if (dr & 0x20) // RAM-B
{
UML_SHL(block, I0, I0, 2);
UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_IO);
@@ -1719,7 +1719,7 @@ void mb86235_device::generate_xfer2(drcuml_block *block, compiler_state *compile
int disp14 = (opcode >> 7) & 0x3fff;
if (disp14 & 0x2000) disp14 |= 0xffffc000;
- if (op == 0) // MOV2
+ if (op == 0) // MOV2
{
if (trm == 0)
{
@@ -1737,7 +1737,7 @@ void mb86235_device::generate_xfer2(drcuml_block *block, compiler_state *compile
else
{
generate_ea(block, compiler, desc, md, sr & 7, ary, disp14);
- if (sr & 0x20) // RAM-B
+ if (sr & 0x20) // RAM-B
{
UML_SHL(block, I0, I0, 2);
UML_READ(block, I1, I0, SIZE_DWORD, SPACE_IO);
@@ -1745,7 +1745,7 @@ void mb86235_device::generate_xfer2(drcuml_block *block, compiler_state *compile
else // RAM-A
{
UML_CALLH(block, *m_read_abus);
- }
+ }
}
if ((dr & 0x40) == 0)
@@ -1755,7 +1755,7 @@ void mb86235_device::generate_xfer2(drcuml_block *block, compiler_state *compile
else
{
generate_ea(block, compiler, desc, md, dr & 7, ary, disp14);
- if (dr & 0x20) // RAM-B
+ if (dr & 0x20) // RAM-B
{
UML_SHL(block, I0, I0, 2);
UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_IO);
@@ -1791,7 +1791,7 @@ void mb86235_device::generate_xfer2(drcuml_block *block, compiler_state *compile
UML_ADD(block, mem(&m_core->eo), mem(&m_core->eo), disp14);
}
}
- else if (op == 2) // MOV4
+ else if (op == 2) // MOV4
{
fatalerror("generate_xfer2 MOV4 at %08X (%08X%08X)", desc->pc, (uint32_t)(opcode >> 32), (uint32_t)(opcode));
}
@@ -1809,7 +1809,7 @@ void mb86235_device::generate_xfer3(drcuml_block *block, compiler_state *compile
uint64_t opcode = desc->opptr.q[0];
uint32_t imm = (uint32_t)(opcode >> 27);
- int dr = (opcode >> 19) & 0x7f;
+ int dr = (opcode >> 19) & 0x7f;
int ary = (opcode >> 4) & 7;
int md = opcode & 0xf;
@@ -1819,17 +1819,17 @@ void mb86235_device::generate_xfer3(drcuml_block *block, compiler_state *compile
switch (dr >> 5)
{
case 0:
- case 1: // reg
+ case 1: // reg
generate_reg_write(block, compiler, desc, dr & 0x3f, uml::parameter(imm));
break;
- case 2: // RAM-A
+ case 2: // RAM-A
generate_ea(block, compiler, desc, md, dr & 7, ary, disp);
UML_MOV(block, I1, imm);
UML_CALLH(block, *m_write_abus);
break;
- case 3: // RAM-B
+ case 3: // RAM-B
generate_ea(block, compiler, desc, md, dr & 7, ary, disp);
UML_SHL(block, I0, I0, 2);
UML_WRITE(block, I0, imm, SIZE_DWORD, SPACE_IO);
@@ -1847,38 +1847,38 @@ void mb86235_device::generate_pre_control(drcuml_block *block, compiler_state *c
switch (cop)
{
- case 0x10: // DBcc
- case 0x11: // DBNcc
- case 0x18: // DCcc
- case 0x19: // DCNcc
+ case 0x10: // DBcc
+ case 0x11: // DBNcc
+ case 0x18: // DCcc
+ case 0x19: // DCNcc
switch (ef1)
{
- case 0x00: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MN); break; // MN
- case 0x01: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MZ); break; // MZ
- case 0x02: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MV); break; // MV
- case 0x03: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MU); break; // MU
- case 0x04: UML_MOV(block, mem(&m_core->condtemp), FLAGS_ZD); break; // ZD
- case 0x05: UML_MOV(block, mem(&m_core->condtemp), FLAGS_NR); break; // NR
- case 0x06: UML_MOV(block, mem(&m_core->condtemp), FLAGS_IL); break; // IL
- case 0x07: UML_MOV(block, mem(&m_core->condtemp), FLAGS_ZC); break; // ZC
- case 0x08: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AN); break; // AN
- case 0x09: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AZ); break; // AZ
- case 0x0a: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AV); break; // AV
- case 0x0b: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AU); break; // AU
- case 0x0c: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MD); break; // MD
- case 0x0d: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AD); break; // AD
+ case 0x00: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MN); break; // MN
+ case 0x01: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MZ); break; // MZ
+ case 0x02: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MV); break; // MV
+ case 0x03: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MU); break; // MU
+ case 0x04: UML_MOV(block, mem(&m_core->condtemp), FLAGS_ZD); break; // ZD
+ case 0x05: UML_MOV(block, mem(&m_core->condtemp), FLAGS_NR); break; // NR
+ case 0x06: UML_MOV(block, mem(&m_core->condtemp), FLAGS_IL); break; // IL
+ case 0x07: UML_MOV(block, mem(&m_core->condtemp), FLAGS_ZC); break; // ZC
+ case 0x08: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AN); break; // AN
+ case 0x09: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AZ); break; // AZ
+ case 0x0a: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AV); break; // AV
+ case 0x0b: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AU); break; // AU
+ case 0x0c: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MD); break; // MD
+ case 0x0d: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AD); break; // AD
default:
fatalerror("generate_pre_control: unimplemented cc %02X at %08X", ef1, desc->pc);
break;
}
break;
- case 0x14: // DBBC ARx:y, rel12
+ case 0x14: // DBBC ARx:y, rel12
// TODO: copy ARx
UML_MOV(block, mem(&m_core->condtemp), AR((ef2 >> 13) & 7));
break;
- case 0x15: // DBBS ARx:y, rel12
+ case 0x15: // DBBS ARx:y, rel12
// TODO: copy ARx
UML_MOV(block, mem(&m_core->condtemp), AR((ef2 >> 13) & 7));
break;
diff --git a/src/devices/cpu/mb86235/mb86235fe.cpp b/src/devices/cpu/mb86235/mb86235fe.cpp
index f5343109a2e..f55fb0934bf 100644
--- a/src/devices/cpu/mb86235/mb86235fe.cpp
+++ b/src/devices/cpu/mb86235/mb86235fe.cpp
@@ -11,45 +11,45 @@
#include "mb86235fe.h"
-#define AA_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0)
-#define AA_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0)
-#define AB_USED(desc,x) do { (desc).regin[0] |= 1 << (8+(x)); } while(0)
-#define AB_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (8+(x)); } while(0)
-#define MA_USED(desc,x) do { (desc).regin[0] |= 1 << (16+(x)); } while(0)
-#define MA_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (16+(x)); } while(0)
-#define MB_USED(desc,x) do { (desc).regin[0] |= 1 << (24+(x)); } while(0)
-#define MB_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (24+(x)); } while(0)
-#define AR_USED(desc,x) do { (desc).regin[1] |= 1 << (24+(x)); } while(0)
-#define AR_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (24+(x)); } while(0)
-
-#define AZ_USED(desc) do { (desc).regin[1] |= 1 << 0; } while (0)
-#define AZ_MODIFIED(desc) do { (desc).regout[1] |= 1 << 0; } while (0)
-#define AN_USED(desc) do { (desc).regin[1] |= 1 << 1; } while (0)
-#define AN_MODIFIED(desc) do { (desc).regout[1] |= 1 << 1; } while (0)
-#define AV_USED(desc) do { (desc).regin[1] |= 1 << 2; } while (0)
-#define AV_MODIFIED(desc) do { (desc).regout[1] |= 1 << 2; } while (0)
-#define AU_USED(desc) do { (desc).regin[1] |= 1 << 3; } while (0)
-#define AU_MODIFIED(desc) do { (desc).regout[1] |= 1 << 3; } while (0)
-#define AD_USED(desc) do { (desc).regin[1] |= 1 << 4; } while (0)
-#define AD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 4; } while (0)
-#define ZC_USED(desc) do { (desc).regin[1] |= 1 << 5; } while (0)
-#define ZC_MODIFIED(desc) do { (desc).regout[1] |= 1 << 5; } while (0)
-#define IL_USED(desc) do { (desc).regin[1] |= 1 << 6; } while (0)
-#define IL_MODIFIED(desc) do { (desc).regout[1] |= 1 << 6; } while (0)
-#define NR_USED(desc) do { (desc).regin[1] |= 1 << 7; } while (0)
-#define NR_MODIFIED(desc) do { (desc).regout[1] |= 1 << 7; } while (0)
-#define ZD_USED(desc) do { (desc).regin[1] |= 1 << 8; } while (0)
-#define ZD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 8; } while (0)
-#define MN_USED(desc) do { (desc).regin[1] |= 1 << 9; } while (0)
-#define MN_MODIFIED(desc) do { (desc).regout[1] |= 1 << 9; } while (0)
-#define MZ_USED(desc) do { (desc).regin[1] |= 1 << 10; } while (0)
-#define MZ_MODIFIED(desc) do { (desc).regout[1] |= 1 << 10; } while (0)
-#define MV_USED(desc) do { (desc).regin[1] |= 1 << 11; } while (0)
-#define MV_MODIFIED(desc) do { (desc).regout[1] |= 1 << 11; } while (0)
-#define MU_USED(desc) do { (desc).regin[1] |= 1 << 12; } while (0)
-#define MU_MODIFIED(desc) do { (desc).regout[1] |= 1 << 12; } while (0)
-#define MD_USED(desc) do { (desc).regin[1] |= 1 << 13; } while (0)
-#define MD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 13; } while (0)
+#define AA_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0)
+#define AA_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0)
+#define AB_USED(desc,x) do { (desc).regin[0] |= 1 << (8+(x)); } while(0)
+#define AB_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (8+(x)); } while(0)
+#define MA_USED(desc,x) do { (desc).regin[0] |= 1 << (16+(x)); } while(0)
+#define MA_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (16+(x)); } while(0)
+#define MB_USED(desc,x) do { (desc).regin[0] |= 1 << (24+(x)); } while(0)
+#define MB_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (24+(x)); } while(0)
+#define AR_USED(desc,x) do { (desc).regin[1] |= 1 << (24+(x)); } while(0)
+#define AR_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (24+(x)); } while(0)
+
+#define AZ_USED(desc) do { (desc).regin[1] |= 1 << 0; } while (0)
+#define AZ_MODIFIED(desc) do { (desc).regout[1] |= 1 << 0; } while (0)
+#define AN_USED(desc) do { (desc).regin[1] |= 1 << 1; } while (0)
+#define AN_MODIFIED(desc) do { (desc).regout[1] |= 1 << 1; } while (0)
+#define AV_USED(desc) do { (desc).regin[1] |= 1 << 2; } while (0)
+#define AV_MODIFIED(desc) do { (desc).regout[1] |= 1 << 2; } while (0)
+#define AU_USED(desc) do { (desc).regin[1] |= 1 << 3; } while (0)
+#define AU_MODIFIED(desc) do { (desc).regout[1] |= 1 << 3; } while (0)
+#define AD_USED(desc) do { (desc).regin[1] |= 1 << 4; } while (0)
+#define AD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 4; } while (0)
+#define ZC_USED(desc) do { (desc).regin[1] |= 1 << 5; } while (0)
+#define ZC_MODIFIED(desc) do { (desc).regout[1] |= 1 << 5; } while (0)
+#define IL_USED(desc) do { (desc).regin[1] |= 1 << 6; } while (0)
+#define IL_MODIFIED(desc) do { (desc).regout[1] |= 1 << 6; } while (0)
+#define NR_USED(desc) do { (desc).regin[1] |= 1 << 7; } while (0)
+#define NR_MODIFIED(desc) do { (desc).regout[1] |= 1 << 7; } while (0)
+#define ZD_USED(desc) do { (desc).regin[1] |= 1 << 8; } while (0)
+#define ZD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 8; } while (0)
+#define MN_USED(desc) do { (desc).regin[1] |= 1 << 9; } while (0)
+#define MN_MODIFIED(desc) do { (desc).regout[1] |= 1 << 9; } while (0)
+#define MZ_USED(desc) do { (desc).regin[1] |= 1 << 10; } while (0)
+#define MZ_MODIFIED(desc) do { (desc).regout[1] |= 1 << 10; } while (0)
+#define MV_USED(desc) do { (desc).regin[1] |= 1 << 11; } while (0)
+#define MV_MODIFIED(desc) do { (desc).regout[1] |= 1 << 11; } while (0)
+#define MU_USED(desc) do { (desc).regin[1] |= 1 << 12; } while (0)
+#define MU_MODIFIED(desc) do { (desc).regout[1] |= 1 << 12; } while (0)
+#define MD_USED(desc) do { (desc).regin[1] |= 1 << 13; } while (0)
+#define MD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 13; } while (0)
mb86235_frontend::mb86235_frontend(mb86235_device *core, uint32_t window_start, uint32_t window_end, uint32_t max_sequence)
@@ -137,18 +137,18 @@ void mb86235_frontend::describe_alu_input(opcode_desc &desc, int reg)
AB_USED(desc, reg & 7);
break;
- case 0x10: // PR
+ case 0x10: // PR
break;
- case 0x11: // PR++
+ case 0x11: // PR++
desc.userflags &= ~OP_USERFLAG_PR_MASK;
desc.userflags |= OP_USERFLAG_PR_INC;
break;
- case 0x12: // PR--
+ case 0x12: // PR--
desc.userflags &= ~OP_USERFLAG_PR_MASK;
desc.userflags |= OP_USERFLAG_PR_DEC;
break;
- case 0x13: // PR#0
+ case 0x13: // PR#0
desc.userflags &= ~OP_USERFLAG_PR_MASK;
desc.userflags |= OP_USERFLAG_PR_ZERO;
break;
@@ -171,23 +171,23 @@ void mb86235_frontend::describe_mul_input(opcode_desc &desc, int reg)
MB_USED(desc, reg & 7);
break;
- case 0x10: // PR
+ case 0x10: // PR
break;
- case 0x11: // PR++
- if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
+ case 0x11: // PR++
+ if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
{
desc.userflags |= OP_USERFLAG_PR_INC;
}
break;
- case 0x12: // PR--
- if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
+ case 0x12: // PR--
+ if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
{
desc.userflags |= OP_USERFLAG_PR_DEC;
}
break;
- case 0x13: // PR#0
- if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
+ case 0x13: // PR#0
+ if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
{
desc.userflags |= OP_USERFLAG_PR_ZERO;
}
@@ -248,31 +248,31 @@ void mb86235_frontend::describe_reg_read(opcode_desc &desc, int reg)
AB_USED(desc, reg & 7);
break;
- case 0x31: // FI
+ case 0x31: // FI
desc.userflags |= OP_USERFLAG_FIFOIN;
- desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
+ desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
break;
- case 0x32: // FO0
+ case 0x32: // FO0
break;
- case 0x33: // FO1
+ case 0x33: // FO1
break;
- case 0x10: // EB
- case 0x11: // EBU
- case 0x12: // EBL
- case 0x13: // EO
- case 0x15: // ST
- case 0x16: // MOD
- case 0x17: // LRPC
- case 0x34: // PDR
- case 0x35: // DDR
- case 0x36: // PRP
- case 0x37: // PWP
+ case 0x10: // EB
+ case 0x11: // EBU
+ case 0x12: // EBL
+ case 0x13: // EO
+ case 0x15: // ST
+ case 0x16: // MOD
+ case 0x17: // LRPC
+ case 0x34: // PDR
+ case 0x35: // DDR
+ case 0x36: // PRP
+ case 0x37: // PWP
break;
- case 0x30: // PR
- if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU and MUL PR updates have higher priority
+ case 0x30: // PR
+ if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU and MUL PR updates have higher priority
{
desc.userflags |= OP_USERFLAG_PR_INC;
}
@@ -305,32 +305,32 @@ void mb86235_frontend::describe_reg_write(opcode_desc &desc, int reg)
AB_MODIFIED(desc, reg & 7);
break;
- case 0x31: // FI
+ case 0x31: // FI
break;
- case 0x32: // FO0
+ case 0x32: // FO0
desc.userflags |= OP_USERFLAG_FIFOOUT0;
- desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
+ desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
break;
- case 0x33: // FO1
+ case 0x33: // FO1
desc.userflags |= OP_USERFLAG_FIFOOUT1;
- desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
+ desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
break;
- case 0x10: // EB
- case 0x11: // EBU
- case 0x12: // EBL
- case 0x13: // EO
- case 0x15: // ST
- case 0x16: // MOD
- case 0x17: // LRPC
- case 0x34: // PDR
- case 0x35: // DDR
- case 0x36: // PRP
- case 0x37: // PWP
+ case 0x10: // EB
+ case 0x11: // EBU
+ case 0x12: // EBL
+ case 0x13: // EO
+ case 0x15: // ST
+ case 0x16: // MOD
+ case 0x17: // LRPC
+ case 0x34: // PDR
+ case 0x35: // DDR
+ case 0x36: // PRP
+ case 0x37: // PWP
break;
- case 0x30: // PR
+ case 0x30: // PR
desc.userflags &= ~OP_USERFLAG_PW_MASK;
desc.userflags |= OP_USERFLAG_PW_INC;
break;
@@ -347,14 +347,14 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
switch (op)
{
- case 0x00: // FADD
+ case 0x00: // FADD
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
- case 0x01: // FADDZ
+ case 0x01: // FADDZ
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
ZC_MODIFIED(desc);
AN_MODIFIED(desc);
@@ -363,7 +363,7 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x02: // FSUB
+ case 0x02: // FSUB
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
@@ -371,7 +371,7 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x03: // FSUBZ
+ case 0x03: // FSUBZ
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
ZC_MODIFIED(desc);
AN_MODIFIED(desc);
@@ -380,7 +380,7 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x04: // FCMP
+ case 0x04: // FCMP
describe_alu_input(desc, i1); describe_alu_input(desc, i2);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
@@ -388,36 +388,36 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x05: // FABS
+ case 0x05: // FABS
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x06: // FABC
+ case 0x06: // FABC
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x07: // NOP
+ case 0x07: // NOP
break;
- case 0x08: // FEA
+ case 0x08: // FEA
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x09: // FES
+ case 0x09: // FES
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x0a: // FRCP
+ case 0x0a: // FRCP
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
ZD_MODIFIED(desc);
AN_MODIFIED(desc);
@@ -425,7 +425,7 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x0b: // FRSQ
+ case 0x0b: // FRSQ
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
NR_MODIFIED(desc);
AN_MODIFIED(desc);
@@ -433,26 +433,26 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x0c: // FLOG
+ case 0x0c: // FLOG
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
IL_MODIFIED(desc);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x0d: // CIF
+ case 0x0d: // CIF
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
break;
- case 0x0e: // CFI
+ case 0x0e: // CFI
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AD_MODIFIED(desc);
break;
- case 0x0f: // CFIB
+ case 0x0f: // CFIB
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
@@ -460,99 +460,99 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AD_MODIFIED(desc);
AU_MODIFIED(desc);
break;
- case 0x10: // ADD
+ case 0x10: // ADD
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
- case 0x11: // ADDZ
+ case 0x11: // ADDZ
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
ZC_MODIFIED(desc);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
- case 0x12: // SUB
+ case 0x12: // SUB
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
- case 0x13: // SUBZ
+ case 0x13: // SUBZ
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
ZC_MODIFIED(desc);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
- case 0x14: // CMP
+ case 0x14: // CMP
describe_alu_input(desc, i1); describe_alu_input(desc, i2);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
- case 0x15: // ABS
+ case 0x15: // ABS
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
- case 0x16: // ATR
+ case 0x16: // ATR
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
break;
- case 0x17: // ATRZ
+ case 0x17: // ATRZ
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
ZC_MODIFIED(desc);
break;
- case 0x18: // AND
+ case 0x18: // AND
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
- case 0x19: // OR
+ case 0x19: // OR
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
- case 0x1a: // XOR
+ case 0x1a: // XOR
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
- case 0x1b: // NOT
+ case 0x1b: // NOT
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
- case 0x1c: // LSR
+ case 0x1c: // LSR
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
- case 0x1d: // LSL
+ case 0x1d: // LSL
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
- case 0x1e: // ASR
+ case 0x1e: // ASR
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
break;
- case 0x1f: // ASL
+ case 0x1f: // ASL
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
@@ -593,51 +593,51 @@ void mb86235_frontend::describe_ea(opcode_desc &desc, int md, int arx, int ary,
{
switch (md)
{
- case 0x0: // @ARx
+ case 0x0: // @ARx
AR_USED(desc, arx);
break;
- case 0x1: // @ARx++
+ case 0x1: // @ARx++
AR_USED(desc, arx); AR_MODIFIED(desc, arx);
break;
- case 0x2: // @ARx--
+ case 0x2: // @ARx--
AR_USED(desc, arx); AR_MODIFIED(desc, arx);
break;
- case 0x3: // @ARx++disp
+ case 0x3: // @ARx++disp
AR_USED(desc, arx); AR_MODIFIED(desc, arx);
break;
- case 0x4: // @ARx+ARy
+ case 0x4: // @ARx+ARy
AR_USED(desc, arx); AR_USED(desc, ary);
break;
- case 0x5: // @ARx+ARy++
+ case 0x5: // @ARx+ARy++
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
- case 0x6: // @ARx+ARy--
+ case 0x6: // @ARx+ARy--
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
- case 0x7: // @ARx+ARy++disp
+ case 0x7: // @ARx+ARy++disp
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
- case 0x8: // @ARx+ARyU
+ case 0x8: // @ARx+ARyU
AR_USED(desc, arx); AR_USED(desc, ary);
break;
- case 0x9: // @ARx+ARyL
+ case 0x9: // @ARx+ARyL
AR_USED(desc, arx); AR_USED(desc, ary);
break;
- case 0xa: // @ARx+disp
+ case 0xa: // @ARx+disp
AR_USED(desc, arx);
break;
- case 0xb: // @ARx+ARy+disp
+ case 0xb: // @ARx+ARy+disp
AR_USED(desc, arx); AR_USED(desc, ary);
break;
- case 0xc: // @disp
+ case 0xc: // @disp
break;
- case 0xd: // @ARx+[ARy++]
+ case 0xd: // @ARx+[ARy++]
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
- case 0xe: // @ARx+[ARy--]
+ case 0xe: // @ARx+[ARy--]
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
- case 0xf: // @ARx+[ARy++disp]
+ case 0xf: // @ARx+[ARy++disp]
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
}
@@ -717,7 +717,7 @@ void mb86235_frontend::describe_xfer2(opcode_desc &desc)
int md = opcode & 0xf;
int disp14 = (opcode >> 7) & 0x3fff;
- if (op == 0) // MOV2
+ if (op == 0) // MOV2
{
if (trm == 0)
{
@@ -760,7 +760,7 @@ void mb86235_frontend::describe_xfer2(opcode_desc &desc)
}
}
}
- else if (op == 2) // MOV4
+ else if (op == 2) // MOV4
{
fatalerror("mb86235_frontend: describe_xfer2 MOV4 at %08X (%08X%08X)", desc.pc, (uint32_t)(opcode >> 32), (uint32_t)(opcode));
}
@@ -785,12 +785,12 @@ void mb86235_frontend::describe_xfer3(opcode_desc &desc)
switch (dr >> 5)
{
case 0:
- case 1: // reg
+ case 1: // reg
describe_reg_write(desc, dr & 0x3f);
break;
- case 2: // RAM-A
- case 3: // RAM-B
+ case 2: // RAM-A
+ case 3: // RAM-B
desc.flags |= OPFLAG_WRITES_MEMORY;
describe_ea(desc, md, dr & 7, ary, disp);
break;
@@ -806,56 +806,56 @@ void mb86235_frontend::describe_control(opcode_desc &desc)
switch (cop)
{
- case 0x00: // NOP
+ case 0x00: // NOP
break;
- case 0x01: // REP
- if (ef1 != 0) // ARx
+ case 0x01: // REP
+ if (ef1 != 0) // ARx
AR_USED(desc, (ef2 >> 12) & 7);
desc.userflags |= OP_USERFLAG_REPEAT;
break;
- case 0x02: // SETL
- if (ef1 != 0) // ARx
+ case 0x02: // SETL
+ if (ef1 != 0) // ARx
AR_USED(desc, (ef2 >> 12) & 7);
break;
- case 0x03: // CLRFI/CLRFO/CLRF
+ case 0x03: // CLRFI/CLRFO/CLRF
break;
- case 0x04: // PUSH
+ case 0x04: // PUSH
describe_reg_read(desc, (ef2 >> 6) & 0x3f);
break;
- case 0x05: // POP
+ case 0x05: // POP
describe_reg_write(desc, (ef2 >> 6) & 0x3f);
break;
- case 0x08: // SETM #imm16
+ case 0x08: // SETM #imm16
break;
- case 0x09: // SETM #imm3, CBSA
+ case 0x09: // SETM #imm3, CBSA
break;
- case 0x0a: // SETM #imm3, CBSB
+ case 0x0a: // SETM #imm3, CBSB
break;
- case 0x0b: // SETM #imm1, RF
+ case 0x0b: // SETM #imm1, RF
break;
- case 0x0c: // SETM #imm1, RDY
+ case 0x0c: // SETM #imm1, RDY
break;
- case 0x0d: // SETM #imm1, WAIT
+ case 0x0d: // SETM #imm1, WAIT
break;
- case 0x13: // DBLP rel12
+ case 0x13: // DBLP rel12
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.targetpc = desc.pc + rel12;
desc.delayslots = 1;
break;
- case 0x14: // DBBC ARx:y, rel12
+ case 0x14: // DBBC ARx:y, rel12
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.targetpc = desc.pc + rel12;
desc.delayslots = 1;
AR_USED(desc, ((desc.opptr.q[0] >> 13) & 7));
break;
- case 0x15: // DBBS ARx:y, rel12
+ case 0x15: // DBBS ARx:y, rel12
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.targetpc = desc.pc + rel12;
desc.delayslots = 1;
AR_USED(desc, ((desc.opptr.q[0] >> 13) & 7));
break;
- case 0x1b: // DRET
+ case 0x1b: // DRET
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
desc.targetpc = BRANCH_TARGET_DYNAMIC;
desc.delayslots = 1;
@@ -919,4 +919,4 @@ void mb86235_frontend::describe_control(opcode_desc &desc)
break;
}
}
-} \ No newline at end of file
+}
diff --git a/src/devices/cpu/powerpc/ppccom.cpp b/src/devices/cpu/powerpc/ppccom.cpp
index bea641ad95f..bcdc17ae9a1 100644
--- a/src/devices/cpu/powerpc/ppccom.cpp
+++ b/src/devices/cpu/powerpc/ppccom.cpp
@@ -1505,7 +1505,7 @@ void ppc_device::ppccom_tlb_flush()
void ppc_device::ppccom_get_dsisr()
{
int intent = 0;
-
+
if (m_core->param1 & 1)
{
intent = TRANSLATE_WRITE;
@@ -1514,7 +1514,7 @@ void ppc_device::ppccom_get_dsisr()
{
intent = TRANSLATE_READ;
}
-
+
m_core->param1 = ppccom_translate_address_internal(intent, m_core->param0);
}
diff --git a/src/devices/cpu/powerpc/ppcdrc.cpp b/src/devices/cpu/powerpc/ppcdrc.cpp
index 58cc8c7dc57..4ebf89a61f8 100644
--- a/src/devices/cpu/powerpc/ppcdrc.cpp
+++ b/src/devices/cpu/powerpc/ppcdrc.cpp
@@ -791,9 +791,9 @@ void ppc_device::static_generate_tlb_mismatch()
{
// DAR gets the address, DSISR gets the 'reason' flags
UML_MOV(block, SPR32(SPROEA_DAR), mem(&m_core->param0)); // mov [dar],[param0]
- m_core->param1 = 0; // always a read here
- UML_CALLC(block, (c_function)cfunc_ppccom_get_dsisr, this); // get DSISR to param1
- UML_MOV(block, SPR32(SPROEA_DSISR), mem(&m_core->param1)); // move [dsisr], [param1]
+ m_core->param1 = 0; // always a read here
+ UML_CALLC(block, (c_function)cfunc_ppccom_get_dsisr, this); // get DSISR to param1
+ UML_MOV(block, SPR32(SPROEA_DSISR), mem(&m_core->param1)); // move [dsisr], [param1]
UML_EXH(block, *m_exception[EXCEPTION_ISI], I0); // exh isi,i0
}
else
@@ -1408,9 +1408,9 @@ void ppc_device::static_generate_memory_accessor(int mode, int size, int iswrite
{
m_core->param1 = 0;
}
- UML_CALLC(block, (c_function)cfunc_ppccom_get_dsisr, this); // get DSISR to param1
- UML_MOV(block, SPR32(SPROEA_DSISR), mem(&m_core->param1)); // move [dsisr], [param1]
- UML_EXH(block, *m_exception[EXCEPTION_DSI], I0); // exh dsi,i0
+ UML_CALLC(block, (c_function)cfunc_ppccom_get_dsisr, this); // get DSISR to param1
+ UML_MOV(block, SPR32(SPROEA_DSISR), mem(&m_core->param1)); // move [dsisr], [param1]
+ UML_EXH(block, *m_exception[EXCEPTION_DSI], I0); // exh dsi,i0
}
}
diff --git a/src/devices/cpu/tms32025/tms32025.cpp b/src/devices/cpu/tms32025/tms32025.cpp
index 7b8e2352d33..0f3984f7927 100644
--- a/src/devices/cpu/tms32025/tms32025.cpp
+++ b/src/devices/cpu/tms32025/tms32025.cpp
@@ -1798,7 +1798,7 @@ void tms32025_device::device_reset()
m_data->install_ram(0x0200, 0x02ff, m_b0);
}
common_reset();
-
+
}
void tms32026_device::device_reset()
diff --git a/src/devices/machine/68230pit.cpp b/src/devices/machine/68230pit.cpp
index 0b3888ca47d..ab6cbd09a1d 100644
--- a/src/devices/machine/68230pit.cpp
+++ b/src/devices/machine/68230pit.cpp
@@ -215,7 +215,7 @@ uint8_t pit68230_device::irq_tiack()
}
/*
- * trigger_interrupt - called when a potential interrupt condition occurs
+ * trigger_interrupt - called when a potential interrupt condition occurs
* but will only generate an interrupt when the PIT is programmed to do so.
*/
void pit68230_device::trigger_interrupt(int source)
@@ -241,7 +241,7 @@ void pit68230_device::trigger_interrupt(int source)
void pit68230_device::tick_clock()
{
if (m_tcr & REG_TCR_TIMER_ENABLE)
- {
+ {
if (m_cntr-- == 0) // Zero detect
{
LOGINT(("Timer reached zero!\n"));
@@ -612,8 +612,8 @@ void pit68230_device::wr_pitreg_tcr(uint8_t data)
{
m_cntr = 0;
if (pen == 1)
- {
- LOG(("PC2 enable/disable TBD\n"));
+ {
+ LOG(("PC2 enable/disable TBD\n"));
}
if (clk == 1)
{
@@ -659,7 +659,7 @@ void pit68230_device::wr_pitreg_cprl(uint8_t data)
void pit68230_device::wr_pitreg_tsr(uint8_t data)
{
LOG(("%s(%02x) \"%s\": \n", FUNCNAME, data, tag()));
- if (data & 1)
+ if (data & 1)
{
m_tsr = 0; // A write resets the TSR;
m_tirq_out_cb(CLEAR_LINE);
diff --git a/src/devices/machine/68230pit.h b/src/devices/machine/68230pit.h
index 92bfe062b43..30850abb39b 100644
--- a/src/devices/machine/68230pit.h
+++ b/src/devices/machine/68230pit.h
@@ -216,61 +216,61 @@ class pit68230_device : public device_t//, public device_execute_interface
protected:
enum { // PGCR - Port Global Control register
- REG_PGCR_MODE_MASK = 0xc0,
- REG_PGCR_MODE_0 = 0x00, // 0 0 Unidirectional 8 bit mode
- REG_PGCR_MODE_1 = 0x40, // 0 1 Unidirectional 16 bit mode
- REG_PGCR_MODE_2 = 0x80, // 1 0 Bidirectional 8 bit mode
- REG_PGCR_MODE_3 = 0xc0, // 1 1 Bidirectional 16 bit mode
- REG_PGCR_H34_ENABLE = 0x20,
- REG_PGCR_H12_ENABLE = 0x10,
- REG_PGCR_H4_SENSE = 0x80,
- REG_PGCR_H3_SENSE = 0x40,
- REG_PGCR_H2_SENSE = 0x20,
- REG_PGCR_H1_SENSE = 0x10,
+ REG_PGCR_MODE_MASK = 0xc0,
+ REG_PGCR_MODE_0 = 0x00, // 0 0 Unidirectional 8 bit mode
+ REG_PGCR_MODE_1 = 0x40, // 0 1 Unidirectional 16 bit mode
+ REG_PGCR_MODE_2 = 0x80, // 1 0 Bidirectional 8 bit mode
+ REG_PGCR_MODE_3 = 0xc0, // 1 1 Bidirectional 16 bit mode
+ REG_PGCR_H34_ENABLE = 0x20,
+ REG_PGCR_H12_ENABLE = 0x10,
+ REG_PGCR_H4_SENSE = 0x80,
+ REG_PGCR_H3_SENSE = 0x40,
+ REG_PGCR_H2_SENSE = 0x20,
+ REG_PGCR_H1_SENSE = 0x10,
};
enum {
- REG_PACR_SUBMODE_MASK = 0xc0,
- REG_PACR_SUBMODE_0 = 0x00, // 0 0
- REG_PACR_SUBMODE_1 = 0x40, // 0 1
- REG_PACR_SUBMODE_2 = 0x80, // 1 0
- REG_PACR_SUBMODE_3 = 0xc0, // 1 1
- REG_PACR_H2_CTRL_MASK = 0x38,
- REG_PACR_H2_CTRL_IN_OUT = 0x20, // H2 sense always cleared if set
- REG_PACR_H2_CTRL_OUT_00 = 0x20, // H2 output negated
- REG_PACR_H2_CTRL_OUT_01 = 0x28, // H2 output asserted
- REG_PACR_H2_CTRL_OUT_10 = 0x30, // H2 output in interlocked input handshake protocol
- REG_PACR_H2_CTRL_OUT_11 = 0x38, // H2 output in pulsed input handshake protocol
- REG_PACR_H2_INT_ENABLE = 0x04,
- REG_PACR_H1_SVCR_ENABLE = 0x02,
- REG_PACR_H1_STATUS_CTRL = 0x01,
+ REG_PACR_SUBMODE_MASK = 0xc0,
+ REG_PACR_SUBMODE_0 = 0x00, // 0 0
+ REG_PACR_SUBMODE_1 = 0x40, // 0 1
+ REG_PACR_SUBMODE_2 = 0x80, // 1 0
+ REG_PACR_SUBMODE_3 = 0xc0, // 1 1
+ REG_PACR_H2_CTRL_MASK = 0x38,
+ REG_PACR_H2_CTRL_IN_OUT = 0x20, // H2 sense always cleared if set
+ REG_PACR_H2_CTRL_OUT_00 = 0x20, // H2 output negated
+ REG_PACR_H2_CTRL_OUT_01 = 0x28, // H2 output asserted
+ REG_PACR_H2_CTRL_OUT_10 = 0x30, // H2 output in interlocked input handshake protocol
+ REG_PACR_H2_CTRL_OUT_11 = 0x38, // H2 output in pulsed input handshake protocol
+ REG_PACR_H2_INT_ENABLE = 0x04,
+ REG_PACR_H1_SVCR_ENABLE = 0x02,
+ REG_PACR_H1_STATUS_CTRL = 0x01,
};
enum {
- REG_PBCR_SUBMODE_MASK = 0xc0,
- REG_PBCR_SUBMODE_00 = 0x00, // 0 0
- REG_PBCR_SUBMODE_01 = 0x40, // 0 1
- REG_PBCR_SUBMODE_10 = 0x80, // 1 0
- REG_PBCR_SUBMODE_11 = 0xc0, // 1 1
- REG_PBCR_SUBMODE_1X = 0x80, // submode 2 or 3
- REG_PBCR_H4_CTRL_MASK = 0x38,
- REG_PBCR_H4_CTRL_IN_OUT = 0x20, // H4 sense always cleared if set
- REG_PBCR_H4_CTRL_OUT_00 = 0x20, // H4 output negated
- REG_PBCR_H4_CTRL_OUT_01 = 0x28, // H4 output asserted
- REG_PBCR_H4_CTRL_OUT_10 = 0x30, // H4 output in interlocked input handshake protocol
- REG_PBCR_H4_CTRL_OUT_11 = 0x38, // H4 output in pulsed input handshake protocol
- REG_PBCR_H4_INT_ENABLE = 0x04,
+ REG_PBCR_SUBMODE_MASK = 0xc0,
+ REG_PBCR_SUBMODE_00 = 0x00, // 0 0
+ REG_PBCR_SUBMODE_01 = 0x40, // 0 1
+ REG_PBCR_SUBMODE_10 = 0x80, // 1 0
+ REG_PBCR_SUBMODE_11 = 0xc0, // 1 1
+ REG_PBCR_SUBMODE_1X = 0x80, // submode 2 or 3
+ REG_PBCR_H4_CTRL_MASK = 0x38,
+ REG_PBCR_H4_CTRL_IN_OUT = 0x20, // H4 sense always cleared if set
+ REG_PBCR_H4_CTRL_OUT_00 = 0x20, // H4 output negated
+ REG_PBCR_H4_CTRL_OUT_01 = 0x28, // H4 output asserted
+ REG_PBCR_H4_CTRL_OUT_10 = 0x30, // H4 output in interlocked input handshake protocol
+ REG_PBCR_H4_CTRL_OUT_11 = 0x38, // H4 output in pulsed input handshake protocol
+ REG_PBCR_H4_INT_ENABLE = 0x04,
REG_PBCR_H3_SVCRQ_ENABLE= 0x02,
- REG_PBCR_H3_STATUS_CTRL = 0x01,
+ REG_PBCR_H3_STATUS_CTRL = 0x01,
};
enum {
- REG_PCDR_TIN_BIT = 2, // BIT number
- REG_PCDR_TIN = 0x04 // bit position
+ REG_PCDR_TIN_BIT = 2, // BIT number
+ REG_PCDR_TIN = 0x04 // bit position
};
enum {
- REG_TCR_TIMER_ENABLE = 0x01
+ REG_TCR_TIMER_ENABLE = 0x01
};
enum { // TCR - Timer Control register
@@ -333,10 +333,10 @@ protected:
uint8_t m_pbdr; // Port B Data register
uint8_t m_pcdr; // Port C Data register
uint8_t m_psr; // Port Status Register
- uint8_t m_tcr; // Timer Control Register
+ uint8_t m_tcr; // Timer Control Register
uint8_t m_tivr; // Timer Interrupt Vector register
- int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
- int m_cntr; // - The 24 bit Counter
+ int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
+ int m_cntr; // - The 24 bit Counter
uint8_t m_tsr; // Timer Status Register
diff --git a/src/devices/machine/netlist.cpp b/src/devices/machine/netlist.cpp
index 2301ec49a4f..9f321b52751 100644
--- a/src/devices/machine/netlist.cpp
+++ b/src/devices/machine/netlist.cpp
@@ -249,7 +249,7 @@ void netlist_ram_pointer_t::device_start()
fatalerror("device %s wrong parameter type for %s\n", basetag(), m_param_name.cstr());
}
- m_data = (*m_param)();
+ m_data = (*m_param)();
}
// ----------------------------------------------------------------------------------------
diff --git a/src/devices/machine/netlist.h b/src/devices/machine/netlist.h
index 3a223541091..e4cee9a87fd 100644
--- a/src/devices/machine/netlist.h
+++ b/src/devices/machine/netlist.h
@@ -422,7 +422,7 @@ private:
// ----------------------------------------------------------------------------------------
class netlist_mame_int_input_t : public device_t,
- public netlist_mame_sub_interface
+ public netlist_mame_sub_interface
{
public:
@@ -514,7 +514,7 @@ private:
// ----------------------------------------------------------------------------------------
class netlist_mame_rom_t : public device_t,
- public netlist_mame_sub_interface
+ public netlist_mame_sub_interface
{
public:
@@ -544,7 +544,7 @@ private:
// ----------------------------------------------------------------------------------------
class netlist_ram_pointer_t: public device_t,
- public netlist_mame_sub_interface
+ public netlist_mame_sub_interface
{
public:
diff --git a/src/devices/machine/z80scc.h b/src/devices/machine/z80scc.h
index 496c82f4d45..ce9fa3074f3 100644
--- a/src/devices/machine/z80scc.h
+++ b/src/devices/machine/z80scc.h
@@ -409,7 +409,7 @@ protected:
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
- WR1_RX_INT_ALL = 0x10,
+ WR1_RX_INT_ALL = 0x10,
WR1_RX_INT_PARITY = 0x18,
WR1_WRDY_ON_RX_TX = 0x20,
WR1_WRDY_FUNCTION = 0x40,
diff --git a/src/devices/sound/dac76.cpp b/src/devices/sound/dac76.cpp
index 965b74473e6..67fc452b260 100644
--- a/src/devices/sound/dac76.cpp
+++ b/src/devices/sound/dac76.cpp
@@ -33,7 +33,7 @@ const device_type DAC76 = &device_creator<dac76_device>;
// dac76_device - constructor
//-------------------------------------------------
-dac76_device::dac76_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+dac76_device::dac76_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, DAC76, "DAC-76 COMDAC", tag, owner, clock, "dac76", __FILE__),
device_sound_interface(mconfig, *this),
m_stream(nullptr),
diff --git a/src/devices/sound/votrax.cpp b/src/devices/sound/votrax.cpp
index b368a35ea54..bde5fbd6086 100644
--- a/src/devices/sound/votrax.cpp
+++ b/src/devices/sound/votrax.cpp
@@ -17,11 +17,11 @@
0 - - - sram write pulse
i1.o = glottal impulse
-i2.o = white noise
+i2.o = white noise
tp1 = phi clock (tied to f2q rom access)
*/
-
+
#include "emu.h"
#include "votrax.h"
@@ -51,7 +51,7 @@ const char *const votrax_sc01_device::s_phone_table[64] =
// ladder. There is first a transistor to ground, then a series of
// seven transistors one quarter the size of the first one, then it
// finishes by an active resistor to +9V.
-//
+//
// The terminal of the transistor to ground is used as a middle value.
// Index 0 is at that value. Index 1 is at 0V. Index 2 to 8 start at
// just after the resistor down the latter. Indices 9+ are the middle
@@ -438,23 +438,23 @@ void votrax_sc01_device::chip_update()
// The formants are frozen on a pause phone unless both voice and
// noise volumes are zero.
if(tick_208 && (!m_rom_pause || !(m_filt_fa || m_filt_va))) {
- // interpolate(m_cur_va, m_rom_va);
+ // interpolate(m_cur_va, m_rom_va);
interpolate(m_cur_fc, m_rom_fc);
interpolate(m_cur_f1, m_rom_f1);
interpolate(m_cur_f2, m_rom_f2);
interpolate(m_cur_f2q, m_rom_f2q);
interpolate(m_cur_f3, m_rom_f3);
- // logerror("int fa=%x va=%x fc=%x f1=%x f2=%02x f2q=%02x f3=%x\n", m_cur_fa >> 4, m_cur_va >> 4, m_cur_fc >> 4, m_cur_f1 >> 4, m_cur_f2 >> 3, m_cur_f2q >> 4, m_cur_f3 >> 4);
- }
+ // logerror("int fa=%x va=%x fc=%x f1=%x f2=%02x f2q=%02x f3=%x\n", m_cur_fa >> 4, m_cur_va >> 4, m_cur_fc >> 4, m_cur_f1 >> 4, m_cur_f2 >> 3, m_cur_f2q >> 4, m_cur_f3 >> 4);
+ }
// Non-formant update. Same bug there, va should be updated, not fc.
if(tick_625) {
if(m_ticks >= m_rom_vd)
interpolate(m_cur_fa, m_rom_fa);
if(m_ticks >= m_rom_cld)
- // interpolate(m_cur_fc, m_rom_fc);
+ // interpolate(m_cur_fc, m_rom_fc);
interpolate(m_cur_va, m_rom_va);
- // logerror("int fa=%x va=%x fc=%x f1=%x f2=%02x f2q=%02x f3=%x\n", m_cur_fa >> 4, m_cur_va >> 4, m_cur_fc >> 4, m_cur_f1 >> 4, m_cur_f2 >> 3, m_cur_f2q >> 4, m_cur_f3 >> 4);
+ // logerror("int fa=%x va=%x fc=%x f1=%x f2=%02x f2q=%02x f3=%x\n", m_cur_fa >> 4, m_cur_va >> 4, m_cur_fc >> 4, m_cur_f1 >> 4, m_cur_f2 >> 3, m_cur_f2q >> 4, m_cur_f3 >> 4);
}
// Closure counter, reset every other tick in theory when not
@@ -466,7 +466,7 @@ void votrax_sc01_device::chip_update()
if(!m_cur_closure && (m_filt_fa || m_filt_va))
m_closure = 0;
else if(m_closure != 7 << 2)
- m_closure ++;
+ m_closure ++;
// Pitch counter. Equality comparison, so it's possible to make
// it miss by manipulating the inflection inputs, but it'll wrap.
@@ -486,7 +486,7 @@ void votrax_sc01_device::chip_update()
m_noise = ((m_noise << 1) & 0x7ffe) | inp;
m_cur_noise = !(((m_noise >> 14) ^ (m_noise >> 13)) & 1);
- // logerror("tick %02x.%03x 625=%d 208=%d pitch=%02x.%x ns=%04x ni=%d noise=%d cl=%x.%x clf=%d/%d\n", m_ticks, m_phonetick, tick_625, tick_208, m_pitch >> 2, m_pitch & 3, m_noise, inp, m_cur_noise, m_closure >> 2, m_closure & 3, m_rom_closure, m_cur_closure);
+ // logerror("tick %02x.%03x 625=%d 208=%d pitch=%02x.%x ns=%04x ni=%d noise=%d cl=%x.%x clf=%d/%d\n", m_ticks, m_phonetick, tick_625, tick_208, m_pitch >> 2, m_pitch & 3, m_noise, inp, m_cur_noise, m_closure >> 2, m_closure & 3, m_rom_closure, m_cur_closure);
}
void votrax_sc01_device::filters_commit(bool force)
@@ -600,7 +600,7 @@ stream_sample_t votrax_sc01_device::analog_calc()
double n2 = n * m_filt_fc / 15.0;
shift_hist(n2, m_noise_3);
- // 8. Apply the f2 filter, noise half,
+ // 8. Apply the f2 filter, noise half,
n2 = apply_filter(m_noise_3, m_noise_4, m_f2n_a, m_f2n_b);
shift_hist(n2, m_noise_4);
@@ -893,7 +893,7 @@ void votrax_sc01_device::build_lowpass_filter(double *a, double *b,
/*
Used to shape the white noise
-
+
+-------------------------------------------------------------------+
| |
+--|C1|--+---------|C3|----------+--|C4|--+ |
@@ -902,10 +902,10 @@ void votrax_sc01_device::build_lowpass_filter(double *a, double *b,
-|R0|-+--+-\ | | | | |\ | (1) (1) |
| >--+--(2)-+--|C2|--+---(2)-+--+-\ | | | |
0-++/ | | >--+--(2)--+--|C5|--+---(2)--+
- |/ Vo 0-++/
+ |/ Vo 0-++/
|/
Equivalent:
-
+
+------------------|R5|-------------------+
| |
+--|C1|--+---------|C3|----------+--|C4|--+
@@ -914,7 +914,7 @@ void votrax_sc01_device::build_lowpass_filter(double *a, double *b,
-|R0|-+--+-\ | | |\ |
| >--+---------|R2|----------+--+-\ |
0-++/ | | >--+
- |/ Vo 0-++/
+ |/ Vo 0-++/
|/
We assume r0 = r2
@@ -980,7 +980,7 @@ void votrax_sc01_device::build_injection_filter(double *a, double *b,
double c2b, // Switched cap, over first amp-op, bottom
double c3, // Cap between the two op-amps
double c4) // Cap over second op-amp
-{
+{
// First compute the three coefficients of H(s) = (k0 + k2*s)/(k1 - k2*s)
double k0 = m_cclock * c2t;
double k1 = m_cclock * (c1b * c3 / c2t - c2t);
diff --git a/src/devices/video/ef9369.cpp b/src/devices/video/ef9369.cpp
index d373fea132f..7d97888b845 100644
--- a/src/devices/video/ef9369.cpp
+++ b/src/devices/video/ef9369.cpp
@@ -100,5 +100,5 @@ WRITE8_MEMBER( ef9369_device::data_w )
WRITE8_MEMBER( ef9369_device::address_w )
{
- m_address = data & 0x1f; // 5-bit
+ m_address = data & 0x1f; // 5-bit
}
diff --git a/src/devices/video/ef9369.h b/src/devices/video/ef9369.h
index d31c447dba4..3689e8c6f00 100644
--- a/src/devices/video/ef9369.h
+++ b/src/devices/video/ef9369.h
@@ -48,7 +48,7 @@
//**************************************************************************
typedef device_delegate<void (int entry, bool m, uint8_t ca, uint8_t cb, uint8_t cc)> ef9369_color_update_delegate;
-#define EF9369_COLOR_UPDATE(name) void name(int entry, bool m, uint8_t ca, uint8_t cb, uint8_t cc)
+#define EF9369_COLOR_UPDATE(name) void name(int entry, bool m, uint8_t ca, uint8_t cb, uint8_t cc)
// ======================> ef9369_device
@@ -76,7 +76,7 @@ private:
ef9369_color_update_delegate m_color_update_cb;
// state
- uint8_t m_ca[NUMCOLORS], m_cb[NUMCOLORS], m_cc[NUMCOLORS]; // actually 4-bit
+ uint8_t m_ca[NUMCOLORS], m_cb[NUMCOLORS], m_cc[NUMCOLORS]; // actually 4-bit
bool m_m[NUMCOLORS];
int m_address;
};
diff --git a/src/devices/video/zeus2.cpp b/src/devices/video/zeus2.cpp
index 01806e7be3c..45750a15d4d 100644
--- a/src/devices/video/zeus2.cpp
+++ b/src/devices/video/zeus2.cpp
@@ -716,7 +716,7 @@ void zeus2_device::zeus2_register_update(offs_t offset, uint32_t oldval, int log
}
/* make sure we log anything else */
//else if (logit || m_zeusbase[0x50] != 0x0)
- // logerror("\tw[50]=%08X [5E]=%08X\n", m_zeusbase[0x50], m_zeusbase[0x5e]);
+ // logerror("\tw[50]=%08X [5E]=%08X\n", m_zeusbase[0x50], m_zeusbase[0x5e]);
}
}
break;
@@ -1634,14 +1634,14 @@ void zeus2_renderer::zeus2_draw_quad(const uint32_t *databuffer, uint32_t texdat
vert[i].p[0] += m_state->zeus_point[2];
}
//if (0)
- // //vert[i].p[0] += m_state->zbase;
- // vert[i].p[0] += reinterpret_cast<float&>(m_state->m_zeusbase[0x63]);
+ // //vert[i].p[0] += m_state->zbase;
+ // vert[i].p[0] += reinterpret_cast<float&>(m_state->m_zeusbase[0x63]);
//else {
int shift;
shift = 1024 >> m_state->m_zeusbase[0x6c];
vert[i].p[0] += shift;
- // //float zScale = reinterpret_cast<float&>(m_state->m_zeusbase[0x63]);
- // //vert[i].p[0] += zScale;
+ // //float zScale = reinterpret_cast<float&>(m_state->m_zeusbase[0x63]);
+ // //vert[i].p[0] += zScale;
//}
vert[i].p[2] += (texdata >> 16) << 2;