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Diffstat (limited to 'src/devices/machine/pci.h')
-rw-r--r--src/devices/machine/pci.h144
1 files changed, 72 insertions, 72 deletions
diff --git a/src/devices/machine/pci.h b/src/devices/machine/pci.h
index 9eeb3582dc0..37ad677a476 100644
--- a/src/devices/machine/pci.h
+++ b/src/devices/machine/pci.h
@@ -35,41 +35,41 @@ public:
uint32_t unmapped_r(offs_t offset, uint32_t mem_mask, int bank);
void unmapped_w(offs_t offset, uint32_t data, uint32_t mem_mask, int bank);
- READ32_MEMBER (unmapped0_r);
- WRITE32_MEMBER(unmapped0_w);
- READ32_MEMBER (unmapped1_r);
- WRITE32_MEMBER(unmapped1_w);
- READ32_MEMBER (unmapped2_r);
- WRITE32_MEMBER(unmapped2_w);
- READ32_MEMBER (unmapped3_r);
- WRITE32_MEMBER(unmapped3_w);
- READ32_MEMBER (unmapped4_r);
- WRITE32_MEMBER(unmapped4_w);
- READ32_MEMBER (unmapped5_r);
- WRITE32_MEMBER(unmapped5_w);
-
-
- DECLARE_READ16_MEMBER(vendor_r);
- DECLARE_READ16_MEMBER(device_r);
- DECLARE_READ16_MEMBER(command_r);
- DECLARE_WRITE16_MEMBER(command_w);
- DECLARE_READ16_MEMBER(status_r);
- DECLARE_READ32_MEMBER(class_rev_r);
- virtual DECLARE_READ8_MEMBER(cache_line_size_r);
- virtual DECLARE_READ8_MEMBER(latency_timer_r);
+ uint32_t unmapped0_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t unmapped1_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t unmapped2_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t unmapped3_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped3_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t unmapped4_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped4_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t unmapped5_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped5_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+
+
+ uint16_t vendor_r();
+ uint16_t device_r();
+ uint16_t command_r();
+ void command_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t status_r();
+ uint32_t class_rev_r();
+ virtual uint8_t cache_line_size_r();
+ virtual uint8_t latency_timer_r();
virtual uint8_t header_type_r();
- virtual DECLARE_READ8_MEMBER(bist_r);
- DECLARE_READ32_MEMBER(address_base_r);
- DECLARE_WRITE32_MEMBER(address_base_w);
- DECLARE_READ16_MEMBER(subvendor_r);
- DECLARE_READ16_MEMBER(subsystem_r);
- DECLARE_READ32_MEMBER (expansion_base_r);
- DECLARE_WRITE32_MEMBER(expansion_base_w);
- virtual DECLARE_READ8_MEMBER(capptr_r);
- DECLARE_READ8_MEMBER(interrupt_line_r);
- DECLARE_WRITE8_MEMBER(interrupt_line_w);
- DECLARE_READ8_MEMBER(interrupt_pin_r);
- DECLARE_WRITE8_MEMBER(interrupt_pin_w);
+ virtual uint8_t bist_r();
+ uint32_t address_base_r(offs_t offset);
+ void address_base_w(offs_t offset, uint32_t data);
+ uint16_t subvendor_r();
+ uint16_t subsystem_r();
+ uint32_t expansion_base_r();
+ void expansion_base_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ virtual uint8_t capptr_r();
+ uint8_t interrupt_line_r();
+ void interrupt_line_w(offs_t offset, uint8_t data, uint8_t mem_mask = ~0);
+ uint8_t interrupt_pin_r();
+ void interrupt_pin_w(offs_t offset, uint8_t data, uint8_t mem_mask = ~0);
protected:
pci_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
@@ -156,40 +156,40 @@ public:
virtual void config_map(address_map &map) override;
- DECLARE_READ32_MEMBER (b_address_base_r);
- DECLARE_WRITE32_MEMBER(b_address_base_w);
- DECLARE_READ8_MEMBER (primary_bus_r);
- DECLARE_WRITE8_MEMBER (primary_bus_w);
- DECLARE_READ8_MEMBER (secondary_bus_r);
- DECLARE_WRITE8_MEMBER (secondary_bus_w);
- DECLARE_READ8_MEMBER (subordinate_bus_r);
- DECLARE_WRITE8_MEMBER (subordinate_bus_w);
- DECLARE_READ8_MEMBER (secondary_latency_r);
- DECLARE_WRITE8_MEMBER (secondary_latency_w);
- DECLARE_READ8_MEMBER (iobase_r);
- DECLARE_WRITE8_MEMBER (iobase_w);
- DECLARE_READ8_MEMBER (iolimit_r);
- DECLARE_WRITE8_MEMBER (iolimit_w);
- DECLARE_READ16_MEMBER (secondary_status_r);
- DECLARE_WRITE16_MEMBER(secondary_status_w);
- DECLARE_READ16_MEMBER (memory_base_r);
- DECLARE_WRITE16_MEMBER(memory_base_w);
- DECLARE_READ16_MEMBER (memory_limit_r);
- DECLARE_WRITE16_MEMBER(memory_limit_w);
- DECLARE_READ16_MEMBER (prefetch_base_r);
- DECLARE_WRITE16_MEMBER(prefetch_base_w);
- DECLARE_READ16_MEMBER (prefetch_limit_r);
- DECLARE_WRITE16_MEMBER(prefetch_limit_w);
- DECLARE_READ32_MEMBER (prefetch_baseu_r);
- DECLARE_WRITE32_MEMBER(prefetch_baseu_w);
- DECLARE_READ32_MEMBER (prefetch_limitu_r);
- DECLARE_WRITE32_MEMBER(prefetch_limitu_w);
- DECLARE_READ16_MEMBER (iobaseu_r);
- DECLARE_WRITE16_MEMBER(iobaseu_w);
- DECLARE_READ16_MEMBER (iolimitu_r);
- DECLARE_WRITE16_MEMBER(iolimitu_w);
- DECLARE_READ16_MEMBER (bridge_control_r);
- DECLARE_WRITE16_MEMBER(bridge_control_w);
+ uint32_t b_address_base_r(offs_t offset);
+ void b_address_base_w(offs_t offset, uint32_t data);
+ uint8_t primary_bus_r();
+ void primary_bus_w(uint8_t data);
+ uint8_t secondary_bus_r();
+ void secondary_bus_w(uint8_t data);
+ uint8_t subordinate_bus_r();
+ void subordinate_bus_w(uint8_t data);
+ uint8_t secondary_latency_r();
+ void secondary_latency_w(uint8_t data);
+ uint8_t iobase_r();
+ void iobase_w(uint8_t data);
+ uint8_t iolimit_r();
+ void iolimit_w(uint8_t data);
+ uint16_t secondary_status_r();
+ void secondary_status_w(uint16_t data);
+ uint16_t memory_base_r();
+ void memory_base_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t memory_limit_r();
+ void memory_limit_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t prefetch_base_r();
+ void prefetch_base_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t prefetch_limit_r();
+ void prefetch_limit_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint32_t prefetch_baseu_r();
+ void prefetch_baseu_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t prefetch_limitu_r();
+ void prefetch_limitu_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint16_t iobaseu_r();
+ void iobaseu_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t iolimitu_r();
+ void iolimitu_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t bridge_control_r();
+ void bridge_control_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
protected:
enum
@@ -240,10 +240,10 @@ public:
protected:
pci_host_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_READ32_MEMBER(config_address_r);
- DECLARE_WRITE32_MEMBER(config_address_w);
- DECLARE_READ32_MEMBER(config_data_r);
- DECLARE_WRITE32_MEMBER(config_data_w);
+ uint32_t config_address_r();
+ void config_address_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t config_data_r(offs_t offset, uint32_t mem_mask = ~0);
+ void config_data_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
virtual void device_start() override;
virtual void device_reset() override;