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Diffstat (limited to 'src/devices/machine/atmel_arm_aic.h')
-rw-r--r--src/devices/machine/atmel_arm_aic.h42
1 files changed, 21 insertions, 21 deletions
diff --git a/src/devices/machine/atmel_arm_aic.h b/src/devices/machine/atmel_arm_aic.h
index 0e9e2fcdd21..cc0388d21f3 100644
--- a/src/devices/machine/atmel_arm_aic.h
+++ b/src/devices/machine/atmel_arm_aic.h
@@ -52,29 +52,29 @@ private:
void pop_level() { if (m_lvlidx) --m_lvlidx; };
int get_level() { return m_level_stack[m_lvlidx]; };
- DECLARE_READ32_MEMBER(irq_vector_r);
- DECLARE_READ32_MEMBER(firq_vector_r);
- DECLARE_READ32_MEMBER(aic_isr_r) { return m_status; };
- DECLARE_READ32_MEMBER(aic_cisr_r) { return m_core_status; };
- DECLARE_READ32_MEMBER(aic_ipr_r) { return m_irqs_pending; };
- DECLARE_READ32_MEMBER(aic_imr_r) { return m_irqs_enabled; };
- DECLARE_READ32_MEMBER(aic_ffsr_r) { return m_fast_irqs; };
+ uint32_t irq_vector_r();
+ uint32_t firq_vector_r();
+ uint32_t aic_isr_r() { return m_status; };
+ uint32_t aic_cisr_r() { return m_core_status; };
+ uint32_t aic_ipr_r() { return m_irqs_pending; };
+ uint32_t aic_imr_r() { return m_irqs_enabled; };
+ uint32_t aic_ffsr_r() { return m_fast_irqs; };
// can't use ram() and share() in device submaps
- DECLARE_READ32_MEMBER(aic_smr_r) { return m_aic_smr[offset]; };
- DECLARE_READ32_MEMBER(aic_svr_r) { return m_aic_svr[offset]; };
- DECLARE_WRITE32_MEMBER(aic_smr_w) { COMBINE_DATA(&m_aic_smr[offset]); };
- DECLARE_WRITE32_MEMBER(aic_svr_w) { COMBINE_DATA(&m_aic_svr[offset]); };
- DECLARE_WRITE32_MEMBER(aic_spu_w) { COMBINE_DATA(&m_spurious_vector); };
- DECLARE_WRITE32_MEMBER(aic_dcr_w) { COMBINE_DATA(&m_debug); check_irqs(); };
- DECLARE_WRITE32_MEMBER(aic_ffer_w) { m_fast_irqs |= data & mem_mask; check_irqs(); };
- DECLARE_WRITE32_MEMBER(aic_ffdr_w) { m_fast_irqs &= ~(data & mem_mask) | 1; check_irqs(); };
-
- DECLARE_WRITE32_MEMBER(aic_iecr_w) { m_irqs_enabled |= data & mem_mask; check_irqs(); };
- DECLARE_WRITE32_MEMBER(aic_idcr_w) { m_irqs_enabled &= ~(data & mem_mask); check_irqs(); };
- DECLARE_WRITE32_MEMBER(aic_iccr_w) { m_irqs_pending &= ~(data & mem_mask); check_irqs(); };
- DECLARE_WRITE32_MEMBER(aic_iscr_w) { m_irqs_pending |= data & mem_mask; check_irqs(); };
- DECLARE_WRITE32_MEMBER(aic_eoicr_w) { m_status = 0; pop_level(); check_irqs(); };
+ uint32_t aic_smr_r(offs_t offset) { return m_aic_smr[offset]; };
+ uint32_t aic_svr_r(offs_t offset) { return m_aic_svr[offset]; };
+ void aic_smr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { COMBINE_DATA(&m_aic_smr[offset]); };
+ void aic_svr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { COMBINE_DATA(&m_aic_svr[offset]); };
+ void aic_spu_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { COMBINE_DATA(&m_spurious_vector); };
+ void aic_dcr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { COMBINE_DATA(&m_debug); check_irqs(); };
+ void aic_ffer_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { m_fast_irqs |= data & mem_mask; check_irqs(); };
+ void aic_ffdr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { m_fast_irqs &= ~(data & mem_mask) | 1; check_irqs(); };
+
+ void aic_iecr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { m_irqs_enabled |= data & mem_mask; check_irqs(); };
+ void aic_idcr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { m_irqs_enabled &= ~(data & mem_mask); check_irqs(); };
+ void aic_iccr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { m_irqs_pending &= ~(data & mem_mask); check_irqs(); };
+ void aic_iscr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { m_irqs_pending |= data & mem_mask; check_irqs(); };
+ void aic_eoicr_w(uint32_t data) { m_status = 0; pop_level(); check_irqs(); };
};
#endif