summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/machine/68340sim.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'src/devices/machine/68340sim.cpp')
-rw-r--r--src/devices/machine/68340sim.cpp133
1 files changed, 79 insertions, 54 deletions
diff --git a/src/devices/machine/68340sim.cpp b/src/devices/machine/68340sim.cpp
index 9f351cade15..4ef9a9c28a0 100644
--- a/src/devices/machine/68340sim.cpp
+++ b/src/devices/machine/68340sim.cpp
@@ -9,23 +9,21 @@
// MACROS / CONSTANTS
//**************************************************************************
-//#define LOG_GENERAL (1U << 0) // Already defined in logmacro.h
-#define LOG_SETUP (1U << 1)
-#define LOG_READ (1U << 2)
-#define LOG_PORTS (1U << 3)
-#define LOG_SIM (1U << 4)
-#define LOG_CLOCK (1U << 5)
-#define LOG_DATA (1U << 6)
-#define LOG_INT (1U << 7)
-#define LOG_PIT (1U << 8)
-#define LOG_CS (1U << 9)
+#define LOG_SETUP (1U << 1)
+#define LOG_READ (1U << 2)
+#define LOG_PORTS (1U << 3)
+#define LOG_SIM (1U << 4)
+#define LOG_CLOCK (1U << 5)
+#define LOG_DATA (1U << 6)
+#define LOG_INT (1U << 7)
+#define LOG_PIT (1U << 8)
+#define LOG_CS (1U << 9)
#define VERBOSE (LOG_PIT)
#define LOG_OUTPUT_FUNC printf // Needs always to be enabled as the default value 'logerror' is not available here
#include "logmacro.h"
-//#define LOG(...) LOGMASKED(LOG_GENERAL, __VA_ARGS__) // Already defined in logmacro.h
#define LOGSETUP(...) LOGMASKED(LOG_SETUP, __VA_ARGS__)
#define LOGR(...) LOGMASKED(LOG_READ, __VA_ARGS__)
#define LOGPORTS(...) LOGMASKED(LOG_PORTS, __VA_ARGS__)
@@ -115,7 +113,7 @@ void m68340_cpu_device::m68340_internal_sim_w(offs_t offset, uint16_t data, uint
LOGSIM("PC: %08x %s %04x, %04x (%04x) (MCR - Module Configuration Register)\n", m_ppc, FUNCNAME, offset * 2, data, mem_mask);
LOGPIT("- FRZ1: Watchdog and PIT timer are %s\n", (data & m68340_sim::REG_MCR_FRZ1) == 0 ? "enabled" : "disabled");
LOGSIM("- FRZ0: The BUS monitor is %s\n", (data & m68340_sim::REG_MCR_FRZ0) == 0 ? "enabled" : "disabled");
- LOGSIM("- FIRQ: Full Interrupt Request Mode %s\n", data & m68340_sim::REG_MCR_FIRQ ? "used on port B" : "supressed, adding 4 chip select lines on Port B");
+ LOGSIM("- FIRQ: Full Interrupt Request Mode %s\n", data & m68340_sim::REG_MCR_FIRQ ? "used on port B" : "suppressed, adding 4 chip select lines on Port B");
LOGSIM("- SHEN0-SHEN1: Show Cycle Enable %02x - not implemented\n", ((data & m68340_sim::REG_MCR_SHEN) >> 8));
LOGSIM("- Supervisor registers %s - not implemented\n", data & m68340_sim::REG_MCR_SVREG ? "requries supervisor privileges" : "can be accessed by user privileged software");
LOGSIM("- Interrupt Arbitration level: %02x\n", data & m68340_sim::REG_MCR_ARBLV);
@@ -210,7 +208,7 @@ uint8_t m68340_cpu_device::m68340_internal_sim_ports_r(offs_t offset)
sim.m_porta &= sim.m_ddra;
// TODO: call callback
- if (!m_pa_in_cb.isnull())
+ if (!m_pa_in_cb.isunset())
{
sim.m_porta |= (m_pa_in_cb() & ~sim.m_ddra);
}
@@ -241,12 +239,13 @@ uint8_t m68340_cpu_device::m68340_internal_sim_ports_r(offs_t offset)
case m68340_sim::REG_PORTB1:
LOGR("- %08x %s %04x (PORTB1 - Port B Data 1)\n", m_ppc, FUNCNAME, offset);
// Fallthrough to mirror register
+ [[fallthrough]];
case m68340_sim::REG_PORTB:
LOGR("- %08x %s %04x (PORTB - Port B Data 0)\n", m_ppc, FUNCNAME, offset);
sim.m_portb &= sim.m_ddrb;
// TODO: call callback
- if (!m_pb_in_cb.isnull())
+ if (!m_pb_in_cb.isunset())
{
sim.m_portb |= (m_pb_in_cb() & ~sim.m_ddrb);
}
@@ -317,6 +316,7 @@ void m68340_cpu_device::m68340_internal_sim_ports_w(offs_t offset, uint8_t data)
case m68340_sim::REG_PORTB1:
LOGDATA("- %08x %04x, %02x (PORTB1 - Port B Data - mirror)\n", m_ppc, offset,data);
// Falling through to mirrored register portb
+ [[fallthrough]];
case m68340_sim::REG_PORTB:
LOGDATA("- %08x %04x, %02x (PORTB - Port B Data)\n", m_ppc, offset,data);
sim.m_portb = (data & sim.m_ddrb & sim.m_pparb);
@@ -342,87 +342,120 @@ void m68340_cpu_device::m68340_internal_sim_ports_w(offs_t offset, uint8_t data)
}
}
-uint32_t m68340_cpu_device::m68340_internal_sim_cs_r(offs_t offset, uint32_t mem_mask)
+uint16_t m68340_cpu_device::m68340_internal_sim_cs_r(offs_t offset, uint16_t mem_mask)
{
+ uint32_t data = 0;
LOGR("%s\n", FUNCNAME);
- offset += m68340_sim::REG_AM_CS0>>2;
+ offset += m68340_sim::REG_AM_CS0>>1;
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
- switch (offset<<2)
+ switch (offset << 1)
{
- case m68340_sim::REG_AM_CS0: return sim.m_am[0];
- case m68340_sim::REG_BA_CS0: return sim.m_ba[0];
- case m68340_sim::REG_AM_CS1: return sim.m_am[1];
- case m68340_sim::REG_BA_CS1: return sim.m_ba[1];
- case m68340_sim::REG_AM_CS2: return sim.m_am[2];
- case m68340_sim::REG_BA_CS2: return sim.m_ba[2];
- case m68340_sim::REG_AM_CS3: return sim.m_am[3];
- case m68340_sim::REG_BA_CS3: return sim.m_ba[3];
+ case m68340_sim::REG_AM_CS0: data = sim.m_am[0]; break;
+ case m68340_sim::REG_BA_CS0: data = sim.m_ba[0]; break;
+ case m68340_sim::REG_AM_CS1: data = sim.m_am[1]; break;
+ case m68340_sim::REG_BA_CS1: data = sim.m_ba[1]; break;
+ case m68340_sim::REG_AM_CS2: data = sim.m_am[2]; break;
+ case m68340_sim::REG_BA_CS2: data = sim.m_ba[2]; break;
+ case m68340_sim::REG_AM_CS3: data = sim.m_am[3]; break;
+ case m68340_sim::REG_BA_CS3: data = sim.m_ba[3]; break;
default:
- logerror("%08x m68340_internal_sim_r %08x, (%08x)\n", m_ppc, offset*4,mem_mask);
+ logerror("%08x m68340_internal_sim_r %08x, (%08x)\n", m_ppc, offset*2,mem_mask);
}
- return 0x00000000;
+ return (BIT(offset,0) ? data : (data >> 16)) & 0xffff;
}
-void m68340_cpu_device::m68340_internal_sim_cs_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+void m68340_cpu_device::m68340_internal_sim_cs_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
LOG("%s\n", FUNCNAME);
- offset += m68340_sim::REG_AM_CS0>>2;
- if (offset & 1)
+ offset += m68340_sim::REG_AM_CS0>>1;
+
+ if (BIT(offset, 1))
{
- LOGCS("%08x Base address CS%d %08x, %08x (%08x) ", m_ppc, (offset - 0x10) / 2, offset * 4, data, mem_mask);
- LOGCS("- Base: %08x BFC:%02x WP:%d FTE:%d NCS:%d Valid: %s\n", data & 0xffffff00, (data & 0xf0) >> 4, data & 0x08 ? 1 : 0, data & 0x04 ? 1 : 0, data & 0x02 ? 1 : 0, data & 0x01 ? "Yes" : "No");
+ if (BIT(offset, 0))
+ {
+ LOGCS("%08x (LSWORD) Base address CS%d %08x, %04x (%04x) ", m_ppc, (offset - 0x20) / 2, offset * 2, data, mem_mask);
+ LOGCS("- Base: %04x BFC:%02x WP:%d FTE:%d NCS:%d Valid: %s\n", data & 0xff00, (data & 0xf0) >> 4, data & 0x08 ? 1 : 0, data & 0x04 ? 1 : 0, data & 0x02 ? 1 : 0, data & 0x01 ? "Yes" : "No");
+ }
+ else
+ {
+ LOGCS("%08x (MSWORD) Base address CS%d %08x, %04x (%04x) ", m_ppc, (offset - 0x20) / 2, offset * 2, data, mem_mask);
+ LOGCS("- Base: %04x\n", data);
+ }
}
else
{
- LOGCS("%08x Address mask CS%d %08x, %08x (%08x) ", m_ppc, (offset - 0x10) / 2, offset * 4, data, mem_mask);
- LOGCS("- Mask: %08x FCM:%02x DD:%d PS: %s\n", data & 0xffffff00, (data & 0xf0) >> 4, (data >> 2) & 0x03, std::array<char const *, 4>{{"Reserved", "16-Bit", "8-bit", "External DSACK response"}}[data & 0x03]);
+ if (BIT(offset, 0))
+ {
+ LOGCS("%08x Address mask CS%d %08x, %04x (%04x) ", m_ppc, (offset - 0x20) / 2, offset * 2, data, mem_mask);
+ LOGCS("- FCM:%02x DD:%d PS: %s\n", (data & 0xf0) >> 4, (data >> 2) & 0x03, std::array<char const *, 4>{{"Reserved", "16-Bit", "8-bit", "External DSACK response"}}[data & 0x03]);
+ }
+ else
+ {
+ LOGCS("%08x Address mask CS%d %08x, %04x (%04x) ", m_ppc, (offset - 0x20) / 2, offset * 2, data, mem_mask);
+ LOGCS("- Mask: %04x\n", data & 0xff00);
+ }
}
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
- switch (offset << 2)
+ auto const combine_data32 =
+ [&offset, &data, &mem_mask] (uint32_t *varptr)
+ {
+ uint32_t data32 = data;
+ uint32_t mem_mask32 = mem_mask;
+
+ if (!BIT(offset,0))
+ {
+ data32 <<= 16;
+ mem_mask32 <<= 16;
+ }
+
+ *varptr = (*varptr & ~mem_mask32) | (data32 & mem_mask32);
+ };
+
+ switch ((offset << 1) & ~3)
{
case m68340_sim::REG_AM_CS0:
- COMBINE_DATA(&sim.m_am[0]);
+ combine_data32(&sim.m_am[0]);
break;
case m68340_sim::REG_BA_CS0:
- COMBINE_DATA(&sim.m_ba[0]);
+ combine_data32(&sim.m_ba[0]);
break;
case m68340_sim::REG_AM_CS1:
- COMBINE_DATA(&sim.m_am[1]);
+ combine_data32(&sim.m_am[1]);
break;
case m68340_sim::REG_BA_CS1:
- COMBINE_DATA(&sim.m_ba[1]);
+ combine_data32(&sim.m_ba[1]);
break;
case m68340_sim::REG_AM_CS2:
- COMBINE_DATA(&sim.m_am[2]);
+ combine_data32(&sim.m_am[2]);
break;
case m68340_sim::REG_BA_CS2:
- COMBINE_DATA(&sim.m_ba[2]);
+ combine_data32(&sim.m_ba[2]);
break;
case m68340_sim::REG_AM_CS3:
- COMBINE_DATA(&sim.m_am[3]);
+ combine_data32(&sim.m_am[3]);
break;
case m68340_sim::REG_BA_CS3:
- COMBINE_DATA(&sim.m_ba[3]);
+ combine_data32(&sim.m_ba[3]);
break;
default:
- logerror("%08x m68340_internal_sim_cs_w %08x, %08x (%08x)\n", m_ppc, offset*4,data,mem_mask);
+ logerror("%08x m68340_internal_sim_cs_w %08x, %08x (%08x)\n", m_ppc, offset*2,data,mem_mask);
break;
}
}
@@ -436,15 +469,7 @@ void m68340_cpu_device::start_68340_sim()
{
LOG("%s\n", FUNCNAME);
LOGCLOCK( " - Clock: %d [0x%08x]\n", clock(), clock());
- m_irq_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(m68340_cpu_device::periodic_interrupt_timer_callback),this));
-
- // resolve callbacks Port A
- m_pa_out_cb.resolve_safe();
- m_pa_in_cb.resolve();
-
- // resolve callbacks Port B
- m_pb_out_cb.resolve_safe();
- m_pb_in_cb.resolve();
+ m_irq_timer = timer_alloc(FUNC(m68340_cpu_device::periodic_interrupt_timer_callback), this);
// Setup correct VCO/clock speed based on reset values and crystal
assert(m_m68340SIM);
@@ -527,7 +552,7 @@ void m68340_cpu_device::do_tick_pit()
}
}
-WRITE_LINE_MEMBER( m68340_cpu_device::extal_w )
+void m68340_cpu_device::extal_w(int state)
{
LOGPIT("%s H1 set to %d\n", FUNCNAME, state);
m_extal = state;