diff options
Diffstat (limited to 'src/devices/cpu')
42 files changed, 155 insertions, 58 deletions
diff --git a/src/devices/cpu/arcompact/arcompact_make.py b/src/devices/cpu/arcompact/arcompact_make.py index 080fd72b426..30aba810a99 100644 --- a/src/devices/cpu/arcompact/arcompact_make.py +++ b/src/devices/cpu/arcompact/arcompact_make.py @@ -1,5 +1,6 @@ #!/usr/bin/python - +# license:BSD-3-Clause +# copyright-holders:David Haywood from __future__ import print_function import sys diff --git a/src/devices/cpu/es5510/es5510.cpp b/src/devices/cpu/es5510/es5510.cpp index 17a73204f09..28be6e56f8b 100644 --- a/src/devices/cpu/es5510/es5510.cpp +++ b/src/devices/cpu/es5510/es5510.cpp @@ -422,12 +422,12 @@ WRITE8_MEMBER(es5510_device::host_w) break; /* 0x03 to 0x08 INSTR Register */ - case 0x03: instr_latch = ((instr_latch&U64(0x00ffffffffff)) | ((INT64)data&0xff)<<40); LOG(("ES5510: Host Write INSTR latch[5] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break; - case 0x04: instr_latch = ((instr_latch&U64(0xff00ffffffff)) | ((INT64)data&0xff)<<32); LOG(("ES5510: Host Write INSTR latch[4] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break; - case 0x05: instr_latch = ((instr_latch&U64(0xffff00ffffff)) | ((INT64)data&0xff)<<24); LOG(("ES5510: Host Write INSTR latch[3] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break; - case 0x06: instr_latch = ((instr_latch&U64(0xffffff00ffff)) | ((INT64)data&0xff)<<16); LOG(("ES5510: Host Write INSTR latch[2] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break; - case 0x07: instr_latch = ((instr_latch&U64(0xffffffff00ff)) | ((INT64)data&0xff)<< 8); LOG(("ES5510: Host Write INSTR latch[1] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break; - case 0x08: instr_latch = ((instr_latch&U64(0xffffffffff00)) | ((INT64)data&0xff)<< 0); LOG(("ES5510: Host Write INSTR latch[0] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break; + case 0x03: instr_latch = ((instr_latch&U64(0x00ffffffffff)) | ((INT64)data&0xff)<<40); LOG(("%s",string_format("ES5510: Host Write INSTR latch[5] = %02x -> %012I64x\n", data, instr_latch).c_str())); break; + case 0x04: instr_latch = ((instr_latch&U64(0xff00ffffffff)) | ((INT64)data&0xff)<<32); LOG(("%s",string_format("ES5510: Host Write INSTR latch[4] = %02x -> %012I64x\n", data, instr_latch).c_str())); break; + case 0x05: instr_latch = ((instr_latch&U64(0xffff00ffffff)) | ((INT64)data&0xff)<<24); LOG(("%s",string_format("ES5510: Host Write INSTR latch[3] = %02x -> %012I64x\n", data, instr_latch).c_str())); break; + case 0x06: instr_latch = ((instr_latch&U64(0xffffff00ffff)) | ((INT64)data&0xff)<<16); LOG(("%s",string_format("ES5510: Host Write INSTR latch[2] = %02x -> %012I64x\n", data, instr_latch).c_str())); break; + case 0x07: instr_latch = ((instr_latch&U64(0xffffffff00ff)) | ((INT64)data&0xff)<< 8); LOG(("%s",string_format("ES5510: Host Write INSTR latch[1] = %02x -> %012I64x\n", data, instr_latch).c_str())); break; + case 0x08: instr_latch = ((instr_latch&U64(0xffffffffff00)) | ((INT64)data&0xff)<< 0); LOG(("%s",string_format("ES5510: Host Write INSTR latch[0] = %02x -> %012I64x\n", data, instr_latch).c_str())); break; /* 0x09 to 0x0b DIL Register (r/o) */ @@ -477,7 +477,7 @@ WRITE8_MEMBER(es5510_device::host_w) break; case 0x80: /* Read select - GPR + INSTR */ - LOG(("ES5510: Host Read INSTR+GPR %02x (%s): %012" I64FMT "x %06x (%d)\n", data, REGNAME(data & 0xff), instr[data] & U64(0xffffffffffff), gpr[data] & 0xffffff, gpr[data])); + LOG(("%s",string_format("ES5510: Host Read INSTR+GPR %02x (%s): %012I64x %06x (%d)\n", data, REGNAME(data & 0xff), instr[data] & U64(0xffffffffffff), gpr[data] & 0xffffff, gpr[data]).c_str())); /* Check if an INSTR address is selected */ if (data < 0xa0) { @@ -498,7 +498,7 @@ WRITE8_MEMBER(es5510_device::host_w) case 0xc0: /* Write select - INSTR */ #if VERBOSE DESCRIBE_INSTR(buf, instr_latch, gpr[data], NULL, NULL, NULL, NULL); - LOG(("ES5510: Host Write INSTR %02x %012" I64FMT "x: %s\n", data, instr_latch&U64(0xffffffffffff), buf)); + LOG(("%s",string_format("ES5510: Host Write INSTR %02x %012I64x: %s\n", data, instr_latch&U64(0xffffffffffff), buf).c_str())); #endif if (data < 0xa0) { instr[data] = instr_latch&U64(0xffffffffffff); @@ -508,7 +508,7 @@ WRITE8_MEMBER(es5510_device::host_w) case 0xe0: /* Write select - GPR + INSTR */ #if VERBOSE DESCRIBE_INSTR(buf, instr_latch, gpr_latch, NULL, NULL, NULL, NULL); - LOG(("ES5510: Host Write INSTR+GPR %02x (%s): %012" I64FMT "x %06x (%d): %s\n", data, REGNAME(data&0xff), instr_latch, gpr_latch, SX(gpr_latch), buf)); + LOG(("%s",string_format("ES5510: Host Write INSTR+GPR %02x (%s): %012I64x %06x (%d): %s\n", data, REGNAME(data&0xff), instr_latch, gpr_latch, SX(gpr_latch), buf).c_str())); #endif if (data < 0xa0) { instr[data] = instr_latch; @@ -675,7 +675,7 @@ void es5510_device::list_program(void(p)(const char *, ...)) { UINT8 cReg = (UINT8)((instr[addr] >> 32) & 0xff); UINT8 dReg = (UINT8)((instr[addr] >> 40) & 0xff); DESCRIBE_INSTR(buf, instr[addr], gpr[addr], name[aReg], name[bReg], name[cReg], name[dReg]); - p("%02x: %012" I64FMT "x %06x (%8d) %s\n", addr, instr[addr], gpr[addr]&0xffffff, SX(gpr[addr]&0xffffff), buf); + p("%s",string_format("%02x: %012I64x %06x (%8d) %s\n", addr, instr[addr], gpr[addr]&0xffffff, SX(gpr[addr]&0xffffff), buf).c_str()); } for (; addr < 0xc0; addr++) { p("%02x: %06x (%d)\n", addr, gpr[addr]&0xffffff, SX(gpr[addr]&0xffffff)); @@ -701,7 +701,7 @@ void es5510_device::execute_run() { #if VERBOSE_EXEC char buf[1024]; DESCRIBE_INSTR(buf, instr[pc], gpr[pc], NULL, NULL, NULL, NULL); - LOG_EXEC(("EXECUTING %02x: %012" I64FMT "x %06x %s\n", pc, instr[pc], gpr[pc]&0xffffff, buf)); + LOG_EXEC(("%s",string_format("EXECUTING %02x: %012I64x %06x %s\n", pc, instr[pc], gpr[pc]&0xffffff, buf).c_str())); #endif ram_pp = ram_p; diff --git a/src/devices/cpu/h8/h8.lst b/src/devices/cpu/h8/h8.lst index 3ec1f46fbe4..56fcd25a548 100644 --- a/src/devices/cpu/h8/h8.lst +++ b/src/devices/cpu/h8/h8.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert macro bxx_any %cond prefetch_start(); TMP2 = read16i(TMP1); diff --git a/src/devices/cpu/h8/h8make.py b/src/devices/cpu/h8/h8make.py index 929b5d14c4e..2115bc01cbe 100644 --- a/src/devices/cpu/h8/h8make.py +++ b/src/devices/cpu/h8/h8make.py @@ -1,5 +1,6 @@ #!/usr/bin/python - +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert from __future__ import print_function USAGE = """ diff --git a/src/devices/cpu/m6502/ddeco16.lst b/src/devices/cpu/m6502/ddeco16.lst index b57f2614cf0..9c84900e98b 100644 --- a/src/devices/cpu/m6502/ddeco16.lst +++ b/src/devices/cpu/m6502/ddeco16.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # deco16 - deco variant brk_16_imp ora_idx ill_non ill_non ill_non ora_zpg asl_zpg ill_non php_imp ora_imm asl_acc u0B_zpg ill_non ora_aba asl_aba ill_non bpl_rel ora_idy ill_non u13_zpg ill_non ora_zpx asl_zpx ill_non clc_imp ora_aby ill_non ill_non ill_non ora_abx asl_abx ill_non diff --git a/src/devices/cpu/m6502/dm4510.lst b/src/devices/cpu/m6502/dm4510.lst index 6de7627ebc7..eae3c8ef006 100644 --- a/src/devices/cpu/m6502/dm4510.lst +++ b/src/devices/cpu/m6502/dm4510.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # m4510 - 65ce02 with a mmu brk_ce_imp ora_ce_idx cle_imp see_imp tsb_ce_zpg ora_ce_zpg asl_ce_zpg rmb_ce_bzp php_ce_imp ora_imm asl_ce_acc tsy_imp tsb_ce_aba ora_aba asl_ce_aba bbr_ce_zpb bpl_ce_rel ora_ce_idy ora_idz bpl_rw2 trb_ce_zpg ora_ce_zpx asl_ce_zpx rmb_ce_bzp clc_ce_imp ora_ce_aby inc_ce_acc inz_imp trb_ce_aba ora_ce_abx asl_ce_abx bbr_ce_zpb diff --git a/src/devices/cpu/m6502/dm6502.lst b/src/devices/cpu/m6502/dm6502.lst index 335cae3d2e7..654a2f1fe74 100644 --- a/src/devices/cpu/m6502/dm6502.lst +++ b/src/devices/cpu/m6502/dm6502.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # m6502_family_device - 6502, 6504 brk_imp ora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_imm nop_aba ora_aba asl_aba slo_aba bpl_rel ora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx diff --git a/src/devices/cpu/m6502/dm6509.lst b/src/devices/cpu/m6502/dm6509.lst index 644aa6c79d6..d8e498ecdf8 100644 --- a/src/devices/cpu/m6502/dm6509.lst +++ b/src/devices/cpu/m6502/dm6509.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # m6509 - special banking on two specific instructions, and banking in general brk_imp ora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_imm nop_aba ora_aba asl_aba slo_aba bpl_rel ora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx diff --git a/src/devices/cpu/m6502/dm6510.lst b/src/devices/cpu/m6502/dm6510.lst index dbc8bd88d57..18b78643795 100644 --- a/src/devices/cpu/m6502/dm6510.lst +++ b/src/devices/cpu/m6502/dm6510.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # m6510_family - identical to 6502, except for some undocumented instructions that have to be handled specifically brk_imp ora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_10_imm nop_aba ora_aba asl_aba slo_aba bpl_rel ora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx diff --git a/src/devices/cpu/m6502/dm65c02.lst b/src/devices/cpu/m6502/dm65c02.lst index 4b0cd1f2db4..a174a154041 100644 --- a/src/devices/cpu/m6502/dm65c02.lst +++ b/src/devices/cpu/m6502/dm65c02.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # m65c02 brk_c_imp ora_idx nop_imm nop_c_imp tsb_zpg ora_zpg asl_zpg nop_c_imp php_imp ora_imm asl_acc nop_c_imp tsb_aba ora_aba asl_aba nop_c_imp bpl_rel ora_idy ora_zpi nop_c_imp trb_zpg ora_zpx asl_zpx nop_c_imp clc_imp ora_aby inc_acc nop_c_imp trb_aba ora_abx asl_c_abx nop_c_imp diff --git a/src/devices/cpu/m6502/dm65ce02.lst b/src/devices/cpu/m6502/dm65ce02.lst index b2fafe67203..819ce35c614 100644 --- a/src/devices/cpu/m6502/dm65ce02.lst +++ b/src/devices/cpu/m6502/dm65ce02.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # m65ce02 - Adds the B and Z registers to the r65c02, a bunch of instructions, and changes most of the timings brk_ce_imp ora_ce_idx cle_imp see_imp tsb_ce_zpg ora_ce_zpg asl_ce_zpg rmb_ce_bzp php_ce_imp ora_imm asl_ce_acc tsy_imp tsb_ce_aba ora_aba asl_ce_aba bbr_ce_zpb bpl_ce_rel ora_ce_idy ora_idz bpl_rw2 trb_ce_zpg ora_ce_zpx asl_ce_zpx rmb_ce_bzp clc_ce_imp ora_ce_aby inc_ce_acc inz_imp trb_ce_aba ora_ce_abx asl_ce_abx bbr_ce_zpb diff --git a/src/devices/cpu/m6502/dm740.lst b/src/devices/cpu/m6502/dm740.lst index c11f0826cd5..04f67738dc9 100644 --- a/src/devices/cpu/m6502/dm740.lst +++ b/src/devices/cpu/m6502/dm740.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # m740 device brk740_imp ora_idx kil_non bbs_bar nop_zpg ora_zpg asl_zpg bbs_bzr php_imp ora_imm asl_acc seb_bac nop_aba ora_aba asl_aba seb_biz bpl_rel ora_idy clt_imp bbc_bar nop_zpx ora_zpx asl_zpx bbc_bzr clc_imp ora_aby dec_acc clb_bac nop_abx ora_abx asl_abx clb_biz diff --git a/src/devices/cpu/m6502/dn2a03.lst b/src/devices/cpu/m6502/dn2a03.lst index 7f0a5d4a9cb..06dcc2610a2 100644 --- a/src/devices/cpu/m6502/dn2a03.lst +++ b/src/devices/cpu/m6502/dn2a03.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # n2a03 - D flag is disabled but present in the P register brk_imp ora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_imm nop_aba ora_aba asl_aba slo_aba bpl_rel ora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx diff --git a/src/devices/cpu/m6502/dr65c02.lst b/src/devices/cpu/m6502/dr65c02.lst index fa4a97bda56..60573ac30d3 100644 --- a/src/devices/cpu/m6502/dr65c02.lst +++ b/src/devices/cpu/m6502/dr65c02.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # r65c02 - rockwell variant, with the bitwise instructions and stp/wai brk_c_imp ora_idx nop_imm nop_c_imp tsb_zpg ora_zpg asl_zpg rmb_bzp php_imp ora_imm asl_acc nop_c_imp tsb_aba ora_aba asl_aba bbr_zpb bpl_rel ora_idy ora_zpi nop_c_imp trb_zpg ora_zpx asl_zpx rmb_bzp clc_imp ora_aby inc_acc nop_c_imp trb_aba ora_abx asl_c_abx bbr_zpb diff --git a/src/devices/cpu/m6502/m6502make.py b/src/devices/cpu/m6502/m6502make.py index 4ac62e90ce9..8bcd85f8e21 100755 --- a/src/devices/cpu/m6502/m6502make.py +++ b/src/devices/cpu/m6502/m6502make.py @@ -1,4 +1,6 @@ #!/usr/bin/python +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert from __future__ import print_function diff --git a/src/devices/cpu/m6502/odeco16.lst b/src/devices/cpu/m6502/odeco16.lst index 6cea2fa7282..f3aade96499 100644 --- a/src/devices/cpu/m6502/odeco16.lst +++ b/src/devices/cpu/m6502/odeco16.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # deco 16 opcodes brk_16_imp // The 6502 bug when a nmi occurs in a brk is reproduced (case !irq_taken && nmi_state) diff --git a/src/devices/cpu/m6502/om4510.lst b/src/devices/cpu/m6502/om4510.lst index fbe49491fac..ade37a82db6 100644 --- a/src/devices/cpu/m6502/om4510.lst +++ b/src/devices/cpu/m6502/om4510.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # 4510 opcodes eom_imp diff --git a/src/devices/cpu/m6502/om6502.lst b/src/devices/cpu/m6502/om6502.lst index 24c560c02fa..93026a1fc8b 100644 --- a/src/devices/cpu/m6502/om6502.lst +++ b/src/devices/cpu/m6502/om6502.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # NMOS 6502 opcodes # Verified with visual6502 # documented opcodes diff --git a/src/devices/cpu/m6502/om6509.lst b/src/devices/cpu/m6502/om6509.lst index 4595827b1d7..8c9a6f9baa1 100644 --- a/src/devices/cpu/m6502/om6509.lst +++ b/src/devices/cpu/m6502/om6509.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # 6509 opcodes lda_9_idy diff --git a/src/devices/cpu/m6502/om6510.lst b/src/devices/cpu/m6502/om6510.lst index e08a5229111..1ad0dfc0182 100644 --- a/src/devices/cpu/m6502/om6510.lst +++ b/src/devices/cpu/m6502/om6510.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # 6510 undocumented instructions in a C64 context anc_10_imm TMP2 = read_pc(); diff --git a/src/devices/cpu/m6502/om65c02.lst b/src/devices/cpu/m6502/om65c02.lst index d64ddcdc409..c2536d2c11d 100644 --- a/src/devices/cpu/m6502/om65c02.lst +++ b/src/devices/cpu/m6502/om65c02.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # m65c02 opcodes adc_c_aba diff --git a/src/devices/cpu/m6502/om65ce02.lst b/src/devices/cpu/m6502/om65ce02.lst index 049097fded8..f5b6beebc9a 100644 --- a/src/devices/cpu/m6502/om65ce02.lst +++ b/src/devices/cpu/m6502/om65ce02.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # 65ce02 opcodes, a lot only remove dummy read/write cycles, some are new, some use the B register adc_ce_aba diff --git a/src/devices/cpu/m6502/om740.lst b/src/devices/cpu/m6502/om740.lst index 9f17dc639bf..f5ea32d49dc 100644 --- a/src/devices/cpu/m6502/om740.lst +++ b/src/devices/cpu/m6502/om740.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # m740 opcodes set_imp read_pc_noinc(); diff --git a/src/devices/cpu/m6502/on2a03.lst b/src/devices/cpu/m6502/on2a03.lst index 7d8a72c8d62..2719f7c6ad2 100644 --- a/src/devices/cpu/m6502/on2a03.lst +++ b/src/devices/cpu/m6502/on2a03.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert # n2a03 opcodes - same as 6502 but with d disabled adc_nd_aba TMP = read_pc(); diff --git a/src/devices/cpu/m6800/6800ops.inc b/src/devices/cpu/m6800/6800ops.inc index d6c3d7634a5..45a78d1d71f 100644 --- a/src/devices/cpu/m6800/6800ops.inc +++ b/src/devices/cpu/m6800/6800ops.inc @@ -1,4 +1,5 @@ - +// license:BSD-3-Clause +// copyright-holders:Aaron Giles /* HNZVC diff --git a/src/devices/cpu/m6800/6800tbl.inc b/src/devices/cpu/m6800/6800tbl.inc index 10515e54bdc..09c86bd8093 100644 --- a/src/devices/cpu/m6800/6800tbl.inc +++ b/src/devices/cpu/m6800/6800tbl.inc @@ -1,4 +1,5 @@ - +// license:BSD-3-Clause +// copyright-holders:Aaron Giles const m6800_cpu_device::op_func m6800_cpu_device::m6800_insn[0x100] = { &m6800_cpu_device::illegal,&m6800_cpu_device::nop, &m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::illegal,&m6800_cpu_device::tap, &m6800_cpu_device::tpa, &m6800_cpu_device::inx, &m6800_cpu_device::dex, &m6800_cpu_device::clv, &m6800_cpu_device::sev, &m6800_cpu_device::clc, &m6800_cpu_device::sec, &m6800_cpu_device::cli, &m6800_cpu_device::sei, diff --git a/src/devices/cpu/m68000/m68000.h b/src/devices/cpu/m68000/m68000.h index 013627ac6c0..6dc0c37489c 100644 --- a/src/devices/cpu/m68000/m68000.h +++ b/src/devices/cpu/m68000/m68000.h @@ -141,6 +141,9 @@ public: DECLARE_WRITE_LINE_MEMBER( write_irq6 ); DECLARE_WRITE_LINE_MEMBER( write_irq7 ); + void presave(); + void postload(); + void clear_all(void); virtual UINT32 disasm_min_opcode_bytes() const override { return 2; }; diff --git a/src/devices/cpu/m68000/m68kcpu.cpp b/src/devices/cpu/m68000/m68kcpu.cpp index 02809436472..8e8e7a3eadb 100644 --- a/src/devices/cpu/m68000/m68kcpu.cpp +++ b/src/devices/cpu/m68000/m68kcpu.cpp @@ -659,19 +659,19 @@ static void set_irq_line(m68000_base_device *m68k, int irqline, int state) m68k->nmi_pending = TRUE; } -static void m68k_presave(m68000_base_device *m68k) +void m68000_base_device::presave() { - m68k->save_sr = m68ki_get_sr(m68k); - m68k->save_stopped = (m68k->stopped & STOP_LEVEL_STOP) != 0; - m68k->save_halted = (m68k->stopped & STOP_LEVEL_HALT) != 0; + save_sr = m68ki_get_sr(this); + save_stopped = (stopped & STOP_LEVEL_STOP) != 0; + save_halted = (stopped & STOP_LEVEL_HALT) != 0; } -static void m68k_postload(m68000_base_device *m68k) +void m68000_base_device::postload() { - m68ki_set_sr_noint_nosp(m68k, m68k->save_sr); + m68ki_set_sr_noint_nosp(this, save_sr); //fprintf(stderr, "Reloaded, pc=%x\n", REG_PC(m68k)); - m68k->stopped = (m68k->save_stopped ? STOP_LEVEL_STOP : 0) | (m68k->save_halted ? STOP_LEVEL_HALT : 0); - m68ki_jump(m68k, REG_PC(m68k)); + stopped = (save_stopped ? STOP_LEVEL_STOP : 0) | (save_halted ? STOP_LEVEL_HALT : 0); + m68ki_jump(this, REG_PC(this)); } static void m68k_cause_bus_error(m68000_base_device *m68k) @@ -742,7 +742,6 @@ WRITE_LINE_MEMBER( m68000_base_device::write_irq7 ) bool m68000_base_device::memory_translate(address_spacenum space, int intention, offs_t &address) { /* only applies to the program address space and only does something if the MMU's enabled */ - if (this) { /* 68040 needs to call the MMU even when disabled so transparent translation works */ if ((space == AS_PROGRAM) && ((pmmu_enabled) || (CPU_TYPE_IS_040_PLUS(cpu_type)))) @@ -1025,8 +1024,8 @@ void m68000_base_device::init_cpu_common(void) save_item(NAME(mmu_atc_data[i]), i); } - machine().save().register_presave(save_prepost_delegate(FUNC(m68k_presave), this)); - machine().save().register_postload(save_prepost_delegate(FUNC(m68k_postload), this)); + machine().save().register_presave(save_prepost_delegate(FUNC(m68000_base_device::presave), this)); + machine().save().register_postload(save_prepost_delegate(FUNC(m68000_base_device::postload), this)); m_icountptr = &remaining_cycles; remaining_cycles = 0; @@ -2646,7 +2645,6 @@ void m68020pmmu_device::device_start() bool m68020hmmu_device::memory_translate(address_spacenum space, int intention, offs_t &address) { /* only applies to the program address space and only does something if the MMU's enabled */ - if (this) { if ((space == AS_PROGRAM) && (hmmu_enabled)) { diff --git a/src/devices/cpu/m6805/6805ops.inc b/src/devices/cpu/m6805/6805ops.inc index 713be5e0d7b..c6761982c96 100644 --- a/src/devices/cpu/m6805/6805ops.inc +++ b/src/devices/cpu/m6805/6805ops.inc @@ -1,4 +1,5 @@ - +// license:BSD-3-Clause +// copyright-holders:Aaron Giles /* HNZC diff --git a/src/devices/cpu/m6809/base6x09.ops b/src/devices/cpu/m6809/base6x09.ops index 334521eb385..54226cddfb9 100644 --- a/src/devices/cpu/m6809/base6x09.ops +++ b/src/devices/cpu/m6809/base6x09.ops @@ -1,3 +1,5 @@ +// license:BSD-3-Clause +// copyright-holders:Nathan Woods NMI: m_nmi_asserted = false; m_cc |= CC_E; diff --git a/src/devices/cpu/m6809/hd6309.ops b/src/devices/cpu/m6809/hd6309.ops index 6da3a904d2b..f96acfc695a 100644 --- a/src/devices/cpu/m6809/hd6309.ops +++ b/src/devices/cpu/m6809/hd6309.ops @@ -1,3 +1,5 @@ +// license:BSD-3-Clause +// copyright-holders:Nathan Woods MAIN: // check interrupt lines switch(get_pending_interrupt()) diff --git a/src/devices/cpu/m6809/konami.ops b/src/devices/cpu/m6809/konami.ops index e2246f85b71..fefa27aea26 100644 --- a/src/devices/cpu/m6809/konami.ops +++ b/src/devices/cpu/m6809/konami.ops @@ -1,3 +1,5 @@ +// license:BSD-3-Clause +// copyright-holders:Nathan Woods MAIN: // check interrupt lines switch(get_pending_interrupt()) diff --git a/src/devices/cpu/m6809/m6809.ops b/src/devices/cpu/m6809/m6809.ops index 96b9f6c11a7..5602211527a 100644 --- a/src/devices/cpu/m6809/m6809.ops +++ b/src/devices/cpu/m6809/m6809.ops @@ -1,3 +1,5 @@ +// license:BSD-3-Clause +// copyright-holders:Nathan Woods MAIN: // check interrupt lines switch(get_pending_interrupt()) diff --git a/src/devices/cpu/m6809/m6809make.py b/src/devices/cpu/m6809/m6809make.py index c3d5b0f66ee..8838b960191 100644 --- a/src/devices/cpu/m6809/m6809make.py +++ b/src/devices/cpu/m6809/m6809make.py @@ -1,4 +1,6 @@ #!/usr/bin/python +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert import sys import re diff --git a/src/devices/cpu/mcs51/mcs51ops.inc b/src/devices/cpu/mcs51/mcs51ops.inc index e60cc3505eb..0c1dec682ef 100644 --- a/src/devices/cpu/mcs51/mcs51ops.inc +++ b/src/devices/cpu/mcs51/mcs51ops.inc @@ -1,3 +1,5 @@ +// license:BSD-3-Clause +// copyright-holders:Steve Ellenoff /******************************************************************************************* NOTE: All registers are accessed directly, instead of using the SFR_R() function for speed Direct register access is availabe from the R_(register name) macros.. ex: ACC for the ACC diff --git a/src/devices/cpu/mcs96/mcs96make.py b/src/devices/cpu/mcs96/mcs96make.py index 72d8f36cfa6..b4844942e3d 100644 --- a/src/devices/cpu/mcs96/mcs96make.py +++ b/src/devices/cpu/mcs96/mcs96make.py @@ -1,4 +1,6 @@ #!/usr/bin/python +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert from __future__ import print_function diff --git a/src/devices/cpu/mcs96/mcs96ops.lst b/src/devices/cpu/mcs96/mcs96ops.lst index 7ccedf358da..372acb44218 100644 --- a/src/devices/cpu/mcs96/mcs96ops.lst +++ b/src/devices/cpu/mcs96/mcs96ops.lst @@ -1,3 +1,5 @@ +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert fetch if(irq_requested) { int level; diff --git a/src/devices/cpu/powerpc/ppcdrc.cpp b/src/devices/cpu/powerpc/ppcdrc.cpp index 35b984d240d..7390f9284e9 100644 --- a/src/devices/cpu/powerpc/ppcdrc.cpp +++ b/src/devices/cpu/powerpc/ppcdrc.cpp @@ -3472,7 +3472,13 @@ int ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *com case 0x12: /* FDIVSx */ if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(block, compiler, desc); - UML_FDDIV(block, F0, F64(G_RA(op)), F64(G_RB(op))); // fddiv f0,ra,rb + UML_FDCMP(block, F64(G_RB(op)), mem(&m_core->fp0)); // fdcmp rb,0 + UML_JMPc(block, COND_Z, compiler->labelnum); // bz 1: + UML_FDDIV(block, F0, F64(G_RA(op)), F64(G_RB(op))); // fddiv f0,ra,rb + UML_JMP(block, compiler->labelnum+1); // bz 2: + UML_LABEL(block, compiler->labelnum++); // 1: + UML_FDMOV(block, F0, mem(&m_core->fp0)); // fdmov f0,0 + UML_LABEL(block, compiler->labelnum++); // 2: UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 generate_fp_flags(block, desc, TRUE); return TRUE; @@ -3566,7 +3572,13 @@ int ppc_device::generate_instruction_3f(drcuml_block *block, compiler_state *com return TRUE; case 0x12: /* FDIVx */ + UML_FDCMP(block, F64(G_RB(op)), mem(&m_core->fp0)); // fdcmp rb,0 + UML_JMPc(block, COND_Z, compiler->labelnum); // bz 1: UML_FDDIV(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fddiv rd,ra,rb + UML_JMP(block, compiler->labelnum+1); // bz 2: + UML_LABEL(block, compiler->labelnum++); // 1: + UML_FDMOV(block, F64(G_RD(op)), mem(&m_core->fp0)); // fdmov rd,0 + UML_LABEL(block, compiler->labelnum++); // 2: generate_fp_flags(block, desc, TRUE); return TRUE; diff --git a/src/devices/cpu/sh4/sh4dmac.h b/src/devices/cpu/sh4/sh4dmac.h index 60148653c2b..fe0bbc84514 100644 --- a/src/devices/cpu/sh4/sh4dmac.h +++ b/src/devices/cpu/sh4/sh4dmac.h @@ -27,8 +27,6 @@ #define DMAOR_NMIF 0x0002 #define DMAOR_DME 0x0001 -TIMER_CALLBACK( sh4_dmac_callback ); - void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask); void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask); void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask); diff --git a/src/devices/cpu/tms0980/tms0980.cpp b/src/devices/cpu/tms0980/tms0980.cpp index e067946bb7a..3ea3ca918b1 100644 --- a/src/devices/cpu/tms0980/tms0980.cpp +++ b/src/devices/cpu/tms0980/tms0980.cpp @@ -203,7 +203,8 @@ const device_type TMS0270 = &device_creator<tms0270_cpu_device>; // 40-pin DIP, // TMS0260 is same or similar? // TP0320 is TI's first CMOS MCU with integrated LCD controller, the die is still very similar to TMS0980 -// - x +// - ROM and main RAM is same as on TMS0980 with different row-select +// - const device_type TP0320 = &device_creator<tp0320_cpu_device>; // 28-pin SDIP, .. diff --git a/src/devices/cpu/tms0980/tms0980d.cpp b/src/devices/cpu/tms0980/tms0980d.cpp index ea72ba9be2e..371047b0a79 100644 --- a/src/devices/cpu/tms0980/tms0980d.cpp +++ b/src/devices/cpu/tms0980/tms0980d.cpp @@ -11,7 +11,8 @@ #include "tms0980.h" -enum e_mnemonics { +enum e_mnemonics +{ zA10AAC=0, zA6AAC, zA8AAC, zAC1AC, zACACC, zACNAA, zALEC, zALEM, zAMAAC, zBRANCH, zCALL, zCCLA, zCLA, zCLO, zCOMC, zCOMX, zCOMX8, zCPAIZ, zCTMDYN, zDAN, zDMAN, zDMEA, zDNAA, zDYN, zIA, zIMAC, zIYC, zKNEZ, zLDP, zLDX, zLDX3, zLDX4, zMNEA, zMNEZ, @@ -22,7 +23,8 @@ enum e_mnemonics { zILL }; -static const char *const s_mnemonic[] = { +static const char *const s_mnemonic[] = +{ "A10AAC", "A6AAC", "A8AAC", "AC1AC", "ACACC", "ACNAA", "ALEC", "ALEM", "AMAAC", "BRANCH", "CALL", "CCLA", "CLA", "CLO", "COMC", "COMX", "COMX8", "CPAIZ", "CTMDYN", "DAN", "DMAN", "DMEA", "DNAA", "DYN", "IA", "IMAC", "IYC", "KNEZ", "LDP", "LDX", "LDX", "LDX", "MNEA", "MNEZ", @@ -37,7 +39,8 @@ static const char *const s_mnemonic[] = { #define _OVER DASMFLAG_STEP_OVER #define _OUT DASMFLAG_STEP_OUT -static const UINT32 s_flags[] = { +static const UINT32 s_flags[] = +{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, _OVER, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -49,11 +52,13 @@ static const UINT32 s_flags[] = { }; -enum e_addressing { +enum e_addressing +{ zB0=0, zI2, zI3, zI4, zB7 }; -static const UINT8 s_addressing[] = { +static const UINT8 s_addressing[] = +{ zB0, zB0, zB0, zI4, zI4, zI4, zI4, zB0, zB0, zB7, zB7, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zB0, zI4, zI2, zI3, zI4, zB0, zB0, @@ -65,7 +70,25 @@ static const UINT8 s_addressing[] = { }; -static const UINT8 tms0980_mnemonic[512] = { +static const UINT8 tms0980_i2_value[4] = +{ + 0, 2, 1, 3 +}; +static const UINT8 tms0980_i3_value[8] = +{ + 0, 4, 2, 6, 1, 5, 3, 7 +}; +static const UINT8 tms0980_i4_value[16] = +{ + 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf +}; + + + +// opcode luts + +static const UINT8 tms0980_mnemonic[512] = +{ /* 0x000 */ zCOMX, zALEM, zYNEA, zXMA, zDYN, zIYC, zCLA, zDMAN, zTKA, zMNEA, zTKM, zILL, zILL, zSETR, zKNEZ, zILL, @@ -151,7 +174,8 @@ static const UINT8 tms0980_mnemonic[512] = { }; -static const UINT8 tms1000_mnemonic[256] = { +static const UINT8 tms1000_mnemonic[256] = +{ /* 0x00 */ zCOMX, zA8AAC, zYNEA, zTAM, zTAMZA, zA10AAC, zA6AAC, zDAN, zTKA, zKNEZ, zTDO, zCLO, zRSTR, zSETR, zIA, zRETN, @@ -191,7 +215,8 @@ static const UINT8 tms1000_mnemonic[256] = { }; -static const UINT8 tms1100_mnemonic[256] = { +static const UINT8 tms1100_mnemonic[256] = +{ /* 0x00 */ zMNEA, zALEM, zYNEA, zXMA, zDYN, zIYC, zAMAAC, zDMAN, zTKA, zCOMX, zTDO, zCOMC, zRSTR, zSETR, zKNEZ, zRETN, @@ -233,21 +258,11 @@ static const UINT8 tms1100_mnemonic[256] = { }; -static const UINT8 tms0980_i2_value[4] = -{ - 0x00, 0x02, 0x01, 0x03 -}; -static const UINT8 tms0980_i3_value[8] = -{ - 0x00, 0x04, 0x02, 0x06, 0x01, 0x05, 0x03, 0x07 -}; -static const UINT8 tms0980_i4_value[16] = -{ - 0x00, 0x08, 0x04, 0x0C, 0x02, 0x0A, 0x06, 0x0E, 0x01, 0x09, 0x05, 0x0D, 0x03, 0x0B, 0x07, 0x0F -}; +// disasm -CPU_DISASSEMBLE( tms0980 ) { +CPU_DISASSEMBLE( tms0980 ) +{ char *dst = buffer; UINT16 op, instr; int pos = 0; @@ -259,7 +274,8 @@ CPU_DISASSEMBLE( tms0980 ) { dst += sprintf( dst, "%-8s ", s_mnemonic[instr] ); - switch( s_addressing[instr] ) { + switch( s_addressing[instr] ) + { default: case zB0: break; @@ -278,7 +294,8 @@ CPU_DISASSEMBLE( tms0980 ) { } -CPU_DISASSEMBLE( tms1000 ) { +CPU_DISASSEMBLE( tms1000 ) +{ char *dst = buffer; UINT8 op, instr; int pos = 0; @@ -290,7 +307,8 @@ CPU_DISASSEMBLE( tms1000 ) { dst += sprintf( dst, "%-8s ", s_mnemonic[instr] ); - switch( s_addressing[instr] ) { + switch( s_addressing[instr] ) + { default: case zB0: break; @@ -309,7 +327,8 @@ CPU_DISASSEMBLE( tms1000 ) { } -CPU_DISASSEMBLE( tms1100 ) { +CPU_DISASSEMBLE( tms1100 ) +{ char *dst = buffer; UINT8 op, instr; int pos = 0; @@ -321,7 +340,8 @@ CPU_DISASSEMBLE( tms1100 ) { dst += sprintf( dst, "%-8s ", s_mnemonic[instr] ); - switch( s_addressing[instr] ) { + switch( s_addressing[instr] ) + { default: case zB0: break; diff --git a/src/devices/cpu/tms57002/tmsmake.py b/src/devices/cpu/tms57002/tmsmake.py index df37f261dc1..e2e12b5a4b3 100755 --- a/src/devices/cpu/tms57002/tmsmake.py +++ b/src/devices/cpu/tms57002/tmsmake.py @@ -1,4 +1,6 @@ #!/usr/bin/python +# license:BSD-3-Clause +# copyright-holders:Olivier Galibert from __future__ import print_function |