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-rw-r--r--src/devices/cpu/z180/z180.cpp344
1 files changed, 102 insertions, 242 deletions
diff --git a/src/devices/cpu/z180/z180.cpp b/src/devices/cpu/z180/z180.cpp
index 18ded716eb7..3097427bd69 100644
--- a/src/devices/cpu/z180/z180.cpp
+++ b/src/devices/cpu/z180/z180.cpp
@@ -15,6 +15,32 @@
work. Currently, only timers are implemented. Ideally, the
burn_cycles routine would go away and halt processing be
implemented in cpu_execute.
+
+ - Documentation for RXS/CTS1 pin is contradictory.
+
+ From page 12:
+ "During RESET, this pin is initialized as RXS pin. If CTS1E
+ bit in ASCI status register ch1 (STAT1) is set to 1, CTS1
+ function is selected. If CTS1E bit is set to 0, RXS function
+ is selected."
+
+ However, there is no CTS1E bit in the ASCI status register.
+
+ From pages 43-44:
+ "CTS/PS: Clear to Send/Prescale (bit 5)—If bit 5 of the System
+ Configuration Register is 0, the CTS0/RxS pin features the
+ CTS0 function, and the state of the pin can be read in bit 5
+ of CNTLB0 in a real-time, positive-logic fashion (HIGH = 1 ,
+ LOW = 0). If bit 5 in the System Configuration Register is 0
+ to auto-enable CTS0, and the pin is negated (High), the TDRE
+ bit is inhibited (forced to 0). Bit 5 of CNTLB1 reads back as
+ 0."
+
+ This contradicts everything else in the documentation as it
+ implies RXS shares a pin with CTS0 (rather than CTS1)
+
+ For now, the input is always sent to both RXS and CTS1.
+
*****************************************************************************/
/*****************************************************************************
@@ -57,7 +83,6 @@ Hitachi HD647180 series:
#include "emu.h"
#include "z180.h"
#include "z180dasm.h"
-#include "debugger.h"
//#define VERBOSE 1
#include "logmacro.h"
@@ -94,15 +119,13 @@ z180_device::z180_device(const machine_config &mconfig, device_type type, const
, m_program_config("program", ENDIANNESS_LITTLE, 8, 20, 0, 16, 12, internal_map)
, m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0)
, m_decrypted_opcodes_config("opcodes", ENDIANNESS_LITTLE, 8, 20, 0, 16, 12, internal_map)
+ , m_asci(*this, "asci_%u", 0U)
+ , m_csio(*this, "csio")
, m_extended_io(extended_io)
+ , m_tend0_cb(*this)
+ , m_tend1_cb(*this)
{
// some arbitrary initial values
- m_asci_cntla[0] = m_asci_cntla[1] = 0;
- m_asci_cntlb[0] = m_asci_cntlb[1] = 0;
- m_asci_stat[0] = 0;
- m_asci_tdr[0] = m_asci_tdr[1] = 0;
- m_asci_rdr[0] = m_asci_rdr[1] = 0;
- m_csio_trdr = 0;
m_tmdr[0].w = m_tmdr[1].w = 0;
m_rldr[0].w = m_rldr[1].w = 0xffff;
m_dma_sar0.d = 0;
@@ -132,8 +155,6 @@ hd64180rp_device::hd64180rp_device(const machine_config &mconfig, const char *ta
z8s180_device::z8s180_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: z180_device(mconfig, type, tag, owner, clock, false, address_map_constructor())
{
- // some arbitrary initial values
- m_asci_tc[0].w = m_asci_tc[1].w = 0;
}
z8s180_device::z8s180_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
@@ -235,69 +256,6 @@ bool z180_device::get_tend1()
#define _LY m_IY.b.l
-/* 00 ASCI control register A ch 0 */
-#define Z180_CNTLA0_MPE 0x80
-#define Z180_CNTLA0_RE 0x40
-#define Z180_CNTLA0_TE 0x20
-#define Z180_CNTLA0_RTS0 0x10
-#define Z180_CNTLA0_MPBR_EFR 0x08
-#define Z180_CNTLA0_MODE_DATA 0x04
-#define Z180_CNTLA0_MODE_PARITY 0x02
-#define Z180_CNTLA0_MODE_STOPB 0x01
-
-/* 01 ASCI control register A ch 1 */
-#define Z180_CNTLA1_MPE 0x80
-#define Z180_CNTLA1_RE 0x40
-#define Z180_CNTLA1_TE 0x20
-#define Z180_CNTLA1_CKA1D 0x10
-#define Z180_CNTLA1_MPBR_EFR 0x08
-#define Z180_CNTLA1_MODE 0x07
-
-/* 02 ASCI control register B ch 0 */
-#define Z180_CNTLB0_MPBT 0x80
-#define Z180_CNTLB0_MP 0x40
-#define Z180_CNTLB0_CTS_PS 0x20
-#define Z180_CNTLB0_PEO 0x10
-#define Z180_CNTLB0_DR 0x08
-#define Z180_CNTLB0_SS 0x07
-
-/* 03 ASCI control register B ch 1 */
-#define Z180_CNTLB1_MPBT 0x80
-#define Z180_CNTLB1_MP 0x40
-#define Z180_CNTLB1_CTS_PS 0x20
-#define Z180_CNTLB1_PEO 0x10
-#define Z180_CNTLB1_DR 0x08
-#define Z180_CNTLB1_SS 0x07
-
-/* 04 ASCI status register 0 (all bits read-only except RIE and TIE) */
-#define Z180_STAT0_RDRF 0x80
-#define Z180_STAT0_OVRN 0x40
-#define Z180_STAT0_PE 0x20
-#define Z180_STAT0_FE 0x10
-#define Z180_STAT0_RIE 0x08
-#define Z180_STAT0_DCD0 0x04
-#define Z180_STAT0_TDRE 0x02
-#define Z180_STAT0_TIE 0x01
-
-/* 05 ASCI status register 1 (all bits read-only except RIE, CTS1E and TIE) */
-#define Z180_STAT1_RDRF 0x80
-#define Z180_STAT1_OVRN 0x40
-#define Z180_STAT1_PE 0x20
-#define Z180_STAT1_FE 0x10
-#define Z180_STAT1_RIE 0x08
-#define Z180_STAT1_CTS1E 0x04
-#define Z180_STAT1_TDRE 0x02
-#define Z180_STAT1_TIE 0x01
-
-/* 0a CSI/O control/status register (EF is read-only) */
-#define Z180_CNTR_EF 0x80
-#define Z180_CNTR_EIE 0x40
-#define Z180_CNTR_RE 0x20
-#define Z180_CNTR_TE 0x10
-#define Z180_CNTR_SS 0x07
-
-#define Z180_CNTR_MASK 0xf7
-
/* 10 TIMER control register (TIF1 and TIF0 are read-only) */
#define Z180_TCR_TIF1 0x80
#define Z180_TCR_TIF0 0x40
@@ -308,26 +266,6 @@ bool z180_device::get_tend1()
#define Z180_TCR_TDE1 0x02
#define Z180_TCR_TDE0 0x01
-/* 12 (Z8S180/Z8L180) ASCI extension control register 0 (break detect is read-only) */
-#define Z180_ASEXT0_DCD0 0x40
-#define Z180_ASEXT0_CTS0 0x20
-#define Z180_ASEXT0_X1_BIT_CLK0 0x10
-#define Z180_ASEXT0_BRG0_MODE 0x08
-#define Z180_ASEXT0_BRK_EN 0x04
-#define Z180_ASEXT0_BRK_DET 0x02
-#define Z180_ASEXT0_BRK_SEND 0x01
-
-#define Z180_ASEXT0_MASK 0x7f
-
-/* 13 (Z8S180/Z8L180) ASCI extension control register 1 (break detect is read-only) */
-#define Z180_ASEXT1_X1_BIT_CLK1 0x10
-#define Z180_ASEXT1_BRG1_MODE 0x08
-#define Z180_ASEXT1_BRK_EN 0x04
-#define Z180_ASEXT1_BRK_DET 0x02
-#define Z180_ASEXT1_BRK_SEND 0x01
-
-#define Z180_ASEXT1_MASK 0x1f
-
/* 1e (Z8S180/Z8L180) clock multiplier */
#define Z180_CMR_X2 0x80
#define Z180_CMR_LOW_NOISE 0x40
@@ -498,64 +436,36 @@ uint8_t z180_device::z180_internal_port_read(uint8_t port)
switch (port)
{
case 0x00:
- data = m_asci_cntla[0];
- LOG("Z180 CNTLA0 rd $%02x\n", data);
- break;
-
case 0x01:
- data = m_asci_cntla[1];
- LOG("Z180 CNTLA1 rd $%02x\n", data);
+ data = m_asci[port & 1]->cntla_r();
break;
case 0x02:
- data = m_asci_cntlb[0];
- LOG("Z180 CNTLB0 rd $%02x\n", data);
- break;
-
case 0x03:
- data = m_asci_cntlb[1];
- LOG("Z180 CNTLB1 rd $%02x\n", data);
+ data = m_asci[port & 1]->cntlb_r();
break;
case 0x04:
- data = m_asci_stat[0];
- data |= 0x02; // kludge for 20pacgal
- LOG("Z180 STAT0 rd $%02x\n", data);
- break;
-
case 0x05:
- data = m_asci_stat[1];
- LOG("Z180 STAT1 rd $%02x\n", data);
+ data = m_asci[port & 1]->stat_r();
break;
case 0x06:
- data = m_asci_tdr[0];
- LOG("Z180 TDR0 rd $%02x\n", data);
- break;
-
case 0x07:
- data = m_asci_tdr[1];
- LOG("Z180 TDR1 rd $%02x\n", data);
+ data = m_asci[port & 1]->tdr_r();
break;
case 0x08:
- data = m_asci_rdr[0];
- LOG("Z180 RDR0 rd $%02x\n", data);
- break;
-
case 0x09:
- data = m_asci_rdr[1];
- LOG("Z180 RDR1 rd $%02x\n", data);
+ data = m_asci[port & 1]->rdr_r();
break;
case 0x0a:
- data = m_csio_cntr | ~Z180_CNTR_MASK;
- LOG("Z180 CNTR rd $%02x ($%02x)\n", data, m_csio_cntr);
+ data = m_csio->cntr_r();
break;
case 0x0b:
- data = m_csio_trdr;
- LOG("Z180 TRDR rd $%02x\n", data);
+ data = m_csio->trdr_r();
break;
case 0x0c:
@@ -862,64 +772,36 @@ void z180_device::z180_internal_port_write(uint8_t port, uint8_t data)
switch (port)
{
case 0x00:
- LOG("Z180 CNTLA0 wr $%02x\n", data);
- m_asci_cntla[0] = data;
- break;
-
case 0x01:
- LOG("Z180 CNTLA1 wr $%02x\n", data);
- m_asci_cntla[1] = data;
+ m_asci[port & 1]->cntla_w(data);
break;
case 0x02:
- LOG("Z180 CNTLB0 wr $%02x\n", data);
- m_asci_cntlb[0] = data;
- break;
-
case 0x03:
- LOG("Z180 CNTLB1 wr $%02x\n", data);
- m_asci_cntlb[1] = data;
+ m_asci[port & 1]->cntlb_w(data);
break;
case 0x04:
- LOG("Z180 STAT0 wr $%02x ($%02x)\n", data, data & (Z180_STAT0_RIE | Z180_STAT0_TIE));
- m_asci_stat[0] = (m_asci_stat[0] & ~(Z180_STAT0_RIE | Z180_STAT0_TIE)) | (data & (Z180_STAT0_RIE | Z180_STAT0_TIE));
- break;
-
case 0x05:
- LOG("Z180 STAT1 wr $%02x ($%02x)\n", data, data & (Z180_STAT1_RIE | Z180_STAT1_CTS1E | Z180_STAT1_TIE));
- m_asci_stat[1] = (m_asci_stat[1] & ~(Z180_STAT1_RIE | Z180_STAT1_CTS1E | Z180_STAT1_TIE)) | (data & (Z180_STAT1_RIE | Z180_STAT1_CTS1E | Z180_STAT1_TIE));
+ m_asci[port & 1]->stat_w(data);
break;
case 0x06:
- LOG("Z180 TDR0 wr $%02x\n", data);
- m_asci_tdr[0] = data;
- break;
-
case 0x07:
- LOG("Z180 TDR1 wr $%02x\n", data);
- m_asci_tdr[1] = data;
+ m_asci[port & 1]->tdr_w(data);
break;
case 0x08:
- LOG("Z180 RDR0 wr $%02x\n", data);
- m_asci_rdr[0] = data;
- break;
-
case 0x09:
- LOG("Z180 RDR1 wr $%02x\n", data);
- m_asci_rdr[1] = data;
+ m_asci[port & 1]->rdr_w(data);
break;
case 0x0a:
- // Inhibit setting up TE & RE flags due to the lack of CSIO implementation
- LOG("Z180 CNTR wr $%02x ($%02x)\n", data, data & ~(Z180_CNTR_EF | Z180_CNTR_RE | Z180_CNTR_TE));
- m_csio_cntr = (m_csio_cntr & (Z180_CNTR_EF | Z180_CNTR_RE | Z180_CNTR_TE)) | (data & ~(Z180_CNTR_EF | Z180_CNTR_RE | Z180_CNTR_TE));
+ m_csio->cntr_w(data);
break;
case 0x0b:
- LOG("Z180 TRDR wr $%02x\n", data);
- m_csio_trdr = data;
+ m_csio->trdr_w(data);
break;
case 0x0c:
@@ -1145,33 +1027,18 @@ uint8_t z8s180_device::z180_internal_port_read(uint8_t port)
switch (port)
{
case 0x12:
- data = m_asci_ext[0];
- LOG("Z180 ASEXT0 rd $%02x ($%02x)\n", data, m_asci_ext[0]);
- break;
-
case 0x13:
- data = m_asci_ext[1];
- LOG("Z180 ASEXT1 rd $%02x ($%02x)\n", data, m_asci_ext[1]);
+ data = m_asci[port & 1]->asext_r();
break;
case 0x1a:
- LOG("Z180 ASTC0L wr $%02x\n", data);
- m_asci_tc[0].b.l = data;
- break;
-
case 0x1b:
- LOG("Z180 ASTC0H wr $%02x\n", data);
- m_asci_tc[0].b.h = data;
+ data = m_asci[port & 1]->astcl_r();
break;
case 0x1c:
- LOG("Z180 ASTC1L wr $%02x\n", data);
- m_asci_tc[1].b.l = data;
- break;
-
case 0x1d:
- LOG("Z180 ASTC1H wr $%02x\n", data);
- m_asci_tc[1].b.h = data;
+ data = m_asci[port & 1]->astcl_r();
break;
case 0x1e:
@@ -1197,33 +1064,18 @@ void z8s180_device::z180_internal_port_write(uint8_t port, uint8_t data)
switch (port)
{
case 0x12:
- LOG("Z180 ASEXT0 wr $%02x ($%02x)\n", data, data & Z180_ASEXT0_MASK & ~Z180_ASEXT0_BRK_DET);
- m_asci_ext[0] = (m_asci_ext[0] & Z180_ASEXT0_BRK_DET) | (data & Z180_ASEXT0_MASK & ~Z180_ASEXT0_BRK_DET);
- break;
-
case 0x13:
- LOG("Z180 ASEXT1 wr $%02x ($%02x)\n", data, data & Z180_ASEXT1_MASK & ~Z180_ASEXT1_BRK_DET);
- m_asci_ext[1] = (m_asci_ext[1] & Z180_ASEXT1_BRK_DET) | (data & Z180_ASEXT1_MASK & ~Z180_ASEXT1_BRK_DET);
+ m_asci[port & 1]->asext_w(data);
break;
case 0x1a:
- data = m_asci_tc[0].b.l;
- LOG("Z180 ASTC0L rd $%02x ($%04x)\n", data, m_asci_tc[0].w);
- break;
-
case 0x1b:
- data = m_asci_tc[0].b.h;
- LOG("Z180 ASTC0H rd $%02x ($%04x)\n", data, m_asci_tc[0].w);
+ m_asci[port & 1]->astcl_w(data);
break;
case 0x1c:
- data = m_asci_tc[1].b.l;
- LOG("Z180 ASTC1L rd $%02x ($%04x)\n", data, m_asci_tc[1].w);
- break;
-
case 0x1d:
- data = m_asci_tc[1].b.h;
- LOG("Z180 ASTC1H rd $%02x ($%04x)\n", data, m_asci_tc[1].w);
+ m_asci[port & 1]->astch_w(data);
break;
case 0x1e:
@@ -1270,6 +1122,7 @@ int z180_device::z180_dma0(int max_cycles)
if (bcr0 == 1)
{
m_iol |= Z180_TEND0;
+ m_tend0_cb(ASSERT_LINE);
}
switch( m_dmode & (Z180_DMODE_SM | Z180_DMODE_DM) )
{
@@ -1392,6 +1245,7 @@ int z180_device::z180_dma0(int max_cycles)
if (bcr0 == 0)
{
m_iol &= ~Z180_TEND0;
+ m_tend0_cb(CLEAR_LINE);
m_dstat &= ~Z180_DSTAT_DE0;
/* terminal count interrupt enabled? */
if (m_dstat & Z180_DSTAT_DIE0 && m_IFF1)
@@ -1425,6 +1279,7 @@ int z180_device::z180_dma1()
if (bcr1 == 1)
{
m_iol |= Z180_TEND1;
+ m_tend1_cb(ASSERT_LINE);
}
m_extra_cycles = 0;
@@ -1433,15 +1288,19 @@ int z180_device::z180_dma1()
{
case 0x00: /* memory MAR1+1 to I/O IAR1 fixed */
m_io.write_byte(iar1, z180_read_memory(mar1++));
+ bcr1--;
break;
case 0x01: /* memory MAR1-1 to I/O IAR1 fixed */
m_io.write_byte(iar1, z180_read_memory(mar1--));
+ bcr1--;
break;
case 0x02: /* I/O IAR1 fixed to memory MAR1+1 */
z180_write_memory(mar1++, m_io.read_byte(iar1));
+ bcr1--;
break;
case 0x03: /* I/O IAR1 fixed to memory MAR1-1 */
z180_write_memory(mar1--, m_io.read_byte(iar1));
+ bcr1--;
break;
}
@@ -1459,6 +1318,7 @@ int z180_device::z180_dma1()
if (bcr1 == 0)
{
m_iol &= ~Z180_TEND1;
+ m_tend1_cb(CLEAR_LINE);
m_dstat &= ~Z180_DSTAT_DE1;
if (m_dstat & Z180_DSTAT_DIE1 && m_IFF1)
m_int_pending[Z180_INT_DMA1] = 1;
@@ -1710,20 +1570,9 @@ void z180_device::device_start()
state_add(Z180_IOLINES, "IOLINES", m_ioltemp).mask(0xffffff).callimport();
- state_add(Z180_CNTLA0, "CNTLA0", m_asci_cntla[0]);
- state_add(Z180_CNTLB0, "CNTLB0", m_asci_cntlb[0]);
- state_add(Z180_STAT0, "STAT0", m_asci_stat[0]);
- state_add(Z180_TDR0, "TDR0", m_asci_tdr[0]);
- state_add(Z180_RDR0, "RDR0", m_asci_rdr[0]);
-
- state_add(Z180_CNTLA1, "CNTLA1", m_asci_cntla[1]);
- state_add(Z180_CNTLB1, "CNTLB1", m_asci_cntlb[1]);
- state_add(Z180_STAT1, "STAT1", m_asci_stat[1]);
- state_add(Z180_TDR1, "TDR1", m_asci_tdr[1]);
- state_add(Z180_RDR1, "RDR1", m_asci_rdr[1]);
-
- state_add(Z180_CNTR, "CNTR", m_csio_cntr).mask(Z180_CNTR_MASK);
- state_add(Z180_TRDR, "TRDR", m_csio_trdr);
+ m_asci[0]->state_add(*this);
+ m_asci[1]->state_add(*this);
+ m_csio->state_add(*this);
state_add(Z180_TMDR0, "TMDR0", m_tmdr_value[0]);
state_add(Z180_RLDR0, "RLDR0", m_rldr[0].w);
@@ -1783,13 +1632,6 @@ void z180_device::device_start()
save_item(NAME(m_tmdrh));
save_item(NAME(m_tmdr_latch));
- save_item(NAME(m_asci_cntla));
- save_item(NAME(m_asci_cntlb));
- save_item(NAME(m_asci_stat));
- save_item(NAME(m_asci_tdr));
- save_item(NAME(m_asci_rdr));
- save_item(NAME(m_csio_cntr));
- save_item(NAME(m_csio_trdr));
save_item(NAME(m_tmdr[0].w));
save_item(NAME(m_tmdr[1].w));
save_item(NAME(m_rldr[0].w));
@@ -1826,18 +1668,9 @@ void z8s180_device::device_start()
{
z180_device::device_start();
- state_add(Z180_ASEXT0, "ASEXT0", m_asci_ext[0]).mask(Z180_ASEXT0_MASK);
- state_add(Z180_ASTC0, "ASTC0", m_asci_tc[0].w);
-
- state_add(Z180_ASEXT1, "ASEXT1", m_asci_ext[1]).mask(Z180_ASEXT1_MASK);
- state_add(Z180_ASTC1, "ASTC1", m_asci_tc[1].w);
-
state_add(Z180_CMR, "CMR", m_cmr).mask(Z180_CMR_MASK);
state_add(Z180_CCR, "CCR", m_ccr);
- save_item(NAME(m_asci_ext));
- save_item(NAME(m_asci_tc[0].w));
- save_item(NAME(m_asci_tc[1].w));
save_item(NAME(m_cmr));
save_item(NAME(m_ccr));
}
@@ -1897,13 +1730,6 @@ void z180_device::device_reset()
m_frc_prescale = 0;
/* reset io registers */
- m_asci_cntla[0] = (m_asci_cntla[0] & Z180_CNTLA0_MPBR_EFR) | Z180_CNTLA0_RTS0;
- m_asci_cntla[1] = (m_asci_cntla[1] & Z180_CNTLA1_MPBR_EFR) | Z180_CNTLA1_CKA1D;
- m_asci_cntlb[0] = (m_asci_cntlb[0] & (Z180_CNTLB0_MPBT | Z180_CNTLB0_CTS_PS)) | 0x07;
- m_asci_cntlb[1] = (m_asci_cntlb[1] & Z180_CNTLB1_MPBT) | 0x07;
- m_asci_stat[0] = m_asci_stat[0] & (Z180_STAT0_DCD0 | Z180_STAT0_TDRE);
- m_asci_stat[1] = Z180_STAT1_TDRE;
- m_csio_cntr = 0x07;
m_tcr = 0x00;
m_dma_iar1.b.h2 = 0x00;
m_dstat = Z180_DSTAT_DWE1 | Z180_DSTAT_DWE0;
@@ -1921,17 +1747,41 @@ void z180_device::device_reset()
z180_mmu();
}
+void z180_device::device_add_mconfig(machine_config &config)
+{
+ Z180ASCI_CHANNEL_0(config, m_asci[0], DERIVED_CLOCK(1,2));
+
+ Z180ASCI_CHANNEL_1(config, m_asci[1], DERIVED_CLOCK(1,2));
+
+ Z180CSIO(config, m_csio, DERIVED_CLOCK(1,2));
+}
+
+void z8s180_device::device_add_mconfig(machine_config &config)
+{
+ Z180ASCI_EXT_CHANNEL_0(config, m_asci[0], DERIVED_CLOCK(1,2));
+
+ Z180ASCI_EXT_CHANNEL_1(config, m_asci[1], DERIVED_CLOCK(1,2));
+
+ Z180CSIO(config, m_csio, DERIVED_CLOCK(1,2));
+}
+
void z8s180_device::device_reset()
{
z180_device::device_reset();
- m_asci_ext[0] = 0x00;
- m_asci_ext[1] = 0x00;
m_cmr = 0x00;
m_ccr = 0x00;
notify_clock_changed();
}
+void z8s180_device::device_clock_changed()
+{
+ auto const rate = (m_cmr & 0x80) ? DERIVED_CLOCK(2,1) : (m_ccr & 0x80) ? DERIVED_CLOCK(1,1) : DERIVED_CLOCK(1,2);
+ m_asci[0]->set_clock(rate);
+ m_asci[1]->set_clock(rate);
+ m_csio->set_clock(rate);
+}
+
/* Handle PRT timers, decreasing them after 20 clocks and returning the new icount base that needs to be used for the next check */
void z180_device::clock_timers()
{
@@ -1976,9 +1826,6 @@ void z180_device::clock_timers()
int z180_device::check_interrupts()
{
- int i;
- int cycles = 0;
-
/* check for IRQs before each instruction */
if (m_IFF1 && !m_after_EI)
{
@@ -1990,15 +1837,27 @@ int z180_device::check_interrupts()
if (m_irq_state[2] != CLEAR_LINE && (m_itc & Z180_ITC_ITE2) == Z180_ITC_ITE2)
m_int_pending[Z180_INT_IRQ2] = 1;
+
+ m_int_pending[Z180_INT_CSIO] = m_csio->check_interrupt();
+ m_int_pending[Z180_INT_ASCI0] = m_asci[0]->check_interrupt();
+ m_int_pending[Z180_INT_ASCI1] = m_asci[1]->check_interrupt();
}
- for (i = 0; i <= Z180_INT_MAX; i++)
+ int cycles = 0;
+ for (int i = 0; i <= Z180_INT_MAX; i++)
+ {
if (m_int_pending[i])
{
cycles += take_interrupt(i);
m_int_pending[i] = 0;
+ switch (i)
+ {
+ case Z180_INT_ASCI0: m_asci[0]->clear_interrupt(); break;
+ case Z180_INT_ASCI1: m_asci[1]->clear_interrupt(); break;
+ }
break;
}
+ }
return cycles;
}
@@ -2209,12 +2068,13 @@ void z180_device::execute_set_input(int irqline, int state)
}
/* logical to physical address translation */
-bool z180_device::memory_translate(int spacenum, int intention, offs_t &address)
+bool z180_device::memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space)
{
if (spacenum == AS_PROGRAM)
{
address = MMU_REMAP_ADDR(address);
}
+ target_space = &space(spacenum);
return true;
}