summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/tms1000/tms1k_base.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/devices/cpu/tms1000/tms1k_base.h')
-rw-r--r--src/devices/cpu/tms1000/tms1k_base.h310
1 files changed, 157 insertions, 153 deletions
diff --git a/src/devices/cpu/tms1000/tms1k_base.h b/src/devices/cpu/tms1000/tms1k_base.h
index f03d4db24d4..01437ba9d4d 100644
--- a/src/devices/cpu/tms1000/tms1k_base.h
+++ b/src/devices/cpu/tms1000/tms1k_base.h
@@ -17,58 +17,18 @@
#include "machine/pla.h"
-// pinout reference
-
-/*
- ____ ____ ____ ____
- R8 1 |* \_/ | 28 R7 R0 1 |* \_/ | 28 Vss
- R9 2 | | 27 R6 R1 2 | | 27 OSC2
- R10 3 | | 26 R5 R2 3 | | 26 OSC1
- Vdd 4 | | 25 R4 R3 4 | | 25 O0
- K1 5 | | 24 R3 R4 5 | | 24 O1
- K2 6 | TMS1000 | 23 R2 R5 6 | | 23 O2
- K4 7 | TMS1070 | 22 R1 R6 7 | TMS1400 | 22 O3
- K8 8 | TMS1100 | 21 R0 R7 8 | | 21 O4
- INIT 9 | TMS1170 | 20 Vss R8 9 | | 20 O5
- O7 10 | | 19 OSC2 R9 10 | | 19 O6
- O6 11 | | 18 OSC1 R10 11 | | 18 O7
- O5 12 | | 17 O0 Vdd 12 | | 17 K8
- O4 13 | | 16 O1 INIT 13 | | 16 K4
- O3 14 |___________| 15 O2 K1 14 |___________| 15 K2
-
-
- ____ ____
- R2 1 |* \_/ | 28 R3
- R1 2 | | 27 R4
- R0 3 | | 26 R5
- ? 4 | | 25 R6
- Vdd 5 | | 24 R7
- K3 6 | | 23 R8
- K8 7 | TMS0980 | 22 ?
- K4 8 | | 21 ?
- K2 9 | | 20 Vss
- K1 10 | | 19 ?
- O7 11 | | 18 O0
- O6 12 | | 17 O1
- O5 13 | | 16 O2
- O4 14 |___________| 15 O3
-
- note: TMS0980 official pin names for R0-R8 is D9-D1, O0-O7 is S(A-G,DP)
-
-*/
-
-
class tms1k_base_device : public cpu_device
{
public:
- // K input pins
- auto k() { return m_read_k.bind(); }
+ // common handlers
+ auto read_k() { return m_read_k.bind(); } // K input pins
+ auto write_o() { return m_write_o.bind(); } // O/Segment output pins
+ auto write_r() { return m_write_r.bind(); } // R output pins (also called D on some chips)
- // O/Segment output pins
- auto o() { return m_write_o.bind(); }
-
- // R output pins (also called D on some chips)
- auto r() { return m_write_r.bind(); }
+ // TMS2100 handlers
+ auto read_j() { return m_read_j.bind(); } // J input pins
+ auto read_r() { return m_read_r.bind(); } // R0-R3 input pins
+ auto &set_option_dec_div(u8 div) { m_option_dec_div = div; return *this; }
// OFF request on TMS0980 and up
auto power_off() { return m_power_off.bind(); }
@@ -92,7 +52,7 @@ public:
protected:
// construction/destruction
- tms1k_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 o_pins, u8 r_pins, u8 pc_bits, u8 byte_bits, u8 x_bits, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data);
+ tms1k_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 o_pins, u8 r_pins, u8 pc_bits, u8 byte_bits, u8 x_bits, u8 stack_levels, int rom_width, address_map_constructor rom_map, int ram_width, address_map_constructor ram_map);
// device-level overrides
virtual void device_start() override;
@@ -102,7 +62,7 @@ protected:
virtual u32 execute_min_cycles() const noexcept override { return 1; }
virtual u32 execute_max_cycles() const noexcept override { return 1; }
virtual void execute_run() override;
- virtual void execute_one();
+ virtual void execute_one(int subcycle);
// device_memory_interface overrides
virtual space_config_vector memory_space_config() const override;
@@ -113,75 +73,98 @@ protected:
// microinstructions
enum
{
- M_15TN = (1<<0), /* 15 to -ALU */
- M_ATN = (1<<1), /* ACC to -ALU */
- M_AUTA = (1<<2), /* ALU to ACC */
- M_AUTY = (1<<3), /* ALU to Y */
- M_C8 = (1<<4), /* CARRY8 to STATUS */
- M_CIN = (1<<5), /* Carry In to ALU */
- M_CKM = (1<<6), /* CKB to MEM */
- M_CKN = (1<<7), /* CKB to -ALU */
- M_CKP = (1<<8), /* CKB to +ALU */
- M_MTN = (1<<9), /* MEM to -ALU */
- M_MTP = (1<<10), /* MEM to +ALU */
- M_NATN = (1<<11), /* ~ACC to -ALU */
- M_NE = (1<<12), /* COMP to STATUS */
- M_STO = (1<<13), /* ACC to MEM */
- M_STSL = (1<<14), /* STATUS to Status Latch */
- M_YTP = (1<<15), /* Y to +ALU */
-
- M_CME = (1<<16), /* Conditional Memory Enable */
- M_DMTP = (1<<17), /* DAM to +ALU */
- M_NDMTP = (1<<18), /* ~DAM to +ALU */
- M_SSE = (1<<19), /* Special Status Enable */
- M_SSS = (1<<20), /* Special Status Sample */
-
- M_SETR = (1<<21), /* -> line #0d, F_SETR (TP0320 custom), */
- M_RSTR = (1<<22), /* -> line #36, F_RSTR (TMS02x0 custom), */
- M_UNK1 = (1<<23) /* -> line #37, F_???? (TMS0270 custom), */
+ M_15TN = (1U << 0), // 15 to -ALU
+ M_ATN = (1U << 1), // ACC to -ALU
+ M_AUTA = (1U << 2), // ALU to ACC
+ M_AUTY = (1U << 3), // ALU to Y
+ M_C8 = (1U << 4), // CARRY8 to STATUS
+ M_CIN = (1U << 5), // Carry In to ALU
+ M_CKM = (1U << 6), // CKB to MEM
+ M_CKN = (1U << 7), // CKB to -ALU
+ M_CKP = (1U << 8), // CKB to +ALU
+ M_MTN = (1U << 9), // MEM to -ALU
+ M_MTP = (1U << 10), // MEM to +ALU
+ M_NATN = (1U << 11), // ~ACC to -ALU
+ M_NE = (1U << 12), // COMP to STATUS
+ M_STO = (1U << 13), // ACC to MEM
+ M_STSL = (1U << 14), // STATUS to Status Latch
+ M_YTP = (1U << 15), // Y to +ALU
+
+ M_CME = (1U << 16), // Conditional Memory Enable
+ M_DMTP = (1U << 17), // DAM to +ALU
+ M_NDMTP = (1U << 18), // ~DAM to +ALU
+ M_SSE = (1U << 19), // Special Status Enable
+ M_SSS = (1U << 20), // Special Status Sample
+
+ M_SETR = (1U << 21), // -> line #0d, F_SETR (TP0320 custom)
+ M_RSTR = (1U << 22), // -> line #36, F_RSTR (TMS02x0 custom)
+ M_UNK1 = (1U << 23) // -> line #37, F_???? (TMS0270 custom)
};
// standard/fixed instructions - these are documented more in their specific handlers
enum
{
- F_BR = (1<<0),
- F_CALL = (1<<1),
- F_CLO = (1<<2),
- F_COMC = (1<<3),
- F_COMX = (1<<4),
- F_COMX8 = (1<<5),
- F_LDP = (1<<6),
- F_LDX = (1<<7),
- F_RBIT = (1<<8),
- F_RETN = (1<<9),
- F_RSTR = (1<<10),
- F_SBIT = (1<<11),
- F_SETR = (1<<12),
- F_TDO = (1<<13),
- F_TPC = (1<<14),
-
- F_OFF = (1<<15),
- F_REAC = (1<<16),
- F_SAL = (1<<17),
- F_SBL = (1<<18),
- F_SEAC = (1<<19),
- F_XDA = (1<<20)
+ F_BR = (1ULL << 0),
+ F_CALL = (1ULL << 1),
+ F_CLO = (1ULL << 2),
+ F_COMC = (1ULL << 3),
+ F_COMX = (1ULL << 4),
+ F_COMX8 = (1ULL << 5),
+ F_LDP = (1ULL << 6),
+ F_LDX = (1ULL << 7),
+ F_RBIT = (1ULL << 8),
+ F_RETN = (1ULL << 9),
+ F_RSTR = (1ULL << 10),
+ F_SBIT = (1ULL << 11),
+ F_SETR = (1ULL << 12),
+ F_TDO = (1ULL << 13),
+ F_TPC = (1ULL << 14),
+
+ F_TAX = (1ULL << 15),
+ F_TXA = (1ULL << 16),
+ F_TRA = (1ULL << 17),
+ F_TAC = (1ULL << 18),
+ F_TCA = (1ULL << 19),
+ F_TADM = (1ULL << 20),
+ F_TMA = (1ULL << 21),
+
+ F_OFF = (1ULL << 22),
+ F_REAC = (1ULL << 23),
+ F_SAL = (1ULL << 24),
+ F_SBL = (1ULL << 25),
+ F_SEAC = (1ULL << 26),
+ F_XDA = (1ULL << 27),
+
+ F_EXTRA = (1ULL << 28), // custom opcodes
};
+ void rom_10bit(address_map &map);
+ void rom_11bit(address_map &map);
+ void rom_12bit(address_map &map);
+ void ram_6bit(address_map &map);
+ void ram_7bit(address_map &map);
+ void ram_8bit(address_map &map);
+
void next_pc();
- virtual void write_o_output(u8 index);
- virtual u8 read_k_input();
+ virtual void write_o_reg(u8 index);
+ virtual void write_o_output(u16 data) { m_write_o(data & m_o_mask); }
+ virtual void write_r_output(u32 data) { m_write_r(data & m_r_mask); }
+ virtual u8 read_k_input() { return m_read_k() & 0xf; }
virtual void set_cki_bus();
- virtual void dynamic_output() { ; } // not used by default
+ virtual void dynamic_output() { } // not used by default
virtual void read_opcode();
-
- virtual void op_br();
- virtual void op_call();
- virtual void op_retn();
- virtual void op_br3();
- virtual void op_call3();
- virtual void op_retn3();
+ virtual void op_extra() { }
+
+ virtual void op_br() { (m_stack_levels == 1) ? op_br1() : op_brn(); }
+ virtual void op_call() { (m_stack_levels == 1) ? op_call1() : op_calln(); }
+ virtual void op_retn() { (m_stack_levels == 1) ? op_retn1() : op_retnn(); }
+ virtual void op_br1();
+ virtual void op_call1();
+ virtual void op_retn1();
+ virtual void op_brn();
+ virtual void op_calln();
+ virtual void op_retnn();
virtual void op_sbit();
virtual void op_rbit();
@@ -196,15 +179,26 @@ protected:
virtual void op_comc();
virtual void op_tpc();
- virtual void op_xda();
- virtual void op_off();
- virtual void op_seac();
- virtual void op_reac();
- virtual void op_sal();
- virtual void op_sbl();
+
+ virtual void op_tax() { }
+ virtual void op_txa() { }
+ virtual void op_tra() { }
+ virtual void op_tac() { }
+ virtual void op_tca() { }
+ virtual void op_tadm() { }
+ virtual void op_tma() { }
+
+ virtual void op_xda() { }
+ virtual void op_off() { }
+ virtual void op_seac() { }
+ virtual void op_reac() { }
+ virtual void op_sal() { }
+ virtual void op_sbl() { }
address_space_config m_program_config;
address_space_config m_data_config;
+ address_space *m_program;
+ address_space *m_data;
optional_device<pla_device> m_mpla;
optional_device<pla_device> m_ipla;
@@ -212,72 +206,82 @@ protected:
optional_memory_region m_opla_b; // binary dump of output PLA, in place of PLA file
optional_device<pla_device> m_spla;
- u8 m_pc; // 6 or 7-bit program counter
- u32 m_sr; // 6 or 7-bit subroutine return register(s)
- u8 m_pa; // 4-bit page address register
- u8 m_pb; // 4-bit page buffer register
- u16 m_ps; // 4-bit page subroutine register(s)
- u8 m_a; // 4-bit accumulator
- u8 m_x; // 2,3,or 4-bit RAM X register
- u8 m_y; // 4-bit RAM Y register
- u8 m_ca; // chapter address register
- u8 m_cb; // chapter buffer register
- u16 m_cs; // chapter subroutine register(s)
- u16 m_r;
+ // internal state
+ u8 m_pc; // 6 or 7-bit program counter
+ u32 m_sr; // 6 or 7-bit subroutine return register(s)
+ u8 m_pa; // 4-bit page address register
+ u8 m_pb; // 4-bit page buffer register
+ u16 m_ps; // 4-bit page subroutine register(s)
+ u8 m_a; // 4-bit accumulator
+ u8 m_x; // 2,3,or 4-bit RAM X register
+ u8 m_y; // 4-bit RAM Y register
+ u8 m_ca; // chapter address register
+ u8 m_cb; // chapter buffer register
+ u16 m_cs; // chapter subroutine register(s)
+ u32 m_r;
u16 m_o;
u8 m_cki_bus;
u8 m_c4;
- u8 m_p; // 4-bit adder p(lus)-input
- u8 m_n; // 4-bit adder n(egative)-input
- u8 m_adder_out; // adder result
- u8 m_carry_in; // adder carry-in bit
- u8 m_carry_out; // adder carry-out bit
+ u8 m_p; // 4-bit adder p(lus)-input
+ u8 m_n; // 4-bit adder n(egative)-input
+ u8 m_adder_out; // adder result
+ u8 m_carry_in; // adder carry-in bit
+ u8 m_carry_out; // adder carry-out bit
u8 m_status;
u8 m_status_latch;
- u8 m_eac; // end around carry bit
- u8 m_clatch; // call latch bit(s)
- u8 m_add; // add latch bit
- u8 m_bl; // branch latch bit
+ u8 m_eac; // end around carry bit
+ u8 m_clatch; // call latch bit(s)
+ u8 m_add; // add latch bit
+ u8 m_bl; // branch latch bit
u8 m_ram_in;
u8 m_dam_in;
- int m_ram_out; // signed!
+ int m_ram_out; // signed!
u8 m_ram_address;
u16 m_rom_address;
u16 m_opcode;
- u32 m_fixed;
+ u64 m_fixed;
u32 m_micro;
int m_subcycle;
- int m_icount;
u8 m_o_index;
- u8 m_o_pins; // how many O pins
- u8 m_r_pins; // how many R pins
- u8 m_pc_bits; // how many program counter bits
- u8 m_byte_bits; // how many bits per 'byte'
- u8 m_x_bits; // how many X register bits
+ // fixed settings or mask options
+ u8 m_o_pins; // how many O pins
+ u8 m_r_pins; // how many R pins
+ u8 m_pc_bits; // how many program counter bits
+ u8 m_byte_bits; // how many bits per 'byte'
+ u8 m_x_bits; // how many X register bits
+ u8 m_stack_levels; // number of stack levels (max 4)
- address_space *m_program;
- address_space *m_data;
+ u32 m_o_mask;
+ u32 m_r_mask;
+ u32 m_pc_mask;
+ u32 m_x_mask;
- const u16 *m_output_pla_table;
+ u8 m_option_dec_div;
+
+ // i/o handlers
devcb_read8 m_read_k;
devcb_write16 m_write_o;
- devcb_write16 m_write_r;
+ devcb_write32 m_write_r;
+
+ devcb_read8 m_read_j;
+ devcb_read8 m_read_r;
+
devcb_write_line m_power_off;
+
devcb_read8 m_read_ctl;
devcb_write8 m_write_ctl;
devcb_write_line m_write_pdc;
+
+ const u16 *m_output_pla_table;
devcb_read32 m_decode_micro;
- u32 m_o_mask;
- u32 m_r_mask;
- u32 m_k_mask;
- u32 m_pc_mask;
- u32 m_x_mask;
+ int m_icount;
+ int m_state_count;
// lookup tables
- std::vector<u32> m_fixed_decode;
+ std::vector<u64> m_fixed_decode;
std::vector<u32> m_micro_decode;
std::vector<u32> m_micro_direct;
};