diff options
Diffstat (limited to 'src/devices/cpu/sparc')
-rw-r--r-- | src/devices/cpu/sparc/mb86901.cpp | 1175 | ||||
-rw-r--r-- | src/devices/cpu/sparc/sparc.h | 102 | ||||
-rw-r--r-- | src/devices/cpu/sparc/sparcdefs.h | 738 |
3 files changed, 1007 insertions, 1008 deletions
diff --git a/src/devices/cpu/sparc/mb86901.cpp b/src/devices/cpu/sparc/mb86901.cpp index 0a1bf03938b..2bf8e1ba284 100644 --- a/src/devices/cpu/sparc/mb86901.cpp +++ b/src/devices/cpu/sparc/mb86901.cpp @@ -10,8 +10,8 @@ // // To-Do: // - Ops: FBFcc, LDF, STF -// - Test: SPARCv8 ops are untested -// - Test: Traps are untested +// - Test: SPARCv8 ops are untested +// - Test: Traps are untested // - FPU support // - Coprocessor support // @@ -155,17 +155,17 @@ void mb86901_device::device_start() #endif // register our state for the debugger - state_add(STATE_GENPC, "GENPC", m_pc).noshow(); - state_add(STATE_GENFLAGS, "GENFLAGS", m_psr).callimport().callexport().formatstr("%6s").noshow(); - state_add(SPARC_PC, "PC", m_pc).formatstr("%08X"); - state_add(SPARC_NPC, "nPC", m_npc).formatstr("%08X"); - state_add(SPARC_PSR, "PSR", m_psr).formatstr("%08X"); - state_add(SPARC_WIM, "WIM", m_wim).formatstr("%08X"); - state_add(SPARC_TBR, "TBR", m_tbr).formatstr("%08X"); - state_add(SPARC_Y, "Y", m_y).formatstr("%08X"); - state_add(SPARC_ANNUL, "ANNUL", m_annul).formatstr("%01d"); - state_add(SPARC_ICC, "icc", m_icc).formatstr("%4s"); - state_add(SPARC_CWP, "CWP", m_cwp).formatstr("%2d"); + state_add(STATE_GENPC, "GENPC", m_pc).noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_psr).callimport().callexport().formatstr("%6s").noshow(); + state_add(SPARC_PC, "PC", m_pc).formatstr("%08X"); + state_add(SPARC_NPC, "nPC", m_npc).formatstr("%08X"); + state_add(SPARC_PSR, "PSR", m_psr).formatstr("%08X"); + state_add(SPARC_WIM, "WIM", m_wim).formatstr("%08X"); + state_add(SPARC_TBR, "TBR", m_tbr).formatstr("%08X"); + state_add(SPARC_Y, "Y", m_y).formatstr("%08X"); + state_add(SPARC_ANNUL, "ANNUL", m_annul).formatstr("%01d"); + state_add(SPARC_ICC, "icc", m_icc).formatstr("%4s"); + state_add(SPARC_CWP, "CWP", m_cwp).formatstr("%2d"); char regname[3] = "g0"; for (int i = 0; i < 8; i++) { @@ -192,12 +192,12 @@ void mb86901_device::device_start() state_add(SPARC_I0 + i, regname, m_dbgregs[16+i]).formatstr("%08X"); } - state_add(SPARC_EC, "EC", m_ec).formatstr("%1d"); - state_add(SPARC_EF, "EF", m_ef).formatstr("%1d"); - state_add(SPARC_ET, "ET", m_et).formatstr("%1d"); - state_add(SPARC_PIL, "PIL", m_pil).formatstr("%2d"); - state_add(SPARC_S, "S", m_s).formatstr("%1d"); - state_add(SPARC_PS, "PS", m_ps).formatstr("%1d"); + state_add(SPARC_EC, "EC", m_ec).formatstr("%1d"); + state_add(SPARC_EF, "EF", m_ef).formatstr("%1d"); + state_add(SPARC_ET, "ET", m_et).formatstr("%1d"); + state_add(SPARC_PIL, "PIL", m_pil).formatstr("%2d"); + state_add(SPARC_S, "S", m_s).formatstr("%1d"); + state_add(SPARC_PS, "PS", m_ps).formatstr("%1d"); char rname[5]; for (int i = 0; i < 120; i++) @@ -415,13 +415,13 @@ void mb86901_device::state_string_export(const device_state_entry &entry, std::s case SPARC_ICC: str = string_format("%c%c%c%c", ICC_N_SET ? 'n' : ' ', ICC_Z_SET ? 'z' : ' ', ICC_V_SET ? 'v' : ' ', ICC_C_SET ? 'c' : ' '); break; - case SPARC_O0: case SPARC_O1: case SPARC_O2: case SPARC_O3: case SPARC_O4: case SPARC_O5: case SPARC_O6: case SPARC_O7: + case SPARC_O0: case SPARC_O1: case SPARC_O2: case SPARC_O3: case SPARC_O4: case SPARC_O5: case SPARC_O6: case SPARC_O7: str = string_format("%08X", m_dbgregs[entry.index() - SPARC_O0]); break; - case SPARC_L0: case SPARC_L1: case SPARC_L2: case SPARC_L3: case SPARC_L4: case SPARC_L5: case SPARC_L6: case SPARC_L7: + case SPARC_L0: case SPARC_L1: case SPARC_L2: case SPARC_L3: case SPARC_L4: case SPARC_L5: case SPARC_L6: case SPARC_L7: str = string_format("%08X", m_dbgregs[8 + (entry.index() - SPARC_L0)]); break; - case SPARC_I0: case SPARC_I1: case SPARC_I2: case SPARC_I3: case SPARC_I4: case SPARC_I5: case SPARC_I6: case SPARC_I7: + case SPARC_I0: case SPARC_I1: case SPARC_I2: case SPARC_I3: case SPARC_I4: case SPARC_I5: case SPARC_I6: case SPARC_I7: str = string_format("%08X", m_dbgregs[16 + (entry.index() - SPARC_I0)]); break; } @@ -524,21 +524,21 @@ void mb86901_device::execute_add(UINT32 op) operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); if (ADD or ADDcc) then - result <- r[rs1] + operand2; + result <- r[rs1] + operand2; else if (ADDX or ADDXcc) then - result <= r[rs1] + operand2 + C; + result <= r[rs1] + operand2 + C; next; if (rd != 0) then - r[rd] <- result; + r[rd] <- result; if (ADDcc or ADDXcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- (r[rs1]<31> and operand2<31> and (not result<31>)) or - ((not r[rs1]<31>) and (not operand2<31>) and result<31>); - C <- (r[rs1]<31> and operand2<31>) or - ((not result<31>) and (r[rs1]<31> or operand2<31>)) + N <- result<31>; + Z <- if (result = 0) then 1 else 0; + V <- (r[rs1]<31> and operand2<31> and (not result<31>)) or + ((not r[rs1]<31>) and (not operand2<31>) and result<31>); + C <- (r[rs1]<31> and operand2<31>) or + ((not result<31>) and (r[rs1]<31> or operand2<31>)) ); */ UINT32 operand2 = USEIMM ? SIMM13 : RS2REG; @@ -559,9 +559,9 @@ void mb86901_device::execute_add(UINT32 op) PSR |= (BIT31(result)) ? PSR_N_MASK : 0; PSR |= (result == 0) ? PSR_Z_MASK : 0; PSR |= ((BIT31(RS1REG) && BIT31(operand2) && !BIT31(result)) || - (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; + (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; PSR |= ((BIT31(RS1REG) && BIT31(operand2)) || - (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; + (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; } } @@ -586,16 +586,16 @@ void mb86901_device::execute_taddcc(UINT32 op) next; if (TADDccTV and (temp_V = 1)) then ( - trap <- 1; - tag_overflow <- 1 + trap <- 1; + tag_overflow <- 1 ) else ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- temp_V; - C <- (r[rs1]<31> and operand2<31>) or - ((not result<31>) and (r[rs1]<31> or operand2<31>)); - if (rd != 0) then - r[rd] <- result; + N <- result<31>; + Z <- if (result = 0) then 1 else 0; + V <- temp_V; + C <- (r[rs1]<31> and operand2<31>) or + ((not result<31>) and (r[rs1]<31> or operand2<31>)); + if (rd != 0) then + r[rd] <- result; ); */ UINT32 operand2 = USEIMM ? SIMM13 : RS2REG; @@ -603,8 +603,8 @@ void mb86901_device::execute_taddcc(UINT32 op) UINT32 result = RS1REG + operand2; bool temp_v = (BIT31(RS1REG) && BIT31(operand2) && !BIT31(result)) || - (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result)) || - ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false; + (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result)) || + ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false; if (TADDCCTV && temp_v) { @@ -618,7 +618,7 @@ void mb86901_device::execute_taddcc(UINT32 op) PSR |= (result == 0) ? PSR_Z_MASK : 0; PSR |= temp_v ? PSR_V_MASK : 0; PSR |= ((BIT31(RS1REG) && BIT31(operand2)) || - (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; + (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; if (RD != 0) RDREG = result; @@ -638,21 +638,21 @@ void mb86901_device::execute_sub(UINT32 op) operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); if (SUB or SUBcc) then - result <- r[rs1] - operand2; + result <- r[rs1] - operand2; else if (SUBX or SUBXcc) then - result <= r[rs1] - operand2 - C; + result <= r[rs1] - operand2 - C; next; if (rd != 0) then - r[rd] <- result; + r[rd] <- result; if (SUBcc or SUBXcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- (r[rs1]<31> and (not operand2<31>) and (not result<31>)) or - ((not r[rs1]<31>) and operand2<31> and result<31>); - C <- ((not r[rs1]<31>) and operand2<31>) or - (result<31> and ((not r[rs1]<31>) or operand2<31>)) + N <- result<31>; + Z <- if (result = 0) then 1 else 0; + V <- (r[rs1]<31> and (not operand2<31>) and (not result<31>)) or + ((not r[rs1]<31>) and operand2<31> and result<31>); + C <- ((not r[rs1]<31>) and operand2<31>) or + (result<31> and ((not r[rs1]<31>) or operand2<31>)) ); */ UINT32 operand2 = USEIMM ? SIMM13 : RS2REG; @@ -672,9 +672,9 @@ void mb86901_device::execute_sub(UINT32 op) PSR |= (BIT31(result)) ? PSR_N_MASK : 0; PSR |= (result == 0) ? PSR_Z_MASK : 0; PSR |= ((BIT31(RS1REG) && !BIT31(operand2) && !BIT31(result)) || - (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; + (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; PSR |= ((!BIT31(RS1REG) && BIT31(operand2)) || - (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; + (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; } } @@ -699,16 +699,16 @@ void mb86901_device::execute_tsubcc(UINT32 op) next; if (TSUBccTV and (temp_V = 1)) then ( - trap <- 1; - tag_overflow <- 1 + trap <- 1; + tag_overflow <- 1 ) else ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- temp_V; - C <- ((not r[rs1]<31>) and operand2<31>) or - (result<31> and ((not r[rs1]<31>) or operand2<31>)); - if (rd != 0) then - r[rd] <- result; + N <- result<31>; + Z <- if (result = 0) then 1 else 0; + V <- temp_V; + C <- ((not r[rs1]<31>) and operand2<31>) or + (result<31> and ((not r[rs1]<31>) or operand2<31>)); + if (rd != 0) then + r[rd] <- result; ); */ @@ -717,8 +717,8 @@ void mb86901_device::execute_tsubcc(UINT32 op) UINT32 result = RS1REG - operand2; bool temp_v = (BIT31(RS1REG) && !BIT31(operand2) && !BIT31(result)) || - (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result)) || - ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false; + (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result)) || + ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false; if (TSUBCCTV && temp_v) { @@ -732,7 +732,7 @@ void mb86901_device::execute_tsubcc(UINT32 op) PSR |= (result == 0) ? PSR_Z_MASK : 0; PSR |= temp_v ? PSR_V_MASK : 0; PSR |= ((!BIT31(RS1REG) && BIT31(operand2)) || - (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; + (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; if (RD != 0) RDREG = result; @@ -762,10 +762,10 @@ void mb86901_device::execute_logical(UINT32 op) if (rd != 0) then r[rd] <- result; if (ANDcccc or ANDNcc or ORcc or ORNcc or XORcc or XNORcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- 0 - C <- 0 + N <- result<31>; + Z <- if (result = 0) then 1 else 0; + V <- 0 + C <- 0 ); */ @@ -824,11 +824,11 @@ void mb86901_device::execute_shift(UINT32 op) shift_count := if (i = 0) then r[rs2]<4:0> else shcnt; if (SLL and (rd != 0) ) then - r[rd] <- shift_left_logical(r[rs1], shift_count) + r[rd] <- shift_left_logical(r[rs1], shift_count) else if (SRL and (rd != 0) ) then - r[rd] <- shift_right_logical(r[rs1], shift_count) + r[rd] <- shift_right_logical(r[rs1], shift_count) else if (SRA and (rd != 0) ) then - r[rd] <- shift_right_arithmetic(r[rs1], shift_count) + r[rd] <- shift_right_arithmetic(r[rs1], shift_count) */ UINT32 shift_count = USEIMM ? (SIMM13 & 31) : (RS2REG & 31); @@ -852,8 +852,8 @@ void mb86901_device::execute_mulscc(UINT32 op) operand1 := (N xor V) [] (r[rs1]<31:1>); operand2 := ( - if (Y<0> = 0) then 0 - else if (i = 0) then r[rs2] else sign_extend(simm13) + if (Y<0> = 0) then 0 + else if (i = 0) then r[rs2] else sign_extend(simm13) ); result <- operand1 + operand2; @@ -861,7 +861,7 @@ void mb86901_device::execute_mulscc(UINT32 op) next; if (rd != 0) then ( - r[rd] <- result; + r[rd] <- result; ) N <- result<31>; Z <- if (result = 0) then 1 else 0; @@ -884,9 +884,9 @@ void mb86901_device::execute_mulscc(UINT32 op) PSR |= (BIT31(result)) ? PSR_N_MASK : 0; PSR |= (result == 0) ? PSR_Z_MASK : 0; PSR |= ((BIT31(operand1) && BIT31(operand2) && !BIT31(result)) || - (!BIT31(operand1) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; + (!BIT31(operand1) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; PSR |= ((BIT31(operand1) && BIT31(operand2)) || - (!BIT31(result) && (BIT31(operand1) || BIT31(operand2)))) ? PSR_C_MASK : 0; + (!BIT31(result) && (BIT31(operand1) || BIT31(operand2)))) ? PSR_C_MASK : 0; } @@ -901,17 +901,17 @@ void mb86901_device::execute_rdsr(UINT32 op) if ((RDPSR or RDWIM or RDBTR or (RDASR and (privileged_ASR(rs1) = 1))) and (S = 0)) then ( - trap <- 1; - privileged_instruction <- 1; + trap <- 1; + privileged_instruction <- 1; else if (illegal_instruction_ASR(rs1) = 1) then ( - trap <- 1; - illegal_instruction <- 1 + trap <- 1; + illegal_instruction <- 1 else if (rd != 0) then ( - if (RDY) then r[rd] <- Y - else if (RDASR) then r[rd] <- ASR[rs1] - else if (RDPSR) then r[rd] <- PSR - else if (RDWIM) then r[rd] <- WIM - else if (RDTBR) then r[rd] <- TBR; + if (RDY) then r[rd] <- Y + else if (RDASR) then r[rd] <- ASR[rs1] + else if (RDPSR) then r[rd] <- PSR + else if (RDWIM) then r[rd] <- WIM + else if (RDTBR) then r[rd] <- TBR; ); */ @@ -957,41 +957,41 @@ void mb86901_device::execute_wrsr(UINT32 op) result := r[rs1] xor operand2; if (WRY) then ( - Y'''' <- result + Y'''' <- result ) else if (WRASR) then ( - if ( (privileged_ASR(rd) = 1) and (S = 0) ) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (illegal_instruction_ASR(rd) = 1) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - ASR[rd]'''' <- result - ) + if ( (privileged_ASR(rd) = 1) and (S = 0) ) then ( + trap <- 1; + privileged_instruction <- 1 + ) else if (illegal_instruction_ASR(rd) = 1) then ( + trap <- 1; + illegal_instruction <- 1 + ) else ( + ASR[rd]'''' <- result + ) ) else if (WRPSR) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (result<4:0> >= NWINDOWS) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - PSR'''' <- result - ) + if (S = 0) then ( + trap <- 1; + privileged_instruction <- 1 + ) else if (result<4:0> >= NWINDOWS) then ( + trap <- 1; + illegal_instruction <- 1 + ) else ( + PSR'''' <- result + ) ) else if (WRWIM) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else ( - WIM'''' <- result - ) + if (S = 0) then ( + trap <- 1; + privileged_instruction <- 1 + ) else ( + WIM'''' <- result + ) ) else if (WRBTR) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else ( - WIM'''' <- result - ) + if (S = 0) then ( + trap <- 1; + privileged_instruction <- 1 + ) else ( + WIM'''' <- result + ) ); */ UINT32 operand2 = USEIMM ? SIMM13 : RS2REG; @@ -1009,8 +1009,8 @@ void mb86901_device::execute_wrsr(UINT32 op) m_trap = 1; m_privileged_instruction = 1; } - else if (m_illegal_instruction_asr[RD]) - { + else if (m_illegal_instruction_asr[RD]) + { m_trap = 1; m_illegal_instruction = 1; } @@ -1043,8 +1043,8 @@ void mb86901_device::execute_wrsr(UINT32 op) m_trap = 1; m_privileged_instruction = 1; } - else - { + else + { WIM = result & 0x7f; } } @@ -1055,8 +1055,8 @@ void mb86901_device::execute_wrsr(UINT32 op) m_trap = 1; m_privileged_instruction = 1; } - else - { + else + { TBR = result & 0xfffff000; } } @@ -1076,33 +1076,33 @@ void mb86901_device::execute_rett(UINT32 op) address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); next; if (ET = 1) then ( - trap <- 1; - if (S = 0) then privileged_instruction <- 1 - else if (S != 0) then illegal_instruction <- 1 + trap <- 1; + if (S = 0) then privileged_instruction <- 1 + else if (S != 0) then illegal_instruction <- 1 ) else if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - tt <- 00000011; { trap type for privileged_instruction } - execute_mode <- 0; - error_mode = 1 + trap <- 1; + privileged_instruction <- 1 + tt <- 00000011; { trap type for privileged_instruction } + execute_mode <- 0; + error_mode = 1 ) else if ((WIM and (1 << new_cwp)) != 0) then ( - trap <- 1; - window_underflow <- 1; - tt <- 00000110; { trap type for window_underflow } - execute_mode = 0; - error_mode = 1 + trap <- 1; + window_underflow <- 1; + tt <- 00000110; { trap type for window_underflow } + execute_mode = 0; + error_mode = 1 ) else if (address<1:0> != 0) then ( - trap = 1; - mem_address_not_aligned = 1; - tt = 7; { trap type for mem_address_not_aligned } - execute_mode = 0; - error_mode = 1 + trap = 1; + mem_address_not_aligned = 1; + tt = 7; { trap type for mem_address_not_aligned } + execute_mode = 0; + error_mode = 1 ) else ( - ET <- 1; - PC <- nPC; - nPC <- address; - CWP <- new_cwp; - S <- PS + ET <- 1; + PC <- nPC; + nPC <- address; + CWP <- new_cwp; + S <- PS ) */ @@ -1166,29 +1166,29 @@ void mb86901_device::execute_saverestore(UINT32 op) operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); if (SAVE) then ( - new_cwp <- (CWP - 1) modulo NWINDOWS; - next; - if ((WIM and (1 << new_cwp)) != 0) then ( - trap <- 1; - window_overflow <- 1 - ) else ( - result <- r[rs1] + operand2; { operands from old window } - CWP <- new_cwp - ) + new_cwp <- (CWP - 1) modulo NWINDOWS; + next; + if ((WIM and (1 << new_cwp)) != 0) then ( + trap <- 1; + window_overflow <- 1 + ) else ( + result <- r[rs1] + operand2; { operands from old window } + CWP <- new_cwp + ) ) else if (RESTORE) then ( - new_cwp <- (CWP + 1) modulo NWINDOWS; - next; - if ((WIM and (1 << new_cwp)) != 0) then ( - trap <- 1; - window_overflow <- 1 - ) else ( - result <- r[rs1] + operand2; { operands from old window } - CWP <- new_cwp - ) + new_cwp <- (CWP + 1) modulo NWINDOWS; + next; + if ((WIM and (1 << new_cwp)) != 0) then ( + trap <- 1; + window_overflow <- 1 + ) else ( + result <- r[rs1] + operand2; { operands from old window } + CWP <- new_cwp + ) ); next; if ((trap = 0) and (rd != 0)) then - r[rd] <- result { destination in new window } + r[rd] <- result { destination in new window } */ UINT32 rs1 = RS1REG; @@ -1243,12 +1243,12 @@ void mb86901_device::execute_jmpl(UINT32 op) jump_address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); next; if (jump_address<1:0> != 0) then ( - trap <- 1; - mem_address_not_aligned <- 1 + trap <- 1; + mem_address_not_aligned <- 1 ) else ( - if (rd != 0) then r[rd] <- PC; - PC <- nPC; - nPC <- jump_address + if (rd != 0) then r[rd] <- PC; + PC <- nPC; + nPC <- jump_address ) */ @@ -1417,119 +1417,119 @@ void mb86901_device::execute_store(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 165, "Appendix C - ISP Descriptions - Store Instructions" (SPARCv8.pdf, pg. 162) if ( (S = 0) and (STDA or STA or STHA or STBA or STDFQ or STDCQ) ) then ( - trap <- 1; - privileged_instruction <- 1 + trap <- 1; + privileged_instruction <- 1 ) else if ((i = 1) and (STDA or STA or STHA or STBA)) then ( - trap <- 1; - illegal_instruction <- 1 + trap <- 1; + illegal_instruction <- 1 ); next; if (trap = 0) then ( - if (STD or ST or STH or STB or STF or STDF or STFSR or STDFQ or STCSR or STC or STDC or STDCQ) then ( - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - addr_space <- (if (S = 0) then 10 else 11) - ) else if (STDA or STA or STHA or STBA) then ( - address <- r[rs1] + r[rs2]; - addr_space <- asi - ); - if ((STF or STDF or STFSR or STDFQ) and - ((EF = 0) or (bp_FPU_present = 0)) ) then ( - trap <- 1; - fp_disabled <- 1; - ); - if ((STC or STDC or STCSR or STDCQ) and - ((EC = 0) or (bp_CP_present = 0)) ) then ( - trap <- 1; - cp_disabled <- 1; - ) + if (STD or ST or STH or STB or STF or STDF or STFSR or STDFQ or STCSR or STC or STDC or STDCQ) then ( + address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); + addr_space <- (if (S = 0) then 10 else 11) + ) else if (STDA or STA or STHA or STBA) then ( + address <- r[rs1] + r[rs2]; + addr_space <- asi + ); + if ((STF or STDF or STFSR or STDFQ) and + ((EF = 0) or (bp_FPU_present = 0)) ) then ( + trap <- 1; + fp_disabled <- 1; + ); + if ((STC or STDC or STCSR or STDCQ) and + ((EC = 0) or (bp_CP_present = 0)) ) then ( + trap <- 1; + cp_disabled <- 1; + ) ); next; if (trap = 0) then ( - if ((STH or STHA) and (address<0> != 0)) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else if ((ST or STA or STF or STFSR or STC or STCSR) and (address<1:0> != 0)) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else if ((STD or STDA or STDF or STDFQ or STDC or STDCQ) and (address<2:0> != 0)) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else ( - if (STDFQ and ((implementation has no floating-point queue) or (FSR.qne = 0))) then ( - trap <- 1; - fp_exception <- 1; - ftt <- sequence_error; - ); - if (STDCQ and ((implementation has no coprocessor queue)) then ( - trap <- 1; - cp_exception <- 1; - { possibly additional implementation-dependent actions } - ); - if (STDF and (rd<0> != 0)) then ( - trap <- 1; - fp_exception <- 1; - ftt <- invalid_fp_register; - ) - ) + if ((STH or STHA) and (address<0> != 0)) then ( + trap <- 1; + mem_address_not_aligned <- 1 + ) else if ((ST or STA or STF or STFSR or STC or STCSR) and (address<1:0> != 0)) then ( + trap <- 1; + mem_address_not_aligned <- 1 + ) else if ((STD or STDA or STDF or STDFQ or STDC or STDCQ) and (address<2:0> != 0)) then ( + trap <- 1; + mem_address_not_aligned <- 1 + ) else ( + if (STDFQ and ((implementation has no floating-point queue) or (FSR.qne = 0))) then ( + trap <- 1; + fp_exception <- 1; + ftt <- sequence_error; + ); + if (STDCQ and ((implementation has no coprocessor queue)) then ( + trap <- 1; + cp_exception <- 1; + { possibly additional implementation-dependent actions } + ); + if (STDF and (rd<0> != 0)) then ( + trap <- 1; + fp_exception <- 1; + ftt <- invalid_fp_register; + ) + ) ); next; if (trap = 0) then ( - if (STF) then ( byte_mask <- 1111; data0 <- f[rd] ) - else if (STC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STDF) then ( byte_mask <- 1111; data0 <- f[rd & 0x1e] ) - else if (STDC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STD or STDA) then ( byte_mask <- 1111; data0 <- r[rd & 0x1e] ) - else if (STDFQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STDCQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STFSR) then ( - while ((FSR.qne = 1) and (trap = 0)) ( - // wait for pending floating-point instructions to complete - ) - next; - byte_mask <- 1111; data0 <- FSR - ) else if (STCSR) then ( - { implementation-dependent actions } - byte_mask <- 1111; data0 <- CSR - ) else if (ST or STA) then ( byte_mask <- 1111; data0 = r[rd] ) - else if (STH or STHA) then ( - if (address<1:0> = 0) then ( - byte_mask <- 1100; data0 <- shift_left_logical(r[rd], 16) ) - else if (address<1:0> = 2) then ( - byte_mask <- 0011; data0 <- r[rd] ) - ) else if (STB or STBA) then ( - if (address<1:0> = 0) then ( - byte_mask <- 1000; data0 <- shift_left_logical(r[rd], 24) ) - ) else if (address<1:0> = 1) then ( - byte_mask <- 0100; data0 <- shift_left_logical(r[rd], 16) ) - ) else if (address<1:0> = 2) then ( - byte_mask <- 0010; data0 <- shift_left_logical(r[rd], 8) ) - ) else if (address<1:0> = 3) then ( - byte_mask <- 0001; data0 <- r[rd] ) - ) - ); + if (STF) then ( byte_mask <- 1111; data0 <- f[rd] ) + else if (STC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) + else if (STDF) then ( byte_mask <- 1111; data0 <- f[rd & 0x1e] ) + else if (STDC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) + else if (STD or STDA) then ( byte_mask <- 1111; data0 <- r[rd & 0x1e] ) + else if (STDFQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) + else if (STDCQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) + else if (STFSR) then ( + while ((FSR.qne = 1) and (trap = 0)) ( + // wait for pending floating-point instructions to complete + ) + next; + byte_mask <- 1111; data0 <- FSR + ) else if (STCSR) then ( + { implementation-dependent actions } + byte_mask <- 1111; data0 <- CSR + ) else if (ST or STA) then ( byte_mask <- 1111; data0 = r[rd] ) + else if (STH or STHA) then ( + if (address<1:0> = 0) then ( + byte_mask <- 1100; data0 <- shift_left_logical(r[rd], 16) ) + else if (address<1:0> = 2) then ( + byte_mask <- 0011; data0 <- r[rd] ) + ) else if (STB or STBA) then ( + if (address<1:0> = 0) then ( + byte_mask <- 1000; data0 <- shift_left_logical(r[rd], 24) ) + ) else if (address<1:0> = 1) then ( + byte_mask <- 0100; data0 <- shift_left_logical(r[rd], 16) ) + ) else if (address<1:0> = 2) then ( + byte_mask <- 0010; data0 <- shift_left_logical(r[rd], 8) ) + ) else if (address<1:0> = 3) then ( + byte_mask <- 0001; data0 <- r[rd] ) + ) + ); ); next; if (trap = 0) then ( - MAE <- memory_write(addr_space, address, byte_mask, data1); - next; - if (MAE = 1) then ( - trap <- 1; - data_access_exception <- 1 - ) + MAE <- memory_write(addr_space, address, byte_mask, data1); + next; + if (MAE = 1) then ( + trap <- 1; + data_access_exception <- 1 + ) ); if ((trap = 0) and (STD or STDA or STDF or STDC or STDFQ or STDCQ)) then ( - if (STD or STDA) then ( data1 <- r[rd or 00001] ) - else if (STDF) then ( data1 <- f[rd or 00001] ) - else if (STDC) then ( data1 <- implementation_dependent_value } - else if (STDFQ) then ( data1 <- implementation_dependent_value } - else if (STDCQ) then ( data1 <- implementation_dependent_value } - next; - MAE <- memory_write(addr_space, address + 4, 1111, data1); - next; - if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } - trap <- 1; - data_access_exception <- 1 - ) + if (STD or STDA) then ( data1 <- r[rd or 00001] ) + else if (STDF) then ( data1 <- f[rd or 00001] ) + else if (STDC) then ( data1 <- implementation_dependent_value } + else if (STDFQ) then ( data1 <- implementation_dependent_value } + else if (STDCQ) then ( data1 <- implementation_dependent_value } + next; + MAE <- memory_write(addr_space, address + 4, 1111, data1); + next; + if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } + trap <- 1; + data_access_exception <- 1 + ) ); */ @@ -1760,100 +1760,100 @@ void mb86901_device::execute_load(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 163, "Appendix C - ISP Descriptions - C.9. Instruction Defintions - Load Instructions" (SPARCv8.pdf, pg. 160) if (LDD or LD or LDSH or LDUH or LDSB or LDUB or LDDF or LDF or LDFSR or LDDC or LDC or LDCSR) then ( - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - addr_space <- (if (S = 0) then 10 else 11) + address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); + addr_space <- (if (S = 0) then 10 else 11) ) else if (LDDA or LDA or LDSHA or LDUHA or LDSBA or LDUBA) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (i = 1) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - address <- r[rs1] + r[rs2]; - addr_space <- asi - ) + if (S = 0) then ( + trap <- 1; + privileged_instruction <- 1 + ) else if (i = 1) then ( + trap <- 1; + illegal_instruction <- 1 + ) else ( + address <- r[rs1] + r[rs2]; + addr_space <- asi + ) ) next; if (trap = 0) then ( - if ( (LDF or LDDF or LDFSR) and ((EF = 0) or (bp_FPU_present = 0)) then ( - trap <- 1; - fp_disabled <- 1 - ) else if ( (LDC or LDDC or LDCSR) and ((EC = 0) or (bp_CP_present = 0)) then ( - trap <- 1; - cp_disabled <- 1 - ) else if ( ( (LDD or LDDA or LDDF or LDDC) and (address<2:0> != 0)) or - ((LD or LDA or LDF or LDFSR or LDC or LDCSR) and (address<1:0> != 0)) or - ((LDSH or LDSHA or LDUH or LDUHA) and address<0> != 0) ) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else if (LDDF and (rd<0> != 0)) then ( - trap <- 1; - fp_exception <- 1; - ftt <- invalid_fpr_register - ) else if ((LDF or LDDF or LDFSR) and (an FPU sequence error is detected)) then ( - trap <- 1; - fp_exception <- 1; - ftt <- sequence_error - ) else if ((LDC or LDDC or LDCSR) and (a CP sequence error is detected)) then ( - trap <- 1; - cp_exception <- 1; - { possibly additional implementation-dependent actions } - ) + if ( (LDF or LDDF or LDFSR) and ((EF = 0) or (bp_FPU_present = 0)) then ( + trap <- 1; + fp_disabled <- 1 + ) else if ( (LDC or LDDC or LDCSR) and ((EC = 0) or (bp_CP_present = 0)) then ( + trap <- 1; + cp_disabled <- 1 + ) else if ( ( (LDD or LDDA or LDDF or LDDC) and (address<2:0> != 0)) or + ((LD or LDA or LDF or LDFSR or LDC or LDCSR) and (address<1:0> != 0)) or + ((LDSH or LDSHA or LDUH or LDUHA) and address<0> != 0) ) then ( + trap <- 1; + mem_address_not_aligned <- 1 + ) else if (LDDF and (rd<0> != 0)) then ( + trap <- 1; + fp_exception <- 1; + ftt <- invalid_fpr_register + ) else if ((LDF or LDDF or LDFSR) and (an FPU sequence error is detected)) then ( + trap <- 1; + fp_exception <- 1; + ftt <- sequence_error + ) else if ((LDC or LDDC or LDCSR) and (a CP sequence error is detected)) then ( + trap <- 1; + cp_exception <- 1; + { possibly additional implementation-dependent actions } + ) ); next; if (trap = 0) then { - (data, MAE) <- memory_read(addr_space, address); - next; - if (MAE = 1) then ( - trap <- 1; - data_access_exception <- 1; - ) else ( - if (LDSB or LDSBA or LDUB or LDUBA) then ( - if (address<1:0> = 0) then byte <- data<31:24> - else if (address<1:0> = 1) then byte <- data<23:16> - else if (address<1:0> = 2) then byte <- data<15: 8> - else if (address<1:0> = 3) then byte <- data< 7: 0> - next; - if (LDSB or LDSBA) then - word0 <- sign_extend_byte(byte) - else - word0 <- zero_extend_byte(byte) - ) else if (LDSH or LDSHA or LDUH or LDUHA) then ( - if (address<1:0> = 0) then halfword <- data<31:16> - else if (address<1:0> = 2) then halfword <- data<15: 0> - next; - if (LDSH or LDSHA) then - word0 <- sign_extend_halfword(halfword) - else - word0 <- zero_extend_halfword(halfword) - ) else - word0 <- data - ) + (data, MAE) <- memory_read(addr_space, address); + next; + if (MAE = 1) then ( + trap <- 1; + data_access_exception <- 1; + ) else ( + if (LDSB or LDSBA or LDUB or LDUBA) then ( + if (address<1:0> = 0) then byte <- data<31:24> + else if (address<1:0> = 1) then byte <- data<23:16> + else if (address<1:0> = 2) then byte <- data<15: 8> + else if (address<1:0> = 3) then byte <- data< 7: 0> + next; + if (LDSB or LDSBA) then + word0 <- sign_extend_byte(byte) + else + word0 <- zero_extend_byte(byte) + ) else if (LDSH or LDSHA or LDUH or LDUHA) then ( + if (address<1:0> = 0) then halfword <- data<31:16> + else if (address<1:0> = 2) then halfword <- data<15: 0> + next; + if (LDSH or LDSHA) then + word0 <- sign_extend_halfword(halfword) + else + word0 <- zero_extend_halfword(halfword) + ) else + word0 <- data + ) ); next; if (trap = 0) then ( - if ( (rd != 0) and (LD or LDA or LDSH or LDSHA - or LDUHA or LDUH or LDSB or LDSBA or LDUB or LDUBA) ) then - r[rd] <- word0 - else if (LDF) then f[rd] <- word0 - else if (LDC) then { implementation-dependent actions } - else if (LDFSR) then FSR <- word0 - else if (LDCSR) then CSR <- word0 - else if (LDD or LDDA) then r[rd and 11110] <- word0 - else if (LDDF) then f[rd and 11110] <- word0 - else if (LDDC) then { implementation-dependent actions } + if ( (rd != 0) and (LD or LDA or LDSH or LDSHA + or LDUHA or LDUH or LDSB or LDSBA or LDUB or LDUBA) ) then + r[rd] <- word0 + else if (LDF) then f[rd] <- word0 + else if (LDC) then { implementation-dependent actions } + else if (LDFSR) then FSR <- word0 + else if (LDCSR) then CSR <- word0 + else if (LDD or LDDA) then r[rd and 11110] <- word0 + else if (LDDF) then f[rd and 11110] <- word0 + else if (LDDC) then { implementation-dependent actions } ); next; if (((trap = 0) and (LDD or LDDA or LDDF or LDDC)) then ( - (word1, MAE) <- memory_read(addr_space, address + 4); - next; - if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } - trap <- 1; - data_access_exception <- 1 ) - else if (LDD or LDDA) then r[rd or 1] <- word1 - else if (LDDF) then f[rd or 1] <- word1 - else if (LDDC) then { implementation-dependent actions } + (word1, MAE) <- memory_read(addr_space, address + 4); + next; + if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } + trap <- 1; + data_access_exception <- 1 ) + else if (LDD or LDDA) then r[rd or 1] <- word1 + else if (LDDF) then f[rd or 1] <- word1 + else if (LDDC) then { implementation-dependent actions } ); */ @@ -2008,59 +2008,59 @@ void mb86901_device::execute_ldstub(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 169, "Appendix C - ISP Descriptions - Atomic Load-Store Unsigned Byte Instructions" (SPARCv8.pdf, pg. 166) if (LDSTUB) then ( - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - addr_space <- (if (S = 0) then 10 else 11) + address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); + addr_space <- (if (S = 0) then 10 else 11) } else if (LDSTUBA) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (i = 1) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - address <- r[rs1] + r[rs2]; - addr_space <- asi - ) + if (S = 0) then ( + trap <- 1; + privileged_instruction <- 1 + ) else if (i = 1) then ( + trap <- 1; + illegal_instruction <- 1 + ) else ( + address <- r[rs1] + r[rs2]; + addr_space <- asi + ) ); next; if (trap = 0) then ( - while ( (pb_block_ldst_byte = 1) or (pb_block_ldst_word = 1) ) then ( - { wait for lock(s) to be lifted } - { an implementation actually need only block when another LDSTUB or SWAP - is pending on the same byte in memory as the one addressed by this LDSTUB } - }; - next; - pb_block_ldst_byte <- 1; - next; - (data, MAE) <- memory_read(addr_space, address); - next; - if (MAE = 1) then ( - trap <- 1; - data_access_exception <- 1 - ) + while ( (pb_block_ldst_byte = 1) or (pb_block_ldst_word = 1) ) then ( + { wait for lock(s) to be lifted } + { an implementation actually need only block when another LDSTUB or SWAP + is pending on the same byte in memory as the one addressed by this LDSTUB } + }; + next; + pb_block_ldst_byte <- 1; + next; + (data, MAE) <- memory_read(addr_space, address); + next; + if (MAE = 1) then ( + trap <- 1; + data_access_exception <- 1 + ) ) next; if (trap = 0) then ( - if (address<1:0> = 0) then ( byte_mask <- 1000 ) - else if (address<1:0> = 1) then ( byte_mask <- 0100 ) - else if (address<1:0> = 2) then ( byte_mask <- 0010 ) - else if (address<1:0> = 3) then ( byte_mask <- 0001 ) - ; - next; - MAE <- memory_write(addr_space, address, byte_mask, FFFFFFFF); - next; - pb_block_ldst_byte <- 0; - if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } - trap <- 1; - data_access_exception <- 1 - ) else ( - if (address<1:0> = 0) then word <- zero_extend_byte(data<31:24>) - else if (address<1:0> = 1) then word <- zero_extend_byte(data<23:24>) - else if (address<1:0> = 2) then word <- zero_extend_byte(data<15: 8>) - else if (address<1:0> = 3) then word <- zero_extend_byte(data< 7: 0>) - next; - if (rd != 0) then r[rd] <- word - ) + if (address<1:0> = 0) then ( byte_mask <- 1000 ) + else if (address<1:0> = 1) then ( byte_mask <- 0100 ) + else if (address<1:0> = 2) then ( byte_mask <- 0010 ) + else if (address<1:0> = 3) then ( byte_mask <- 0001 ) + ; + next; + MAE <- memory_write(addr_space, address, byte_mask, FFFFFFFF); + next; + pb_block_ldst_byte <- 0; + if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } + trap <- 1; + data_access_exception <- 1 + ) else ( + if (address<1:0> = 0) then word <- zero_extend_byte(data<31:24>) + else if (address<1:0> = 1) then word <- zero_extend_byte(data<23:24>) + else if (address<1:0> = 2) then word <- zero_extend_byte(data<15: 8>) + else if (address<1:0> = 3) then word <- zero_extend_byte(data< 7: 0>) + next; + if (rd != 0) then r[rd] <- word + ) ); */ @@ -2258,16 +2258,16 @@ bool mb86901_device::evaluate_condition(UINT32 op) bool v = ICC_V_SET; bool c = ICC_C_SET; - switch(COND & 7) // COND & 8 - { // 0 8 - case 0: take = false; break; // bn ba - case 1: take = z; break; // bz bne - case 2: take = z | (n ^ z); break; // ble bg - case 3: take = n ^ v; break; // bl bge - case 4: take = c | z; break; // bleu bgu - case 5: take = c; break; // bcs bcc - case 6: take = n; break; // bneg bpos - case 7: take = v; break; // bvs bvc + switch(COND & 7) // COND & 8 + { // 0 8 + case 0: take = false; break; // bn ba + case 1: take = z; break; // bz bne + case 2: take = z | (n ^ z); break; // ble bg + case 3: take = n ^ v; break; // bl bge + case 4: take = c | z; break; // bleu bgu + case 5: take = c; break; // bcs bcc + case 6: take = n; break; // bneg bpos + case 7: take = v; break; // bvs bvc } if (COND & 8) @@ -2286,32 +2286,32 @@ void mb86901_device::execute_bicc(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 178, "Appendix C - ISP Descriptions - Branch on Integer Condition Instructions" (SPARCv8.pdf, pg. 175) eval_icc := ( - if (BNE) then (if (Z = 0) then 1 else 0); - if (BE) then (if (Z = 1) then 1 else 0); - if (BG) then (if ((Z or (N xor V)) = 0) then 1 else 0); - if (BLE) then (if ((Z or (N xor V)) = 1) then 1 else 0); - if (BGE) then (if ((N xor V) = 0) then 1 else 0); - if (BL) then (if ((N xor V) = 1) then 1 else 0); - if (BGU) then (if ((C = 0) and (Z = 0)) then 1 else 0); - if (BLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0); - if (BCC) then (if (C = 0) then 1 else 0); - if (BCS) then (if (C = 1) then 1 else 0); - if (BPOS) then (if (N = 0) then 1 else 0); - if (BNEG) then (if (N = 1) then 1 else 0); - if (BVC) then (if (V = 0) then 1 else 0); - if (BVS) then (if (V = 1) then 1 else 0); - if (BA) then 1; - if (BN) then 0; + if (BNE) then (if (Z = 0) then 1 else 0); + if (BE) then (if (Z = 1) then 1 else 0); + if (BG) then (if ((Z or (N xor V)) = 0) then 1 else 0); + if (BLE) then (if ((Z or (N xor V)) = 1) then 1 else 0); + if (BGE) then (if ((N xor V) = 0) then 1 else 0); + if (BL) then (if ((N xor V) = 1) then 1 else 0); + if (BGU) then (if ((C = 0) and (Z = 0)) then 1 else 0); + if (BLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0); + if (BCC) then (if (C = 0) then 1 else 0); + if (BCS) then (if (C = 1) then 1 else 0); + if (BPOS) then (if (N = 0) then 1 else 0); + if (BNEG) then (if (N = 1) then 1 else 0); + if (BVC) then (if (V = 0) then 1 else 0); + if (BVS) then (if (V = 1) then 1 else 0); + if (BA) then 1; + if (BN) then 0; ) PC <- nPC; if (eval_icc = 1) then ( - nPC <- PC + sign_extend(disp22[]00); - if (BA and (a = 1)) then - annul <- 1 { only for annulling Branch-Always } + nPC <- PC + sign_extend(disp22[]00); + if (BA and (a = 1)) then + annul <- 1 { only for annulling Branch-Always } ) else ( - nPC <- nPC + 4; - if (a = 1) then - annul <- 1 { only for annulling branches other than BA } + nPC <- nPC + 4; + if (a = 1) then + annul <- 1 { only for annulling branches other than BA } ) */ @@ -2342,35 +2342,35 @@ void mb86901_device::execute_ticc(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 182, "Appendix C - ISP Descriptions - Trap on Integer Condition Instructions" (SPARCv8.pdf, pg. 179) trap_eval_icc := ( - if (TNE) then (if (Z = 0) then 1 else 0); - if (TE) then (if (Z = 1) then 1 else 0); - if (TG) then (if ((Z or (N xor V)) = 0) then 1 else 0); - if (TLE) then (if ((Z or (N xor V)) = 1) then 1 else 0); - if (TGE) then (if ((N xor V) = 0) then 1 else 0); - if (TL) then (if ((N xor V) = 1) then 1 else 0); - if (TGU) then (if ((C = 0) and (Z = 0)) then 1 else 0); - if (TLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0); - if (TCC) then (if (C = 0) then 1 else 0); - if (TCS) then (if (C = 1) then 1 else 0); - if (TPOS) then (if (N = 0) then 1 else 0); - if (TNEG) then (if (N = 1) then 1 else 0); - if (TVC) then (if (V = 0) then 1 else 0); - if (TVS) then (if (V = 1) then 1 else 0); - if (TA) then 1; - if (TN) then 0; + if (TNE) then (if (Z = 0) then 1 else 0); + if (TE) then (if (Z = 1) then 1 else 0); + if (TG) then (if ((Z or (N xor V)) = 0) then 1 else 0); + if (TLE) then (if ((Z or (N xor V)) = 1) then 1 else 0); + if (TGE) then (if ((N xor V) = 0) then 1 else 0); + if (TL) then (if ((N xor V) = 1) then 1 else 0); + if (TGU) then (if ((C = 0) and (Z = 0)) then 1 else 0); + if (TLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0); + if (TCC) then (if (C = 0) then 1 else 0); + if (TCS) then (if (C = 1) then 1 else 0); + if (TPOS) then (if (N = 0) then 1 else 0); + if (TNEG) then (if (N = 1) then 1 else 0); + if (TVC) then (if (V = 0) then 1 else 0); + if (TVS) then (if (V = 1) then 1 else 0); + if (TA) then 1; + if (TN) then 0; ) trap_number := r[rs1] + (if (i = 0) then r[rs2] else sign_extend(software_trap#)); if (Ticc) then ( - if (trap_eval_icc = 1) then ( - trap <- 1; - trap_instruction <- 1; - ticc_trap_type <- trap_number<6:0> - ) else ( - PC <- nPC; - nPC <- nPC + 4; - ) + if (trap_eval_icc = 1) then ( + trap <- 1; + trap_instruction <- 1; + ticc_trap_type <- trap_number<6:0> + ) else ( + PC <- nPC; + nPC <- nPC + 4; + ) ); */ @@ -2489,76 +2489,76 @@ void mb86901_device::execute_trap() next; if (error_mode = 0) then ( - ET <- 0; - PS <- S; - CWP <- (CWP - 1) modulo NWINDOWS; - - next; - if (annul = 0) then ( - r[17] <- PC; - r[18] <- nPC; - ) else { annul != 0) } ( - r[17] <- nPC; - r[18] <- nPC + 4; - annul <- 0; - ) - - next; - S <- 1; - if (reset_trap = 0) then ( - PC <- TBR; - nPC <- TBR + 4; - ) else { reset_trap = 1 } ( - PC <- 0; - nPC <- 4; - reset_trap <- 0; - ) + ET <- 0; + PS <- S; + CWP <- (CWP - 1) modulo NWINDOWS; + + next; + if (annul = 0) then ( + r[17] <- PC; + r[18] <- nPC; + ) else { annul != 0) } ( + r[17] <- nPC; + r[18] <- nPC + 4; + annul <- 0; + ) + + next; + S <- 1; + if (reset_trap = 0) then ( + PC <- TBR; + nPC <- TBR + 4; + ) else { reset_trap = 1 } ( + PC <- 0; + nPC <- 4; + reset_trap <- 0; + ) ); select_trap := ( - if (reset_trap = 1) then { ignore ET, and leave tt unchanged } - else if (ET = 0) then ( - execute_mode <- 0; - error_mode <- 1 ) - else if (data_store_error = 1) then tt <- 00101011 - else if (instruction_access_error = 1) then tt <- 00100001 - else if (r_register_access_error = 1) then tt <- 00100000 - else if (instruction_access_exception = 1) then tt <- 00000001 - else if (privileged_instruction = 1) then tt <- 00000011 - else if (illegal_instruction = 1) then tt <- 00000010 - else if (fp_disabled = 1) then tt <- 00000100 - else if (cp_disabled = 1) then tt <- 00100100 - else if (unimplemented_FLUSH = 1) then tt <- 00100101 - else if (window_overflow = 1) then tt <- 00000101 - else if (window_underflow = 1) then tt <- 00000110 - else if (mem_address_not_aligned = 1) then tt <- 00000111 - else if (fp_exception = 1) then tt <- 00001000 - else if (cp_exception = 1) then tt <- 00101000 - else if (data_access_error = 1) then tt <- 00101001 - else if (data_access_exception = 1) then tt <- 00001001 - else if (tag_overflow = 1) then tt <- 00001010 - else if (division_by_zero = 1) then tt <- 00101010 - else if (trap_instruction = 1) then tt <- 1[]ticc_trap_type - else if (interrupt_level > 0) then tt <- 0001[]interrupt_level; - - next; - - trap <- 0; - instruction_access_exception <- 0; - illegal_instruction <- 0; - privileged_instruction <- 0; - fp_disabled <- 0; - cp_disabled <- 0; - window_overflow <- 0; - window_underflow <- 0; - mem_address_not_aligned <- 0; - fp_exception <- 0; - cp_exception <- 0; - data_access_exception <- 0; - tag_overflow <- 0; - division_by_zero <- 0; - trap_instruction <- 0; - interrupt_level <- 0; + if (reset_trap = 1) then { ignore ET, and leave tt unchanged } + else if (ET = 0) then ( + execute_mode <- 0; + error_mode <- 1 ) + else if (data_store_error = 1) then tt <- 00101011 + else if (instruction_access_error = 1) then tt <- 00100001 + else if (r_register_access_error = 1) then tt <- 00100000 + else if (instruction_access_exception = 1) then tt <- 00000001 + else if (privileged_instruction = 1) then tt <- 00000011 + else if (illegal_instruction = 1) then tt <- 00000010 + else if (fp_disabled = 1) then tt <- 00000100 + else if (cp_disabled = 1) then tt <- 00100100 + else if (unimplemented_FLUSH = 1) then tt <- 00100101 + else if (window_overflow = 1) then tt <- 00000101 + else if (window_underflow = 1) then tt <- 00000110 + else if (mem_address_not_aligned = 1) then tt <- 00000111 + else if (fp_exception = 1) then tt <- 00001000 + else if (cp_exception = 1) then tt <- 00101000 + else if (data_access_error = 1) then tt <- 00101001 + else if (data_access_exception = 1) then tt <- 00001001 + else if (tag_overflow = 1) then tt <- 00001010 + else if (division_by_zero = 1) then tt <- 00101010 + else if (trap_instruction = 1) then tt <- 1[]ticc_trap_type + else if (interrupt_level > 0) then tt <- 0001[]interrupt_level; + + next; + + trap <- 0; + instruction_access_exception <- 0; + illegal_instruction <- 0; + privileged_instruction <- 0; + fp_disabled <- 0; + cp_disabled <- 0; + window_overflow <- 0; + window_underflow <- 0; + mem_address_not_aligned <- 0; + fp_exception <- 0; + cp_exception <- 0; + data_access_exception <- 0; + tag_overflow <- 0; + division_by_zero <- 0; + trap_instruction <- 0; + interrupt_level <- 0; ); */ @@ -2615,7 +2615,7 @@ void mb86901_device::complete_instruction_execution(UINT32 op) { switch (OP) { - case OP_TYPE0: // Bicc, SETHI, FBfcc + case OP_TYPE0: // Bicc, SETHI, FBfcc switch (OP2) { case OP2_UNIMP: // unimp @@ -2624,7 +2624,7 @@ void mb86901_device::complete_instruction_execution(UINT32 op) case OP2_BICC: // branch on integer condition codes execute_bicc(op); break; - case OP2_SETHI: // sethi + case OP2_SETHI: // sethi SET_RDREG(IMM22); break; case OP2_FBFCC: // branch on floating-point condition codes @@ -2674,26 +2674,26 @@ void mb86901_device::dispatch_instruction(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 159, "Appendix C - ISP Descriptions - C.6. Instruction Dispatch" (SPARCv8.pdf, pg. 156) illegal_IU_instr :- ( - if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction } - or + if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction } + or ( ((op=11) or (op=10)) and (op3=unassigned) ) - then 1 else 0 + then 1 else 0 if (illegal_IU_instr = 1) then ( - trap <- 1 - illegal_instruction <- 1 + trap <- 1 + illegal_instruction <- 1 ); if ((FPop1 or FPop2 or FBfcc) and ((EF = 0) or (bp_FPU_present = 0))) then ( - trap <- 1; - fp_disabled <- 1 + trap <- 1; + fp_disabled <- 1 ); if (CPop1 or CPop2 or CBccc) and ((EC = 0) or (bp_CP_present = 0))) then ( - trap <- 1; - cp_disabled <- 1 + trap <- 1; + cp_disabled <- 1 ); next; if (trap = 0) then ( - { code for specific instruction, defined below } + { code for specific instruction, defined below } ); */ bool illegal_IU_instr = (OP == 0 && OP2 == 0) || ((OP == 3 && !m_ldst_op3_assigned[OP3]) || (OP == 2 && !m_alu_op3_assigned[OP3])); @@ -2742,12 +2742,12 @@ void mb86901_device::execute_step() /* The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153) if (bp_reset_in = 1) then ( - execute_mode <- 0; - reset_mode <- 1; - break { out of while (execute_mode = 1) loop } + execute_mode <- 0; + reset_mode <- 1; + break { out of while (execute_mode = 1) loop } ) else if ((ET = 1) and ((bp_IRL = 15) or (bp_IRL > PIL))) then ( - trap <- 1; - interrupt_level <- bp_IRL + trap <- 1; + interrupt_level <- bp_IRL ); next; @@ -2755,40 +2755,40 @@ void mb86901_device::execute_step() if (execute_mode = 1) then ( { execute_trap may have set execute_mode to 0 } - { the following code emulates the delayed nature of the write-state-register instructions. - PSR <- PSR'; PSR' <- PSR''; PSR'' <- PSR'''; PSR''' <- PSR''''; - ASR <- ASR'; ASR' <- ASR''; ASR'' <- ASR'''; ASR''' <- ASR''''; - TBR <- TBR'; TBR' <- TBR''; TBR'' <- TBR'''; TBR''' <- TBR''''; - WIM <- WIM'; WIM' <- WIM''; WIM'' <- WIM'''; WIM''' <- WIM''''; - Y <- Y'; Y' <- Y''; Y'' <- Y'''; Y''' <- Y''''; - next; - - addr_space := (if (S = 0) then 8 else 9); - (instruction, MAE) <- memory_read(addr_space, PC); - next; - - if ( (MAE = 1) and (annul = 0) ) then ( - trap <- 1; - instruction_access_exception <- 1 - ) else ( - if (annul = 0) then ( - dispatch_instruction ; { See Section C.6 } - next; - if (FPop1 or FPop2) then ( - complete_fp_execution { See Section C.7 } - ) - next; - if ( (trap = 0) and - not (CALL or RETT or JMPL or Bicc or FBfcc or CBccc or Ticc) ) then ( - PC <- nPC; - nPC <- nPC + 4 - ) - ) else { annul != 0 } ( - annul <- 0; - PC <- nPC; - nPC <- nPC + 4 - ) - ) + { the following code emulates the delayed nature of the write-state-register instructions. + PSR <- PSR'; PSR' <- PSR''; PSR'' <- PSR'''; PSR''' <- PSR''''; + ASR <- ASR'; ASR' <- ASR''; ASR'' <- ASR'''; ASR''' <- ASR''''; + TBR <- TBR'; TBR' <- TBR''; TBR'' <- TBR'''; TBR''' <- TBR''''; + WIM <- WIM'; WIM' <- WIM''; WIM'' <- WIM'''; WIM''' <- WIM''''; + Y <- Y'; Y' <- Y''; Y'' <- Y'''; Y''' <- Y''''; + next; + + addr_space := (if (S = 0) then 8 else 9); + (instruction, MAE) <- memory_read(addr_space, PC); + next; + + if ( (MAE = 1) and (annul = 0) ) then ( + trap <- 1; + instruction_access_exception <- 1 + ) else ( + if (annul = 0) then ( + dispatch_instruction ; { See Section C.6 } + next; + if (FPop1 or FPop2) then ( + complete_fp_execution { See Section C.7 } + ) + next; + if ( (trap = 0) and + not (CALL or RETT or JMPL or Bicc or FBfcc or CBccc or Ticc) ) then ( + PC <- nPC; + nPC <- nPC + 4 + ) + ) else { annul != 0 } ( + annul <- 0; + PC <- nPC; + nPC <- nPC + 4 + ) + ) ) */ if (m_bp_reset_in) @@ -2898,7 +2898,7 @@ void mb86901_device::execute_step() printf("Opcode at %08x: %04x, handler is at %08x // add 32-bit word (%08x) from handler table to result (%08x + %08x = %08x)\n", REG(5), opcode, handler_offset, value, REG(4), value, REG(4) + value); } else if (opcode == 0x003f || opcode == 0x0066 || opcode == 0x0099 || opcode == 0x0121 || opcode == 0x0136 || opcode == 0x014f || opcode == 0x0155 || opcode == 0x01c7 || opcode == 0x01cd || - opcode == 0x0217 || opcode == 0x0289 || opcode == 0x0296 || opcode == 0x029d || opcode == 0x02f2 || opcode == 0x0334 || opcode == 0x0381 || opcode == 0x3d38) + opcode == 0x0217 || opcode == 0x0289 || opcode == 0x0296 || opcode == 0x029d || opcode == 0x02f2 || opcode == 0x0334 || opcode == 0x0381 || opcode == 0x3d38) { switch(opcode) { @@ -3093,7 +3093,6 @@ void mb86901_device::execute_step() } else { - m_annul = 0; PC = nPC; nPC = nPC + 4; @@ -3112,12 +3111,12 @@ void mb86901_device::reset_step() /* The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153) while (reset_mode = 1) ( - if (bp_reset_in = 0) then ( - reset_mode <- 0; - execute_mode <- 1; - trap <- 1; - reset_trap <- 1; - ) + if (bp_reset_in = 0) then ( + reset_mode <- 0; + execute_mode <- 1; + trap <- 1; + reset_trap <- 1; + ) ); */ @@ -3140,11 +3139,11 @@ void mb86901_device::error_step() /* The SPARC Instruction Manual: Version 8, page 157, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 154) while (error_mode = 1) ( - if (bp_reset_in = 1) then ( - error_mode <- 0; - reset_mode <- 1; - pb_error <- 0 - ) + if (bp_reset_in = 1) then ( + error_mode <- 0; + reset_mode <- 1; + pb_error <- 0 + ) ); */ @@ -3193,9 +3192,9 @@ void mb86901_device::execute_run() { for (int i = 0; i < 8; i++) { - m_dbgregs[i] = *m_regs[8 + i]; - m_dbgregs[8 + i] = *m_regs[16 + i]; - m_dbgregs[16 + i] = *m_regs[24 + i]; + m_dbgregs[i] = *m_regs[8 + i]; + m_dbgregs[8 + i] = *m_regs[16 + i]; + m_dbgregs[16 + i] = *m_regs[24 + i]; } } --m_icount; diff --git a/src/devices/cpu/sparc/sparc.h b/src/devices/cpu/sparc/sparc.h index da2d0bc7c82..1acc2263854 100644 --- a/src/devices/cpu/sparc/sparc.h +++ b/src/devices/cpu/sparc/sparc.h @@ -11,36 +11,36 @@ #include "sparcdasm.h" -#define SPARCV8 (0) - -#define SPARC_NO_TRAP 256 -#define SPARC_RESET 0 -#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1 -#define SPARC_ILLEGAL_INSTRUCTION 2 -#define SPARC_PRIVILEGED_INSTRUCTION 3 -#define SPARC_FP_DISABLED 4 -#define SPARC_WINDOW_OVERFLOW 5 -#define SPARC_WINDOW_UNDERFLOW 6 -#define SPARC_MEM_ADDRESS_NOT_ALIGNED 7 -#define SPARC_FLOATING_POINT_EXCEPTION 8 -#define SPARC_DATA_ACCESS_EXCEPTION 9 -#define SPARC_TAG_OVERFLOW 10 -#define SPARC_INT1 17 -#define SPARC_INT2 18 -#define SPARC_INT3 19 -#define SPARC_INT4 20 -#define SPARC_INT5 21 -#define SPARC_INT6 22 -#define SPARC_INT7 23 -#define SPARC_INT8 24 -#define SPARC_INT9 25 -#define SPARC_INT10 26 -#define SPARC_INT11 27 -#define SPARC_INT12 28 -#define SPARC_INT13 29 -#define SPARC_INT14 30 -#define SPARC_INT15 31 -#define SPARC_TRAP_INSTRUCTION 128 +#define SPARCV8 (0) + +#define SPARC_NO_TRAP 256 +#define SPARC_RESET 0 +#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1 +#define SPARC_ILLEGAL_INSTRUCTION 2 +#define SPARC_PRIVILEGED_INSTRUCTION 3 +#define SPARC_FP_DISABLED 4 +#define SPARC_WINDOW_OVERFLOW 5 +#define SPARC_WINDOW_UNDERFLOW 6 +#define SPARC_MEM_ADDRESS_NOT_ALIGNED 7 +#define SPARC_FLOATING_POINT_EXCEPTION 8 +#define SPARC_DATA_ACCESS_EXCEPTION 9 +#define SPARC_TAG_OVERFLOW 10 +#define SPARC_INT1 17 +#define SPARC_INT2 18 +#define SPARC_INT3 19 +#define SPARC_INT4 20 +#define SPARC_INT5 21 +#define SPARC_INT6 22 +#define SPARC_INT7 23 +#define SPARC_INT8 24 +#define SPARC_INT9 25 +#define SPARC_INT10 26 +#define SPARC_INT11 27 +#define SPARC_INT12 28 +#define SPARC_INT13 29 +#define SPARC_INT14 30 +#define SPARC_INT15 31 +#define SPARC_TRAP_INSTRUCTION 128 #define SPARC_FPU_SEQUENCE_ERROR // TODO: when there are more SPARC CPUs, move setter to a base class @@ -200,16 +200,16 @@ protected: UINT8 m_cp_sequence_err; // fields separated out from PSR (Processor State Register) - UINT8 m_impl; // implementation (always 0 in MB86901) - UINT8 m_ver; // version (always 0 in MB86901) - UINT8 m_icc; // integer condition codes - bool m_ec; // enable coprocessor - bool m_ef; // enable FPU - UINT8 m_pil; // processor interrupt level - bool m_s; // supervisor mode - bool m_ps; // prior S state - bool m_et; // enable traps - UINT8 m_cwp; // current window pointer + UINT8 m_impl; // implementation (always 0 in MB86901) + UINT8 m_ver; // version (always 0 in MB86901) + UINT8 m_icc; // integer condition codes + bool m_ec; // enable coprocessor + bool m_ef; // enable FPU + UINT8 m_pil; // processor interrupt level + bool m_s; // supervisor mode + bool m_ps; // prior S state + bool m_et; // enable traps + UINT8 m_cwp; // current window pointer bool m_alu_op3_assigned[64]; bool m_ldst_op3_assigned[64]; @@ -259,10 +259,10 @@ enum SPARC_ICC, SPARC_CWP, - SPARC_G0, SPARC_G1, SPARC_G2, SPARC_G3, SPARC_G4, SPARC_G5, SPARC_G6, SPARC_G7, - SPARC_O0, SPARC_O1, SPARC_O2, SPARC_O3, SPARC_O4, SPARC_O5, SPARC_O6, SPARC_O7, - SPARC_L0, SPARC_L1, SPARC_L2, SPARC_L3, SPARC_L4, SPARC_L5, SPARC_L6, SPARC_L7, - SPARC_I0, SPARC_I1, SPARC_I2, SPARC_I3, SPARC_I4, SPARC_I5, SPARC_I6, SPARC_I7, + SPARC_G0, SPARC_G1, SPARC_G2, SPARC_G3, SPARC_G4, SPARC_G5, SPARC_G6, SPARC_G7, + SPARC_O0, SPARC_O1, SPARC_O2, SPARC_O3, SPARC_O4, SPARC_O5, SPARC_O6, SPARC_O7, + SPARC_L0, SPARC_L1, SPARC_L2, SPARC_L3, SPARC_L4, SPARC_L5, SPARC_L6, SPARC_L7, + SPARC_I0, SPARC_I1, SPARC_I2, SPARC_I3, SPARC_I4, SPARC_I5, SPARC_I6, SPARC_I7, SPARC_EC, SPARC_EF, @@ -271,13 +271,13 @@ enum SPARC_S, SPARC_PS, - SPARC_R0, SPARC_R1, SPARC_R2, SPARC_R3, SPARC_R4, SPARC_R5, SPARC_R6, SPARC_R7, SPARC_R8, SPARC_R9, SPARC_R10, SPARC_R11, SPARC_R12, SPARC_R13, SPARC_R14, SPARC_R15, - SPARC_R16, SPARC_R17, SPARC_R18, SPARC_R19, SPARC_R20, SPARC_R21, SPARC_R22, SPARC_R23, SPARC_R24, SPARC_R25, SPARC_R26, SPARC_R27, SPARC_R28, SPARC_R29, SPARC_R30, SPARC_R31, - SPARC_R32, SPARC_R33, SPARC_R34, SPARC_R35, SPARC_R36, SPARC_R37, SPARC_R38, SPARC_R39, SPARC_R40, SPARC_R41, SPARC_R42, SPARC_R43, SPARC_R44, SPARC_R45, SPARC_R46, SPARC_R47, - SPARC_R48, SPARC_R49, SPARC_R50, SPARC_R51, SPARC_R52, SPARC_R53, SPARC_R54, SPARC_R55, SPARC_R56, SPARC_R57, SPARC_R58, SPARC_R59, SPARC_R60, SPARC_R61, SPARC_R62, SPARC_R63, - SPARC_R64, SPARC_R65, SPARC_R66, SPARC_R67, SPARC_R68, SPARC_R69, SPARC_R70, SPARC_R71, SPARC_R72, SPARC_R73, SPARC_R74, SPARC_R75, SPARC_R76, SPARC_R77, SPARC_R78, SPARC_R79, - SPARC_R80, SPARC_R81, SPARC_R82, SPARC_R83, SPARC_R84, SPARC_R85, SPARC_R86, SPARC_R87, SPARC_R88, SPARC_R89, SPARC_R90, SPARC_R91, SPARC_R92, SPARC_R93, SPARC_R94, SPARC_R95, - SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111 + SPARC_R0, SPARC_R1, SPARC_R2, SPARC_R3, SPARC_R4, SPARC_R5, SPARC_R6, SPARC_R7, SPARC_R8, SPARC_R9, SPARC_R10, SPARC_R11, SPARC_R12, SPARC_R13, SPARC_R14, SPARC_R15, + SPARC_R16, SPARC_R17, SPARC_R18, SPARC_R19, SPARC_R20, SPARC_R21, SPARC_R22, SPARC_R23, SPARC_R24, SPARC_R25, SPARC_R26, SPARC_R27, SPARC_R28, SPARC_R29, SPARC_R30, SPARC_R31, + SPARC_R32, SPARC_R33, SPARC_R34, SPARC_R35, SPARC_R36, SPARC_R37, SPARC_R38, SPARC_R39, SPARC_R40, SPARC_R41, SPARC_R42, SPARC_R43, SPARC_R44, SPARC_R45, SPARC_R46, SPARC_R47, + SPARC_R48, SPARC_R49, SPARC_R50, SPARC_R51, SPARC_R52, SPARC_R53, SPARC_R54, SPARC_R55, SPARC_R56, SPARC_R57, SPARC_R58, SPARC_R59, SPARC_R60, SPARC_R61, SPARC_R62, SPARC_R63, + SPARC_R64, SPARC_R65, SPARC_R66, SPARC_R67, SPARC_R68, SPARC_R69, SPARC_R70, SPARC_R71, SPARC_R72, SPARC_R73, SPARC_R74, SPARC_R75, SPARC_R76, SPARC_R77, SPARC_R78, SPARC_R79, + SPARC_R80, SPARC_R81, SPARC_R82, SPARC_R83, SPARC_R84, SPARC_R85, SPARC_R86, SPARC_R87, SPARC_R88, SPARC_R89, SPARC_R90, SPARC_R91, SPARC_R92, SPARC_R93, SPARC_R94, SPARC_R95, + SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111 }; #endif /* __SPARC_H__ */ diff --git a/src/devices/cpu/sparc/sparcdefs.h b/src/devices/cpu/sparc/sparcdefs.h index 7fab760e06b..c59282ffa85 100644 --- a/src/devices/cpu/sparc/sparcdefs.h +++ b/src/devices/cpu/sparc/sparcdefs.h @@ -12,375 +12,375 @@ #ifndef __MB86901_DEFS_H__ #define __MB86901_DEFS_H__ -#define PSR_CWP_MASK 0x0000001f -#define PSR_ET_SHIFT 5 -#define PSR_ET_MASK 0x00000020 -#define PSR_PS_SHIFT 6 -#define PSR_PS_MASK 0x00000040 -#define PSR_S_SHIFT 7 -#define PSR_S_MASK 0x00000080 -#define PSR_PIL_SHIFT 8 -#define PSR_PIL_MASK 0x00000f00 -#define PSR_EF_SHIFT 12 -#define PSR_EF_MASK 0x00001000 -#define PSR_EC_SHIFT 13 -#define PSR_EC_MASK 0x00002000 -#define PSR_ICC_SHIFT 20 -#define PSR_RES_MASK 0x000fc000 -#define PSR_ICC_MASK 0x00f00000 -#define PSR_N_MASK 0x00800000 -#define PSR_Z_MASK 0x00400000 -#define PSR_V_MASK 0x00200000 -#define PSR_C_MASK 0x00100000 -#define PSR_VER_SHIFT 24 -#define PSR_VER_MASK 0x0f000000 -#define PSR_VER 0 -#define PSR_IMPL_SHIFT 28 -#define PSR_IMPL_MASK 0xf0000000 -#define PSR_IMPL 0 -#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK) - -#define ICC_N_SET (m_psr & PSR_N_MASK) -#define ICC_N (ICC_N_SET ? 1 : 0) -#define ICC_N_CLEAR (!ICC_N_SET) -#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0) -#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0) - -#define ICC_Z_SET (m_psr & PSR_Z_MASK) -#define ICC_Z (ICC_Z_SET ? 1 : 0) -#define ICC_Z_CLEAR (!ICC_Z_SET) -#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0) -#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0) - -#define ICC_V_SET (m_psr & PSR_V_MASK) -#define ICC_V (ICC_V_SET ? 1 : 0) -#define ICC_V_CLEAR (!ICC_V_SET) -#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0) -#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0) - -#define ICC_C_SET (m_psr & PSR_C_MASK) -#define ICC_C (ICC_C_SET ? 1 : 0) -#define ICC_C_CLEAR (!ICC_C_SET) -#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0) -#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0) - -#define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0) - -#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0) - -#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0) -#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0) -#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0) - -#define CWP m_cwp -#define S m_s -#define PS m_ps - -#define IS_SUPERVISOR (m_psr & PSR_S_MASK) -#define IS_USER (!IS_SUPERVISOR) - -#define TRAPS_ENABLED (m_psr & PSR_ET_MASK) -#define TRAPS_DISABLED (!TRAPS_ENABLED) - -#define PSR m_psr -#define WIM m_wim -#define TBR m_tbr - -#define OP (op >> 30) // gangnam style -#define OP2 ((op >> 22) & 7) -#define OP3 ((op >> 19) & 63) -#define OPF ((op >> 5) & 0x1ff) -#define OPC ((op >> 5) & 0x1ff) -#define OPFLOW ((op >> 5) & 0x3f) - -#define DISP30 (INT32(op << 2)) -#define DISP22 (INT32(op << 10) >> 8) -#define DISP19 (INT32(op << 13) >> 11) -#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14) -#define IMM22 (op << 10) +#define PSR_CWP_MASK 0x0000001f +#define PSR_ET_SHIFT 5 +#define PSR_ET_MASK 0x00000020 +#define PSR_PS_SHIFT 6 +#define PSR_PS_MASK 0x00000040 +#define PSR_S_SHIFT 7 +#define PSR_S_MASK 0x00000080 +#define PSR_PIL_SHIFT 8 +#define PSR_PIL_MASK 0x00000f00 +#define PSR_EF_SHIFT 12 +#define PSR_EF_MASK 0x00001000 +#define PSR_EC_SHIFT 13 +#define PSR_EC_MASK 0x00002000 +#define PSR_ICC_SHIFT 20 +#define PSR_RES_MASK 0x000fc000 +#define PSR_ICC_MASK 0x00f00000 +#define PSR_N_MASK 0x00800000 +#define PSR_Z_MASK 0x00400000 +#define PSR_V_MASK 0x00200000 +#define PSR_C_MASK 0x00100000 +#define PSR_VER_SHIFT 24 +#define PSR_VER_MASK 0x0f000000 +#define PSR_VER 0 +#define PSR_IMPL_SHIFT 28 +#define PSR_IMPL_MASK 0xf0000000 +#define PSR_IMPL 0 +#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK) + +#define ICC_N_SET (m_psr & PSR_N_MASK) +#define ICC_N (ICC_N_SET ? 1 : 0) +#define ICC_N_CLEAR (!ICC_N_SET) +#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0) +#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0) + +#define ICC_Z_SET (m_psr & PSR_Z_MASK) +#define ICC_Z (ICC_Z_SET ? 1 : 0) +#define ICC_Z_CLEAR (!ICC_Z_SET) +#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0) +#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0) + +#define ICC_V_SET (m_psr & PSR_V_MASK) +#define ICC_V (ICC_V_SET ? 1 : 0) +#define ICC_V_CLEAR (!ICC_V_SET) +#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0) +#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0) + +#define ICC_C_SET (m_psr & PSR_C_MASK) +#define ICC_C (ICC_C_SET ? 1 : 0) +#define ICC_C_CLEAR (!ICC_C_SET) +#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0) +#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0) + +#define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0) + +#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0) + +#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0) +#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0) +#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0) + +#define CWP m_cwp +#define S m_s +#define PS m_ps + +#define IS_SUPERVISOR (m_psr & PSR_S_MASK) +#define IS_USER (!IS_SUPERVISOR) + +#define TRAPS_ENABLED (m_psr & PSR_ET_MASK) +#define TRAPS_DISABLED (!TRAPS_ENABLED) + +#define PSR m_psr +#define WIM m_wim +#define TBR m_tbr + +#define OP (op >> 30) // gangnam style +#define OP2 ((op >> 22) & 7) +#define OP3 ((op >> 19) & 63) +#define OPF ((op >> 5) & 0x1ff) +#define OPC ((op >> 5) & 0x1ff) +#define OPFLOW ((op >> 5) & 0x3f) + +#define DISP30 (INT32(op << 2)) +#define DISP22 (INT32(op << 10) >> 8) +#define DISP19 (INT32(op << 13) >> 11) +#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14) +#define IMM22 (op << 10) #define CONST22 (op & 0x3fffff) -#define SIMM13 (INT32(op << 19) >> 19) -#define SIMM11 (INT32(op << 21) >> 21) -#define SIMM10 (INT32(op << 22) >> 22) -#define SIMM8 (INT32(op << 24) >> 24) -#define IMM7 (op & 0x7f) -#define SIMM7 (INT32(op << 25) >> 25) -#define SHCNT32 (op & 31) +#define SIMM13 (INT32(op << 19) >> 19) +#define SIMM11 (INT32(op << 21) >> 21) +#define SIMM10 (INT32(op << 22) >> 22) +#define SIMM8 (INT32(op << 24) >> 24) +#define IMM7 (op & 0x7f) +#define SIMM7 (INT32(op << 25) >> 25) +#define SHCNT32 (op & 31) #define SHCNT64 (op & 63) #define IAMODE (op & 0x7) -#define USEIMM ((op >> 13) & 1) -#define USEEXT ((op >> 12) & 1) - - -#define COND ((op >> 25) & 15) -#define RCOND ((op >> 10) & 7) -#define MOVCOND ((op >> 14) & 15) -#define PRED ((op >> 19) & 1) -#define ANNUL ((op >> 29) & 1) -#define BRCC ((op >> 20) & 3) -#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4)) -#define OPFCC ((op >> 11) & 7) -#define TCCCC ((op >> 11) & 3) -#define ASI ((op >> 5) & 255) -#define MMASK (op & 15) -#define CMASK ((op >> 4) & 7) - -#define RD ((op >> 25) & 31) -#define RS1 ((op >> 14) & 31) -#define RS2 (op & 31) - -#define FREG(x) m_fpr[(x)] -#define FDREG m_fpr[RD] -#define FSR m_fsr - -#define REG(x) *m_regs[(x)] -#define RDREG *m_regs[RD] -#define RS1REG *m_regs[RS1] -#define RS2REG *m_regs[RS2] -#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0) -#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG)) - -#define PC m_pc -#define nPC m_npc - -#define Y m_y - -#define ET m_et -#define EF m_ef -#define EC m_ec -#define PIL m_pil - -#define MAE m_mae -#define HOLD_BUS m_hold_bus - -#define BIT31(x) ((x) & 0x80000000) - -#define UPDATE_PC true -#define PC_UPDATED false - -#define OP_TYPE0 0 -#define OP_CALL 1 -#define OP_ALU 2 -#define OP_LDST 3 - -#define OP2_UNIMP 0 -#define OP2_BICC 2 -#define OP2_SETHI 4 -#define OP2_FBFCC 6 -#define OP2_CBCCC 7 - -#define OP3_ADD 0 -#define OP3_AND 1 -#define OP3_OR 2 -#define OP3_XOR 3 -#define OP3_SUB 4 -#define OP3_ANDN 5 -#define OP3_ORN 6 -#define OP3_XNOR 7 -#define OP3_ADDX 8 -#define OP3_UMUL 10 -#define OP3_SMUL 11 -#define OP3_SUBX 12 -#define OP3_UDIV 14 -#define OP3_SDIV 15 -#define OP3_ADDCC 16 -#define OP3_ANDCC 17 -#define OP3_ORCC 18 -#define OP3_XORCC 19 -#define OP3_SUBCC 20 -#define OP3_ANDNCC 21 -#define OP3_ORNCC 22 -#define OP3_XNORCC 23 -#define OP3_ADDXCC 24 -#define OP3_UMULCC 26 -#define OP3_SMULCC 27 -#define OP3_SUBXCC 28 -#define OP3_UDIVCC 30 -#define OP3_SDIVCC 31 -#define OP3_TADDCC 32 -#define OP3_TSUBCC 33 -#define OP3_TADDCCTV 34 -#define OP3_TSUBCCTV 35 -#define OP3_MULSCC 36 -#define OP3_SLL 37 -#define OP3_SRL 38 -#define OP3_SRA 39 -#define OP3_RDASR 40 -#define OP3_RDPSR 41 -#define OP3_RDWIM 42 -#define OP3_RDTBR 43 -#define OP3_WRASR 48 -#define OP3_WRPSR 49 -#define OP3_WRWIM 50 -#define OP3_WRTBR 51 -#define OP3_FPOP1 52 -#define OP3_FPOP2 53 -#define OP3_JMPL 56 -#define OP3_RETT 57 -#define OP3_TICC 58 -#define OP3_SAVE 60 -#define OP3_RESTORE 61 - -#define OP3_LD 0 -#define OP3_LDUB 1 -#define OP3_LDUH 2 -#define OP3_LDD 3 -#define OP3_ST 4 -#define OP3_STB 5 -#define OP3_STH 6 -#define OP3_STD 7 -#define OP3_LDSB 9 -#define OP3_LDSH 10 -#define OP3_LDSTUB 13 -#define OP3_SWAP 15 -#define OP3_LDA 16 -#define OP3_LDUBA 17 -#define OP3_LDUHA 18 -#define OP3_LDDA 19 -#define OP3_STA 20 -#define OP3_STBA 21 -#define OP3_STHA 22 -#define OP3_STDA 23 -#define OP3_LDSBA 25 -#define OP3_LDSHA 26 -#define OP3_LDSTUBA 29 -#define OP3_SWAPA 31 -#define OP3_LDFPR 32 -#define OP3_LDFSR 33 -#define OP3_LDDFPR 35 -#define OP3_STFPR 36 -#define OP3_STFSR 37 -#define OP3_STDFQ 38 -#define OP3_STDFPR 39 -#define OP3_LDCPR 40 -#define OP3_LDCSR 41 -#define OP3_LDDCPR 43 -#define OP3_STCPR 44 -#define OP3_STCSR 45 -#define OP3_STDCQ 46 -#define OP3_STDCPR 47 -#define OP3_CPOP1 54 -#define OP3_CPOP2 55 - -#define COND_BN 0 -#define COND_BE 1 -#define COND_BLE 2 -#define COND_BL 3 -#define COND_BLEU 4 -#define COND_BCS 5 -#define COND_BNEG 6 -#define COND_BVS 7 -#define COND_BA 8 -#define COND_BNE 9 -#define COND_BG 10 -#define COND_BGE 11 -#define COND_BGU 12 -#define COND_BCC 13 -#define COND_BPOS 14 -#define COND_BVC 15 - -#define LDD (OP3 == OP3_LDD) -#define LD (OP3 == OP3_LD) -#define LDSH (OP3 == OP3_LDSH) -#define LDUH (OP3 == OP3_LDUH) -#define LDSB (OP3 == OP3_LDSB) -#define LDUB (OP3 == OP3_LDUB) -#define LDDF (OP3 == OP3_LDDFPR) -#define LDF (OP3 == OP3_LDFPR) -#define LDFSR (OP3 == OP3_LDFSR) -#define LDDC (OP3 == OP3_LDDCPR) -#define LDC (OP3 == OP3_LDCPR) -#define LDCSR (OP3 == OP3_LDCSR) -#define LDDA (OP3 == OP3_LDDA) -#define LDA (OP3 == OP3_LDA) -#define LDSHA (OP3 == OP3_LDSHA) -#define LDUHA (OP3 == OP3_LDUHA) -#define LDSBA (OP3 == OP3_LDSBA) -#define LDUBA (OP3 == OP3_LDUBA) - -#define STD (OP3 == OP3_STD) -#define ST (OP3 == OP3_ST) -#define STH (OP3 == OP3_STH) -#define STB (OP3 == OP3_STB) -#define STDA (OP3 == OP3_STDA) -#define STA (OP3 == OP3_STA) -#define STHA (OP3 == OP3_STHA) -#define STBA (OP3 == OP3_STBA) -#define STF (OP3 == OP3_STFPR) -#define STFSR (OP3 == OP3_STFSR) -#define STDFQ (OP3 == OP3_STDFQ) -#define STDF (OP3 == OP3_STDFPR) -#define STC (OP3 == OP3_STCPR) -#define STCSR (OP3 == OP3_STCSR) -#define STDCQ (OP3 == OP3_STDCQ) -#define STDC (OP3 == OP3_STDCPR) - -#define JMPL (OP3 == OP3_JMPL) -#define TICC (OP3 == OP3_TICC) -#define RETT (OP3 == OP3_RETT) - -#define SWAP (OP3 == OP3_SWAP) -#define SWAPA (OP3 == OP3_SWAPA) - -#define FPOP1 (OP3 == OP3_FPOP1) -#define FPOP2 (OP3 == OP3_FPOP2) -#define CPOP1 (OP3 == OP3_CPOP1) -#define CPOP2 (OP3 == OP3_CPOP2) - -#define LDSTUB (OP3 == OP3_LDSTUB) -#define LDSTUBA (OP3 == OP3_LDSTUBA) - -#define ADD (OP3 == OP3_ADD) -#define ADDX (OP3 == OP3_ADDX) -#define ADDCC (OP3 == OP3_ADDCC) -#define ADDXCC (OP3 == OP3_ADDXCC) - -#define SUB (OP3 == OP3_SUB) -#define SUBX (OP3 == OP3_SUBX) -#define SUBCC (OP3 == OP3_SUBCC) -#define SUBXCC (OP3 == OP3_SUBXCC) - -#define TADDCCTV (OP3 == OP3_TADDCCTV) -#define TSUBCCTV (OP3 == OP3_TSUBCCTV) - -#define AND (OP3 == OP3_AND) -#define OR (OP3 == OP3_OR) -#define XOR (OP3 == OP3_XOR) -#define ANDN (OP3 == OP3_ANDN) -#define ORN (OP3 == OP3_ORN) -#define XNOR (OP3 == OP3_XNOR) -#define ANDCC (OP3 == OP3_ANDCC) -#define ORCC (OP3 == OP3_ORCC) -#define XORCC (OP3 == OP3_XORCC) -#define ANDNCC (OP3 == OP3_ANDNCC) -#define ORNCC (OP3 == OP3_ORNCC) -#define XNORCC (OP3 == OP3_XNORCC) - -#define SLL (OP3 == OP3_SLL) -#define SRL (OP3 == OP3_SRL) -#define SRA (OP3 == OP3_SRA) - -#define RDASR (OP3 == OP3_RDASR) -#define RDPSR (OP3 == OP3_RDPSR) -#define RDWIM (OP3 == OP3_RDWIM) -#define RDTBR (OP3 == OP3_RDTBR) - -#define WRASR (OP3 == OP3_WRASR) -#define WRPSR (OP3 == OP3_WRPSR) -#define WRWIM (OP3 == OP3_WRWIM) -#define WRTBR (OP3 == OP3_WRTBR) - -#define SAVE (OP3 == OP3_SAVE) -#define RESTORE (OP3 == OP3_RESTORE) - -#define UMUL (OP3 == OP3_UMUL) -#define UMULCC (OP3 == OP3_UMULCC) -#define SMUL (OP3 == OP3_SMUL) -#define SMULCC (OP3 == OP3_SMULCC) - -#define UDIV (OP3 == OP3_UDIV) -#define UDIVCC (OP3 == OP3_UDIVCC) -#define SDIV (OP3 == OP3_SDIV) -#define SDIVCC (OP3 == OP3_SDIVCC) - -#endif // __MB86901_DEFS_H__
\ No newline at end of file +#define USEIMM ((op >> 13) & 1) +#define USEEXT ((op >> 12) & 1) + + +#define COND ((op >> 25) & 15) +#define RCOND ((op >> 10) & 7) +#define MOVCOND ((op >> 14) & 15) +#define PRED ((op >> 19) & 1) +#define ANNUL ((op >> 29) & 1) +#define BRCC ((op >> 20) & 3) +#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4)) +#define OPFCC ((op >> 11) & 7) +#define TCCCC ((op >> 11) & 3) +#define ASI ((op >> 5) & 255) +#define MMASK (op & 15) +#define CMASK ((op >> 4) & 7) + +#define RD ((op >> 25) & 31) +#define RS1 ((op >> 14) & 31) +#define RS2 (op & 31) + +#define FREG(x) m_fpr[(x)] +#define FDREG m_fpr[RD] +#define FSR m_fsr + +#define REG(x) *m_regs[(x)] +#define RDREG *m_regs[RD] +#define RS1REG *m_regs[RS1] +#define RS2REG *m_regs[RS2] +#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0) +#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG)) + +#define PC m_pc +#define nPC m_npc + +#define Y m_y + +#define ET m_et +#define EF m_ef +#define EC m_ec +#define PIL m_pil + +#define MAE m_mae +#define HOLD_BUS m_hold_bus + +#define BIT31(x) ((x) & 0x80000000) + +#define UPDATE_PC true +#define PC_UPDATED false + +#define OP_TYPE0 0 +#define OP_CALL 1 +#define OP_ALU 2 +#define OP_LDST 3 + +#define OP2_UNIMP 0 +#define OP2_BICC 2 +#define OP2_SETHI 4 +#define OP2_FBFCC 6 +#define OP2_CBCCC 7 + +#define OP3_ADD 0 +#define OP3_AND 1 +#define OP3_OR 2 +#define OP3_XOR 3 +#define OP3_SUB 4 +#define OP3_ANDN 5 +#define OP3_ORN 6 +#define OP3_XNOR 7 +#define OP3_ADDX 8 +#define OP3_UMUL 10 +#define OP3_SMUL 11 +#define OP3_SUBX 12 +#define OP3_UDIV 14 +#define OP3_SDIV 15 +#define OP3_ADDCC 16 +#define OP3_ANDCC 17 +#define OP3_ORCC 18 +#define OP3_XORCC 19 +#define OP3_SUBCC 20 +#define OP3_ANDNCC 21 +#define OP3_ORNCC 22 +#define OP3_XNORCC 23 +#define OP3_ADDXCC 24 +#define OP3_UMULCC 26 +#define OP3_SMULCC 27 +#define OP3_SUBXCC 28 +#define OP3_UDIVCC 30 +#define OP3_SDIVCC 31 +#define OP3_TADDCC 32 +#define OP3_TSUBCC 33 +#define OP3_TADDCCTV 34 +#define OP3_TSUBCCTV 35 +#define OP3_MULSCC 36 +#define OP3_SLL 37 +#define OP3_SRL 38 +#define OP3_SRA 39 +#define OP3_RDASR 40 +#define OP3_RDPSR 41 +#define OP3_RDWIM 42 +#define OP3_RDTBR 43 +#define OP3_WRASR 48 +#define OP3_WRPSR 49 +#define OP3_WRWIM 50 +#define OP3_WRTBR 51 +#define OP3_FPOP1 52 +#define OP3_FPOP2 53 +#define OP3_JMPL 56 +#define OP3_RETT 57 +#define OP3_TICC 58 +#define OP3_SAVE 60 +#define OP3_RESTORE 61 + +#define OP3_LD 0 +#define OP3_LDUB 1 +#define OP3_LDUH 2 +#define OP3_LDD 3 +#define OP3_ST 4 +#define OP3_STB 5 +#define OP3_STH 6 +#define OP3_STD 7 +#define OP3_LDSB 9 +#define OP3_LDSH 10 +#define OP3_LDSTUB 13 +#define OP3_SWAP 15 +#define OP3_LDA 16 +#define OP3_LDUBA 17 +#define OP3_LDUHA 18 +#define OP3_LDDA 19 +#define OP3_STA 20 +#define OP3_STBA 21 +#define OP3_STHA 22 +#define OP3_STDA 23 +#define OP3_LDSBA 25 +#define OP3_LDSHA 26 +#define OP3_LDSTUBA 29 +#define OP3_SWAPA 31 +#define OP3_LDFPR 32 +#define OP3_LDFSR 33 +#define OP3_LDDFPR 35 +#define OP3_STFPR 36 +#define OP3_STFSR 37 +#define OP3_STDFQ 38 +#define OP3_STDFPR 39 +#define OP3_LDCPR 40 +#define OP3_LDCSR 41 +#define OP3_LDDCPR 43 +#define OP3_STCPR 44 +#define OP3_STCSR 45 +#define OP3_STDCQ 46 +#define OP3_STDCPR 47 +#define OP3_CPOP1 54 +#define OP3_CPOP2 55 + +#define COND_BN 0 +#define COND_BE 1 +#define COND_BLE 2 +#define COND_BL 3 +#define COND_BLEU 4 +#define COND_BCS 5 +#define COND_BNEG 6 +#define COND_BVS 7 +#define COND_BA 8 +#define COND_BNE 9 +#define COND_BG 10 +#define COND_BGE 11 +#define COND_BGU 12 +#define COND_BCC 13 +#define COND_BPOS 14 +#define COND_BVC 15 + +#define LDD (OP3 == OP3_LDD) +#define LD (OP3 == OP3_LD) +#define LDSH (OP3 == OP3_LDSH) +#define LDUH (OP3 == OP3_LDUH) +#define LDSB (OP3 == OP3_LDSB) +#define LDUB (OP3 == OP3_LDUB) +#define LDDF (OP3 == OP3_LDDFPR) +#define LDF (OP3 == OP3_LDFPR) +#define LDFSR (OP3 == OP3_LDFSR) +#define LDDC (OP3 == OP3_LDDCPR) +#define LDC (OP3 == OP3_LDCPR) +#define LDCSR (OP3 == OP3_LDCSR) +#define LDDA (OP3 == OP3_LDDA) +#define LDA (OP3 == OP3_LDA) +#define LDSHA (OP3 == OP3_LDSHA) +#define LDUHA (OP3 == OP3_LDUHA) +#define LDSBA (OP3 == OP3_LDSBA) +#define LDUBA (OP3 == OP3_LDUBA) + +#define STD (OP3 == OP3_STD) +#define ST (OP3 == OP3_ST) +#define STH (OP3 == OP3_STH) +#define STB (OP3 == OP3_STB) +#define STDA (OP3 == OP3_STDA) +#define STA (OP3 == OP3_STA) +#define STHA (OP3 == OP3_STHA) +#define STBA (OP3 == OP3_STBA) +#define STF (OP3 == OP3_STFPR) +#define STFSR (OP3 == OP3_STFSR) +#define STDFQ (OP3 == OP3_STDFQ) +#define STDF (OP3 == OP3_STDFPR) +#define STC (OP3 == OP3_STCPR) +#define STCSR (OP3 == OP3_STCSR) +#define STDCQ (OP3 == OP3_STDCQ) +#define STDC (OP3 == OP3_STDCPR) + +#define JMPL (OP3 == OP3_JMPL) +#define TICC (OP3 == OP3_TICC) +#define RETT (OP3 == OP3_RETT) + +#define SWAP (OP3 == OP3_SWAP) +#define SWAPA (OP3 == OP3_SWAPA) + +#define FPOP1 (OP3 == OP3_FPOP1) +#define FPOP2 (OP3 == OP3_FPOP2) +#define CPOP1 (OP3 == OP3_CPOP1) +#define CPOP2 (OP3 == OP3_CPOP2) + +#define LDSTUB (OP3 == OP3_LDSTUB) +#define LDSTUBA (OP3 == OP3_LDSTUBA) + +#define ADD (OP3 == OP3_ADD) +#define ADDX (OP3 == OP3_ADDX) +#define ADDCC (OP3 == OP3_ADDCC) +#define ADDXCC (OP3 == OP3_ADDXCC) + +#define SUB (OP3 == OP3_SUB) +#define SUBX (OP3 == OP3_SUBX) +#define SUBCC (OP3 == OP3_SUBCC) +#define SUBXCC (OP3 == OP3_SUBXCC) + +#define TADDCCTV (OP3 == OP3_TADDCCTV) +#define TSUBCCTV (OP3 == OP3_TSUBCCTV) + +#define AND (OP3 == OP3_AND) +#define OR (OP3 == OP3_OR) +#define XOR (OP3 == OP3_XOR) +#define ANDN (OP3 == OP3_ANDN) +#define ORN (OP3 == OP3_ORN) +#define XNOR (OP3 == OP3_XNOR) +#define ANDCC (OP3 == OP3_ANDCC) +#define ORCC (OP3 == OP3_ORCC) +#define XORCC (OP3 == OP3_XORCC) +#define ANDNCC (OP3 == OP3_ANDNCC) +#define ORNCC (OP3 == OP3_ORNCC) +#define XNORCC (OP3 == OP3_XNORCC) + +#define SLL (OP3 == OP3_SLL) +#define SRL (OP3 == OP3_SRL) +#define SRA (OP3 == OP3_SRA) + +#define RDASR (OP3 == OP3_RDASR) +#define RDPSR (OP3 == OP3_RDPSR) +#define RDWIM (OP3 == OP3_RDWIM) +#define RDTBR (OP3 == OP3_RDTBR) + +#define WRASR (OP3 == OP3_WRASR) +#define WRPSR (OP3 == OP3_WRPSR) +#define WRWIM (OP3 == OP3_WRWIM) +#define WRTBR (OP3 == OP3_WRTBR) + +#define SAVE (OP3 == OP3_SAVE) +#define RESTORE (OP3 == OP3_RESTORE) + +#define UMUL (OP3 == OP3_UMUL) +#define UMULCC (OP3 == OP3_UMULCC) +#define SMUL (OP3 == OP3_SMUL) +#define SMULCC (OP3 == OP3_SMULCC) + +#define UDIV (OP3 == OP3_UDIV) +#define UDIVCC (OP3 == OP3_UDIVCC) +#define SDIV (OP3 == OP3_SDIV) +#define SDIVCC (OP3 == OP3_SDIVCC) + +#endif // __MB86901_DEFS_H__ |