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Diffstat (limited to 'src/devices/cpu/sh4/sh4dmac.h')
-rw-r--r--src/devices/cpu/sh4/sh4dmac.h68
1 files changed, 34 insertions, 34 deletions
diff --git a/src/devices/cpu/sh4/sh4dmac.h b/src/devices/cpu/sh4/sh4dmac.h
index fe0bbc84514..b7918fac997 100644
--- a/src/devices/cpu/sh4/sh4dmac.h
+++ b/src/devices/cpu/sh4/sh4dmac.h
@@ -27,37 +27,37 @@
#define DMAOR_NMIF 0x0002
#define DMAOR_DME 0x0001
-void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask);
-void sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask);
-UINT32 sh4_handle_sar0_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_sar1_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_sar2_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_sar3_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_dar0_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_dar1_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_dar2_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_dar3_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_dmatcr0_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_dmatcr1_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_dmatcr2_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_dmatcr3_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_chcr0_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_chcr1_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_chcr2_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_chcr3_addr_r(UINT32 mem_mask);
-UINT32 sh4_handle_dmaor_addr_r(UINT32 mem_mask);
+void sh4_handle_sar0_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_sar1_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_sar2_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_sar3_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_dar0_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_dar1_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_dar2_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_dar3_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_dmatcr0_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_dmatcr1_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_dmatcr2_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_dmatcr3_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_chcr0_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_chcr1_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_chcr2_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_chcr3_addr_w(uint32_t data, uint32_t mem_mask);
+void sh4_handle_dmaor_addr_w(uint32_t data, uint32_t mem_mask);
+uint32_t sh4_handle_sar0_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_sar1_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_sar2_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_sar3_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_dar0_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_dar1_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_dar2_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_dar3_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_dmatcr0_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_dmatcr1_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_dmatcr2_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_dmatcr3_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_chcr0_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_chcr1_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_chcr2_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_chcr3_addr_r(uint32_t mem_mask);
+uint32_t sh4_handle_dmaor_addr_r(uint32_t mem_mask);