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-rw-r--r--src/devices/cpu/sh/sh_fe.cpp259
1 files changed, 129 insertions, 130 deletions
diff --git a/src/devices/cpu/sh/sh_fe.cpp b/src/devices/cpu/sh/sh_fe.cpp
index efee8bf506f..5e803b8ee00 100644
--- a/src/devices/cpu/sh/sh_fe.cpp
+++ b/src/devices/cpu/sh/sh_fe.cpp
@@ -2,7 +2,7 @@
// copyright-holders:David Haywood, R. Belmont
/***************************************************************************
- sh_fe.c
+ sh_fe.cpp
Front end for SH recompiler
@@ -10,7 +10,6 @@
#include "emu.h"
#include "sh2.h"
-#include "sh2comn.h"
#include "cpu/drcfe.h"
@@ -51,7 +50,7 @@ bool sh_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return describe_group_0(desc, prev, opcode);
case 1: // MOVLS4
- desc.regin[0] |= REGFLAG_R(Rn) | REGFLAG_R(Rm);
+ desc.regin[0] |= REGFLAG_R(REG_N) | REGFLAG_R(REG_M);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
@@ -65,8 +64,8 @@ bool sh_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return describe_group_4(desc, prev, opcode);
case 5: // MOVLL4
- desc.regin[0] |= REGFLAG_R(Rm);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
@@ -74,24 +73,24 @@ bool sh_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return describe_group_6(desc, prev, opcode);
case 7: // ADDI
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 8:
return describe_group_8(desc, prev, opcode);
case 9: // MOVWI
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 11: // BSR
desc.regout[1] |= REGFLAG_PR;
- // (intentional fallthrough - BSR is BRA with the addition of PR = the return address)
+ [[fallthrough]]; // BSR is BRA with the addition of PR = the return address
case 10: // BRA
{
- int32_t disp = ((int32_t)opcode << 20) >> 20;
+ int32_t disp = util::sext(opcode, 12);
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
desc.targetpc = (desc.pc + 2) + disp * 2 + 2;
@@ -104,12 +103,12 @@ bool sh_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return describe_group_12(desc, prev, opcode);
case 13: // MOVLI
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 14: // MOVI
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 15: // NOP
@@ -127,7 +126,7 @@ bool sh_frontend::describe_group_2(opcode_desc &desc, const opcode_desc *prev, u
case 0: // MOVBS(Rm, Rn);
case 1: // MOVWS(Rm, Rn);
case 2: // MOVLS(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
@@ -138,28 +137,28 @@ bool sh_frontend::describe_group_2(opcode_desc &desc, const opcode_desc *prev, u
case 5: // MOVWM(Rm, Rn);
case 6: // MOVLM(Rm, Rn);
case 13: // XTRCT(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 7: // DIV0S(Rm, Rn);
case 8: // TST(Rm, Rn);
case 12: // CMPSTR(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 9: // AND(Rm, Rn);
case 10: // XOR(Rm, Rn);
case 11: // OR(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 14: // MULU(Rm, Rn);
case 15: // MULS(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
desc.cycles = 2;
return true;
@@ -177,7 +176,7 @@ bool sh_frontend::describe_group_3(opcode_desc &desc, const opcode_desc *prev, u
case 3: // CMPGE(Rm, Rn);
case 6: // CMPHI(Rm, Rn);
case 7: // CMPGT(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
@@ -186,31 +185,31 @@ bool sh_frontend::describe_group_3(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 4: // DIV1(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 5: // DMULU(Rm, Rn);
case 13: // DMULS(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
desc.cycles = 2;
return true;
case 8: // SUB(Rm, Rn);
case 12: // ADD(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 10: // SUBC(Rm, Rn);
case 11: // SUBV(Rm, Rn);
case 14: // ADDC(Rm, Rn);
case 15: // ADDV(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_SR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
}
@@ -233,26 +232,26 @@ bool sh_frontend::describe_group_6(opcode_desc &desc, const opcode_desc *prev, u
case 13: // EXTUW(Rm, Rn);
case 14: // EXTSB(Rm, Rn);
case 15: // EXTSW(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 4: // MOVBP(Rm, Rn);
case 5: // MOVWP(Rm, Rn);
case 6: // MOVLP(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 8: // SWAPB(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 10: // NEGC(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
}
@@ -263,49 +262,49 @@ bool sh_frontend::describe_group_8(opcode_desc &desc, const opcode_desc *prev, u
{
int32_t disp;
- switch ( opcode & (15<<8) )
+ switch (opcode & (15 << 8))
{
case 0 << 8: // MOVBS4(opcode & 0x0f, Rm);
case 1 << 8: // MOVWS4(opcode & 0x0f, Rm);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(0);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(0);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
- case 2<< 8: // NOP();
- case 3<< 8: // NOP();
- case 6<< 8: // NOP();
- case 7<< 8: // NOP();
- case 10<< 8: // NOP();
- case 12<< 8: // NOP();
- case 14<< 8: // NOP();
+ case 2 << 8: // NOP();
+ case 3 << 8: // NOP();
+ case 6 << 8: // NOP();
+ case 7 << 8: // NOP();
+ case 10 << 8: // NOP();
+ case 12 << 8: // NOP();
+ case 14 << 8: // NOP();
return true;
- case 4<< 8: // MOVBL4(Rm, opcode & 0x0f);
- case 5<< 8: // MOVWL4(Rm, opcode & 0x0f);
- desc.regin[0] |= REGFLAG_R(Rm);
+ case 4 << 8: // MOVBL4(Rm, opcode & 0x0f);
+ case 5 << 8: // MOVWL4(Rm, opcode & 0x0f);
+ desc.regin[0] |= REGFLAG_R(REG_M);
desc.regout[0] |= REGFLAG_R(0);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
- case 8<< 8: // CMPIM(opcode & 0xff);
- desc.regin[0] |= REGFLAG_R(Rm);
+ case 8 << 8: // CMPIM(opcode & 0xff);
+ desc.regin[0] |= REGFLAG_R(REG_M);
desc.regin[1] |= REGFLAG_SR;
desc.regout[1] |= REGFLAG_SR;
return true;
- case 9<< 8: // BT(opcode & 0xff);
- case 11<< 8: // BF(opcode & 0xff);
+ case 9 << 8: // BT(opcode & 0xff);
+ case 11 << 8: // BF(opcode & 0xff);
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.cycles = 3;
- disp = ((int32_t)opcode << 24) >> 24;
+ disp = util::sext(opcode, 8);
desc.targetpc = (desc.pc + 2) + disp * 2 + 2;
return true;
- case 13<< 8: // BTS(opcode & 0xff);
- case 15<< 8: // BFS(opcode & 0xff);
+ case 13 << 8: // BTS(opcode & 0xff);
+ case 15 << 8: // BFS(opcode & 0xff);
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.cycles = 2;
- disp = ((int32_t)opcode << 24) >> 24;
+ disp = util::sext(opcode, 8);
desc.targetpc = (desc.pc + 2) + disp * 2 + 2;
desc.delayslots = 1;
return true;
@@ -318,14 +317,14 @@ bool sh_frontend::describe_group_12(opcode_desc &desc, const opcode_desc *prev,
{
switch (opcode & (15<<8))
{
- case 0<<8: // MOVBSG(opcode & 0xff);
- case 1<<8: // MOVWSG(opcode & 0xff);
- case 2<<8: // MOVLSG(opcode & 0xff);
+ case 0 << 8: // MOVBSG(opcode & 0xff);
+ case 1 << 8: // MOVWSG(opcode & 0xff);
+ case 2 << 8: // MOVLSG(opcode & 0xff);
desc.regin[0] |= REGFLAG_R(0);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
- case 3<<8: // TRAPA(opcode & 0xff);
+ case 3 << 8: // TRAPA(opcode & 0xff);
desc.regin[0] |= REGFLAG_R(15);
desc.regin[1] |= REGFLAG_VBR;
desc.regout[0] |= REGFLAG_R(15);
@@ -334,31 +333,31 @@ bool sh_frontend::describe_group_12(opcode_desc &desc, const opcode_desc *prev,
desc.flags |= OPFLAG_READS_MEMORY | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
return true;
- case 4<<8: // MOVBLG(opcode & 0xff);
- case 5<<8: // MOVWLG(opcode & 0xff);
- case 6<<8: // MOVLLG(opcode & 0xff);
- case 7<<8: // MOVA(opcode & 0xff);
+ case 4 << 8: // MOVBLG(opcode & 0xff);
+ case 5 << 8: // MOVWLG(opcode & 0xff);
+ case 6 << 8: // MOVLLG(opcode & 0xff);
+ case 7 << 8: // MOVA(opcode & 0xff);
desc.regout[0] |= REGFLAG_R(0);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
- case 8<<8: // TSTI(opcode & 0xff);
+ case 8 << 8: // TSTI(opcode & 0xff);
desc.regin[0] |= REGFLAG_R(0);
desc.regin[1] |= REGFLAG_SR;
desc.regout[1] |= REGFLAG_SR;
return true;
- case 9<<8: // ANDI(opcode & 0xff);
- case 10<<8: // XORI(opcode & 0xff);
- case 11<<8: // ORI(opcode & 0xff);
+ case 9 << 8: // ANDI(opcode & 0xff);
+ case 10 << 8: // XORI(opcode & 0xff);
+ case 11 << 8: // ORI(opcode & 0xff);
desc.regin[0] |= REGFLAG_R(0);
desc.regout[0] |= REGFLAG_R(0);
return true;
- case 12<<8: // TSTM(opcode & 0xff);
- case 13<<8: // ANDM(opcode & 0xff);
- case 14<<8: // XORM(opcode & 0xff);
- case 15<<8: // ORM(opcode & 0xff);
+ case 12 << 8: // TSTM(opcode & 0xff);
+ case 13 << 8: // ANDM(opcode & 0xff);
+ case 14 << 8: // XORM(opcode & 0xff);
+ case 15 << 8: // ORM(opcode & 0xff);
desc.regin[0] |= REGFLAG_R(0);
desc.regin[1] |= REGFLAG_SR | REGFLAG_GBR;
desc.regout[1] |= REGFLAG_SR;
@@ -394,7 +393,7 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 0x02: // STCSR(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 0x03: // BSRF(Rn);
@@ -418,7 +417,7 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x34: // MOVBS0(Rm, Rn);
case 0x35: // MOVWS0(Rm, Rn);
case 0x36: // MOVLS0(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn) | REGFLAG_R(0);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N) | REGFLAG_R(0);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
@@ -426,7 +425,7 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x17: // MULL(Rm, Rn);
case 0x27: // MULL(Rm, Rn);
case 0x37: // MULL(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rn) | REGFLAG_R(Rm);
+ desc.regin[0] |= REGFLAG_R(REG_N) | REGFLAG_R(REG_M);
desc.regout[1] |= REGFLAG_MACL;
desc.cycles = 2;
return true;
@@ -436,7 +435,7 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 0x0a: // STSMACH(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACH;
return true;
@@ -462,8 +461,8 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x3c: // MOVBL0(Rm, Rn);
case 0x3d: // MOVWL0(Rm, Rn);
case 0x3e: // MOVLL0(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(0);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(0);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
@@ -471,13 +470,13 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x1f: // MAC_L(Rm, Rn);
case 0x2f: // MAC_L(Rm, Rn);
case 0x3f: // MAC_L(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
desc.cycles = 3;
return true;
case 0x12: // STCGBR(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_GBR;
return true;
@@ -491,7 +490,7 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x1a: // STSMACL(Rn);
desc.regin[1] |= REGFLAG_MACL;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 0x1b: // SLEEP();
@@ -499,12 +498,12 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 0x22: // STCVBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_VBR;
return true;
case 0x23: // BRAF(Rn);
- desc.regin[0] |= REGFLAG_R(Rm);
+ desc.regin[0] |= REGFLAG_R(REG_M);
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
desc.targetpc = BRANCH_TARGET_DYNAMIC;
desc.delayslots = 1;
@@ -517,12 +516,12 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x29: // MOVT(Rn);
desc.regin[1] |= REGFLAG_SR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 0x2a: // STSPR(Rn);
desc.regin[1] |= REGFLAG_PR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 0x2b: // RTE();
@@ -549,35 +548,35 @@ bool sh_frontend::describe_group_4(opcode_desc &desc, const opcode_desc *prev, u
case 0x01: // SHLR(Rn);
case 0x04: // ROTL(Rn);
case 0x05: // ROTR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 0x02: // STSMMACH(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_MACH;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x03: // STCMSR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.cycles = 2;
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x06: // LDSMMACH(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACH;
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 0x07: // LDCMSR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
desc.cycles = 3;
desc.flags |= OPFLAG_READS_MEMORY | OPFLAG_CAN_EXPOSE_EXTERNAL_INT | OPFLAG_END_SEQUENCE;
@@ -589,17 +588,17 @@ bool sh_frontend::describe_group_4(opcode_desc &desc, const opcode_desc *prev, u
case 0x19: // SHLR8(Rn);
case 0x28: // SHLL16(Rn);
case 0x29: // SHLR16(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 0x0a: // LDSMACH(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACH;
return true;
case 0x0b: // JSR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_PR;
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
desc.targetpc = BRANCH_TARGET_DYNAMIC;
@@ -607,7 +606,7 @@ bool sh_frontend::describe_group_4(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 0x0e: // LDCSR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
desc.flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT | OPFLAG_END_SEQUENCE;
return true;
@@ -616,62 +615,62 @@ bool sh_frontend::describe_group_4(opcode_desc &desc, const opcode_desc *prev, u
case 0x1f: // MAC_W(Rm, Rn);
case 0x2f: // MAC_W(Rm, Rn);
case 0x3f: // MAC_W(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_MACL | REGFLAG_MACH;
- desc.regout[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
desc.cycles = 3;
return true;
case 0x10: // DT(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_SR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 0x11: // CMPPZ(Rn);
case 0x15: // CMPPL(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_SR;
desc.regout[1] |= REGFLAG_SR;
return true;
case 0x12: // STSMMACL(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_MACL;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x13: // STCMGBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_GBR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x16: // LDSMMACL(Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL;
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 0x17: // LDCMGBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_GBR;
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 0x1a: // LDSMACL(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL;
return true;
case 0x1b: // TAS(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_SR;
desc.regout[1] |= REGFLAG_SR;
desc.cycles = 4;
@@ -679,67 +678,67 @@ bool sh_frontend::describe_group_4(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 0x1e: // LDCGBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_GBR;
return true;
case 0x20: // SHAL(Rn);
case 0x21: // SHAR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 0x22: // STSMPR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_PR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x23: // STCMVBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_VBR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x24: // ROTCL(Rn);
case 0x25: // ROTCR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_SR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 0x26: // LDSMPR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_PR;
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 0x27: // LDCMVBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_VBR;
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 0x2a: // LDSPR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_PR;
return true;
case 0x2b: // JMP(Rm);
- desc.regin[0] |= REGFLAG_R(Rm);
+ desc.regin[0] |= REGFLAG_R(REG_M);
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
desc.targetpc = BRANCH_TARGET_DYNAMIC;
desc.delayslots = 1;
return true;
case 0x2e: // LDCVBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_VBR;
return true;