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Diffstat (limited to 'src/devices/cpu/powerpc/ppc.h')
-rw-r--r--src/devices/cpu/powerpc/ppc.h420
1 files changed, 210 insertions, 210 deletions
diff --git a/src/devices/cpu/powerpc/ppc.h b/src/devices/cpu/powerpc/ppc.h
index 3ebb74d1227..0951dfb6b56 100644
--- a/src/devices/cpu/powerpc/ppc.h
+++ b/src/devices/cpu/powerpc/ppc.h
@@ -211,15 +211,15 @@ protected:
public:
// construction/destruction
- ppc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int address_bits, int data_bits, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor, address_map_constructor internal_map);
+ ppc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, int address_bits, int data_bits, powerpc_flavor flavor, uint32_t cap, uint32_t tb_divisor, address_map_constructor internal_map);
- static void set_bus_frequency(device_t &device, UINT32 bus_frequency) { downcast<ppc_device &>(device).c_bus_frequency = bus_frequency; }
+ static void set_bus_frequency(device_t &device, uint32_t bus_frequency) { downcast<ppc_device &>(device).c_bus_frequency = bus_frequency; }
void ppc_set_dcstore_callback(write32_delegate callback);
- void ppcdrc_set_options(UINT32 options);
- void ppcdrc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
- void ppcdrc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
+ void ppcdrc_set_options(uint32_t options);
+ void ppcdrc_add_fastram(offs_t start, offs_t end, uint8_t readonly, void *base);
+ void ppcdrc_add_hotspot(offs_t pc, uint32_t opcode, uint32_t cycles);
TIMER_CALLBACK_MEMBER(decrementer_int_callback);
TIMER_CALLBACK_MEMBER(ppc4xx_buffered_dma_callback);
@@ -251,9 +251,9 @@ protected:
virtual void device_stop() override;
// device_execute_interface overrides
- virtual UINT32 execute_min_cycles() const override { return 1; }
- virtual UINT32 execute_max_cycles() const override { return 40; }
- virtual UINT32 execute_input_lines() const override { return 1; }
+ virtual uint32_t execute_min_cycles() const override { return 1; }
+ virtual uint32_t execute_max_cycles() const override { return 40; }
+ virtual uint32_t execute_input_lines() const override { return 1; }
virtual void execute_run() override;
virtual void execute_set_input(int inputnum, int state) override;
@@ -267,9 +267,9 @@ protected:
virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
// device_disasm_interface overrides
- virtual UINT32 disasm_min_opcode_bytes() const override { return 4; }
- virtual UINT32 disasm_max_opcode_bytes() const override { return 4; }
- virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override;
+ virtual uint32_t disasm_min_opcode_bytes() const override { return 4; }
+ virtual uint32_t disasm_max_opcode_bytes() const override { return 4; }
+ virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
/* exception types */
enum
@@ -295,36 +295,36 @@ protected:
address_space_config m_program_config;
address_space *m_program;
- UINT32 c_bus_frequency;
+ uint32_t c_bus_frequency;
struct internal_ppc_state
{
- UINT32 pc;
- UINT32 r[32];
+ uint32_t pc;
+ uint32_t r[32];
double f[32];
- UINT32 cr[8];
- UINT32 fpscr;
- UINT32 msr;
- UINT32 xerso;
- UINT32 sr[16];
- UINT32 spr[1024];
+ uint32_t cr[8];
+ uint32_t fpscr;
+ uint32_t msr;
+ uint32_t xerso;
+ uint32_t sr[16];
+ uint32_t spr[1024];
int icount;
- UINT32 mode; /* current global mode */
- UINT32 irq_pending;
+ uint32_t mode; /* current global mode */
+ uint32_t irq_pending;
/* parameters for calls */
- UINT32 param0;
- UINT32 param1;
+ uint32_t param0;
+ uint32_t param1;
/* PowerPC 603-specific state */
- UINT32 mmu603_cmp;
- UINT32 mmu603_hash[2];
- UINT32 mmu603_r[4];
+ uint32_t mmu603_cmp;
+ uint32_t mmu603_hash[2];
+ uint32_t mmu603_r[4];
/* parameters for subroutines */
- UINT32 tempaddr; /* temporary address storage */
+ uint32_t tempaddr; /* temporary address storage */
drcuml_ireg tempdata; /* temporary data storage */
- UINT32 updateaddr; /* update address storage */
- UINT32 swcount; /* counter for sw instructions */
+ uint32_t updateaddr; /* update address storage */
+ uint32_t swcount; /* counter for sw instructions */
const char * format; /* format string for printing */
- UINT32 arg0; /* print_debug argument 1 */
+ uint32_t arg0; /* print_debug argument 1 */
double fp0; /* floating point 0 */
};
@@ -335,82 +335,82 @@ protected:
int m_ppc_dec_trigger_cycle;
int m_bus_freq_multiplier;
- UINT32 m_npc;
- UINT32 m_dcr[256];
-
- UINT32 m_lr;
- UINT32 m_ctr;
- UINT32 m_xer;
- UINT32 m_pvr;
- UINT32 m_srr0;
- UINT32 m_srr1;
- UINT32 m_srr2;
- UINT32 m_srr3;
- UINT32 m_hid0;
- UINT32 m_hid1;
- UINT32 m_hid2;
- UINT32 m_sdr1;
- UINT32 m_sprg[4];
-
- UINT32 m_dsisr;
- UINT32 m_dar;
- UINT32 m_ear;
- UINT32 m_dmiss;
- UINT32 m_dcmp;
- UINT32 m_hash1;
- UINT32 m_hash2;
- UINT32 m_imiss;
- UINT32 m_icmp;
- UINT32 m_rpa;
+ uint32_t m_npc;
+ uint32_t m_dcr[256];
+
+ uint32_t m_lr;
+ uint32_t m_ctr;
+ uint32_t m_xer;
+ uint32_t m_pvr;
+ uint32_t m_srr0;
+ uint32_t m_srr1;
+ uint32_t m_srr2;
+ uint32_t m_srr3;
+ uint32_t m_hid0;
+ uint32_t m_hid1;
+ uint32_t m_hid2;
+ uint32_t m_sdr1;
+ uint32_t m_sprg[4];
+
+ uint32_t m_dsisr;
+ uint32_t m_dar;
+ uint32_t m_ear;
+ uint32_t m_dmiss;
+ uint32_t m_dcmp;
+ uint32_t m_hash1;
+ uint32_t m_hash2;
+ uint32_t m_imiss;
+ uint32_t m_icmp;
+ uint32_t m_rpa;
struct BATENT {
- UINT32 u;
- UINT32 l;
+ uint32_t u;
+ uint32_t l;
};
BATENT m_ibat[4];
BATENT m_dbat[4];
- UINT32 m_evpr;
- UINT32 m_exier;
- UINT32 m_exisr;
- UINT32 m_bear;
- UINT32 m_besr;
- UINT32 m_iocr;
- UINT32 m_br[8];
- UINT32 m_iabr;
- UINT32 m_esr;
- UINT32 m_iccr;
- UINT32 m_dccr;
- UINT32 m_pit;
- UINT32 m_pit_counter;
- UINT32 m_pit_int_enable;
- UINT32 m_tsr;
- UINT32 m_dbsr;
- UINT32 m_sgr;
- UINT32 m_pid;
- UINT32 m_pbl1;
- UINT32 m_pbl2;
- UINT32 m_pbu1;
- UINT32 m_pbu2;
- UINT32 m_fit_bit;
- UINT32 m_fit_int_enable;
- UINT32 m_wdt_bit;
- UINT32 m_wdt_int_enable;
- UINT32 m_dac1;
- UINT32 m_dac2;
- UINT32 m_iac1;
- UINT32 m_iac2;
+ uint32_t m_evpr;
+ uint32_t m_exier;
+ uint32_t m_exisr;
+ uint32_t m_bear;
+ uint32_t m_besr;
+ uint32_t m_iocr;
+ uint32_t m_br[8];
+ uint32_t m_iabr;
+ uint32_t m_esr;
+ uint32_t m_iccr;
+ uint32_t m_dccr;
+ uint32_t m_pit;
+ uint32_t m_pit_counter;
+ uint32_t m_pit_int_enable;
+ uint32_t m_tsr;
+ uint32_t m_dbsr;
+ uint32_t m_sgr;
+ uint32_t m_pid;
+ uint32_t m_pbl1;
+ uint32_t m_pbl2;
+ uint32_t m_pbu1;
+ uint32_t m_pbu2;
+ uint32_t m_fit_bit;
+ uint32_t m_fit_int_enable;
+ uint32_t m_wdt_bit;
+ uint32_t m_wdt_int_enable;
+ uint32_t m_dac1;
+ uint32_t m_dac2;
+ uint32_t m_iac1;
+ uint32_t m_iac2;
struct SPU_REGS {
- UINT8 spls;
- UINT8 sphs;
- UINT16 brd;
- UINT8 spctl;
- UINT8 sprc;
- UINT8 sptc;
- UINT8 sprb;
- UINT8 sptb;
+ uint8_t spls;
+ uint8_t sphs;
+ uint16_t brd;
+ uint8_t spctl;
+ uint8_t sprc;
+ uint8_t sptc;
+ uint8_t sprb;
+ uint8_t sptb;
emu_timer *rx_timer;
emu_timer *tx_timer;
};
@@ -418,33 +418,33 @@ protected:
SPU_REGS m_spu_old;
struct DMA_REGS {
- UINT32 cr;
- UINT32 da;
- UINT32 sa;
- UINT32 ct;
- UINT32 cc;
+ uint32_t cr;
+ uint32_t da;
+ uint32_t sa;
+ uint32_t ct;
+ uint32_t cc;
};
DMA_REGS m_dma[4];
- UINT32 m_dmasr;
+ uint32_t m_dmasr;
int m_reserved;
- UINT32 m_reserved_address;
+ uint32_t m_reserved_address;
int m_interrupt_pending;
- UINT64 m_tb; /* 56-bit timebase register */
+ uint64_t m_tb; /* 56-bit timebase register */
// STUFF added for the 6xx series
- UINT32 m_dec, m_dec_frac;
+ uint32_t m_dec, m_dec_frac;
union FPR {
- UINT64 id;
+ uint64_t id;
double fd;
};
union FPR32 {
- UINT32 i;
+ uint32_t i;
float f;
};
@@ -454,30 +454,30 @@ protected:
int m_is602;
/* PowerPC 602 specific registers */
- UINT32 m_lt;
- UINT32 m_sp;
- UINT32 m_tcr;
- UINT32 m_ibr;
- UINT32 m_esasrr;
- UINT32 m_sebr;
- UINT32 m_ser;
+ uint32_t m_lt;
+ uint32_t m_sp;
+ uint32_t m_tcr;
+ uint32_t m_ibr;
+ uint32_t m_esasrr;
+ uint32_t m_sebr;
+ uint32_t m_ser;
/* architectural distinctions */
powerpc_flavor m_flavor;
- UINT32 m_cap;
- UINT8 m_cache_line_size;
- UINT32 m_tb_divisor;
+ uint32_t m_cap;
+ uint8_t m_cache_line_size;
+ uint32_t m_tb_divisor;
/* PowerPC 4xx-specific state */
/* PowerPC 4XX-specific serial port state */
struct ppc4xx_spu_state
{
- UINT8 regs[9];
- UINT8 txbuf;
- UINT8 rxbuf;
+ uint8_t regs[9];
+ uint8_t txbuf;
+ uint8_t rxbuf;
emu_timer * timer;
- UINT8 rxbuffer[256];
- UINT32 rxin, rxout;
+ uint8_t rxbuffer[256];
+ uint32_t rxin, rxout;
write8_delegate tx_cb;
};
@@ -485,18 +485,18 @@ protected:
emu_timer * m_fit_timer;
emu_timer * m_pit_timer;
emu_timer * m_wdog_timer;
- UINT32 m_pit_reload;
- UINT32 m_irqstate;
+ uint32_t m_pit_reload;
+ uint32_t m_irqstate;
emu_timer * m_buffered_dma_timer[4];
int m_buffered_dma_rate[4];
/* internal stuff */
direct_read_data *m_direct;
offs_t m_codexor;
- UINT32 m_system_clock;
- UINT32 m_cpu_clock;
- UINT64 m_tb_zero_cycles;
- UINT64 m_dec_zero_cycles;
+ uint32_t m_system_clock;
+ uint32_t m_cpu_clock;
+ uint64_t m_tb_zero_cycles;
+ uint64_t m_dec_zero_cycles;
emu_timer * m_decrementer_int_timer;
read32_delegate m_dcr_read_func;
@@ -511,45 +511,45 @@ protected:
#ifdef PPC_H_INCLUDED_FROM_PPC_C
jmp_buf m_exception_jmpbuf;
#endif
- UINT8 (*m_ppcread8)(address_space &space, offs_t address);
- UINT16 (*m_ppcread16)(address_space &space, offs_t address);
- UINT32 (*m_ppcread32)(address_space &space, offs_t address);
- UINT64 (*m_ppcread64)(address_space &space, offs_t address);
- void (*m_ppcwrite8)(address_space &space, offs_t address, UINT8 data);
- void (*m_ppcwrite16)(address_space &space, offs_t address, UINT16 data);
- void (*m_ppcwrite32)(address_space &space, offs_t address, UINT32 data);
- void (*m_ppcwrite64)(address_space &space, offs_t address, UINT64 data);
- UINT16 (*m_ppcread16_unaligned)(address_space &space, offs_t address);
- UINT32 (*m_ppcread32_unaligned)(address_space &space, offs_t address);
- UINT64 (*m_ppcread64_unaligned)(address_space &space, offs_t address);
- void (*m_ppcwrite16_unaligned)(address_space &space, offs_t address, UINT16 data);
- void (*m_ppcwrite32_unaligned)(address_space &space, offs_t address, UINT32 data);
- void (*m_ppcwrite64_unaligned)(address_space &space, offs_t address, UINT64 data);
-
- void (*m_optable19[1024])(UINT32);
- void (*m_optable31[1024])(UINT32);
- void (*m_optable59[1024])(UINT32);
- void (*m_optable63[1024])(UINT32);
- void (*m_optable[64])(UINT32);
+ uint8_t (*m_ppcread8)(address_space &space, offs_t address);
+ uint16_t (*m_ppcread16)(address_space &space, offs_t address);
+ uint32_t (*m_ppcread32)(address_space &space, offs_t address);
+ uint64_t (*m_ppcread64)(address_space &space, offs_t address);
+ void (*m_ppcwrite8)(address_space &space, offs_t address, uint8_t data);
+ void (*m_ppcwrite16)(address_space &space, offs_t address, uint16_t data);
+ void (*m_ppcwrite32)(address_space &space, offs_t address, uint32_t data);
+ void (*m_ppcwrite64)(address_space &space, offs_t address, uint64_t data);
+ uint16_t (*m_ppcread16_unaligned)(address_space &space, offs_t address);
+ uint32_t (*m_ppcread32_unaligned)(address_space &space, offs_t address);
+ uint64_t (*m_ppcread64_unaligned)(address_space &space, offs_t address);
+ void (*m_ppcwrite16_unaligned)(address_space &space, offs_t address, uint16_t data);
+ void (*m_ppcwrite32_unaligned)(address_space &space, offs_t address, uint32_t data);
+ void (*m_ppcwrite64_unaligned)(address_space &space, offs_t address, uint64_t data);
+
+ void (*m_optable19[1024])(uint32_t);
+ void (*m_optable31[1024])(uint32_t);
+ void (*m_optable59[1024])(uint32_t);
+ void (*m_optable63[1024])(uint32_t);
+ void (*m_optable[64])(uint32_t);
/* core state */
drc_cache m_cache; /* pointer to the DRC code cache */
std::unique_ptr<drcuml_state> m_drcuml; /* DRC UML generator state */
std::unique_ptr<ppc_frontend> m_drcfe; /* pointer to the DRC front-end state */
- UINT32 m_drcoptions; /* configurable DRC options */
+ uint32_t m_drcoptions; /* configurable DRC options */
/* parameters for subroutines */
- UINT32 m_arg1; /* print_debug argument 2 */
+ uint32_t m_arg1; /* print_debug argument 2 */
/* tables */
- UINT8 m_fpmode[4]; /* FPU mode table */
- UINT8 m_sz_cr_table[32]; /* SZ CR table */
- UINT8 m_cmp_cr_table[32]; /* CMP CR table */
- UINT8 m_cmpl_cr_table[32]; /* CMPL CR table */
- UINT8 m_fcmp_cr_table[32]; /* FCMP CR table */
+ uint8_t m_fpmode[4]; /* FPU mode table */
+ uint8_t m_sz_cr_table[32]; /* SZ CR table */
+ uint8_t m_cmp_cr_table[32]; /* CMP CR table */
+ uint8_t m_cmpl_cr_table[32]; /* CMPL CR table */
+ uint8_t m_fcmp_cr_table[32]; /* FCMP CR table */
/* internal stuff */
- UINT8 m_cache_dirty; /* true if we need to flush the cache */
+ uint8_t m_cache_dirty; /* true if we need to flush the cache */
/* register mappings */
uml::parameter m_regmap[32]; /* parameter to register mappings for all 32 integer registers */
@@ -588,11 +588,11 @@ protected:
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
- UINT8 readonly; /* TRUE if read-only */
+ uint8_t readonly; /* TRUE if read-only */
void * base; /* base in memory where the RAM lives */
};
- UINT32 m_fastram_select;
+ uint32_t m_fastram_select;
fast_ram_info m_fastram[PPC_MAX_FASTRAM];
/* hotspots */
@@ -600,57 +600,57 @@ protected:
struct hotspot_info
{
offs_t pc; /* PC to consider */
- UINT32 opcode; /* required opcode at that PC */
- UINT32 cycles; /* number of cycles to eat when hit */
+ uint32_t opcode; /* required opcode at that PC */
+ uint32_t cycles; /* number of cycles to eat when hit */
};
- UINT32 m_hotspot_select;
+ uint32_t m_hotspot_select;
hotspot_info m_hotspot[PPC_MAX_HOTSPOTS];
- UINT64 m_debugger_temp;
+ uint64_t m_debugger_temp;
/* internal compiler state */
struct compiler_state
{
- UINT32 cycles; /* accumulated cycles */
- UINT8 checkints; /* need to check interrupts before next instruction */
- UINT8 checksoftints; /* need to check software interrupts before next instruction */
+ uint32_t cycles; /* accumulated cycles */
+ uint8_t checkints; /* need to check interrupts before next instruction */
+ uint8_t checksoftints; /* need to check software interrupts before next instruction */
uml::code_label labelnum; /* index for local labels */
};
- UINT32 get_cr();
- void set_cr(UINT32 value);
- UINT32 get_xer();
- void set_xer(UINT32 value);
- UINT64 get_timebase();
- void set_timebase(UINT64 newtb);
- UINT32 get_decrementer();
- void set_decrementer(UINT32 newdec);
- UINT32 ppccom_translate_address_internal(int intention, offs_t &address);
- void ppc4xx_set_irq_line(UINT32 bitmask, int state);
- int ppc4xx_get_irq_line(UINT32 bitmask);
+ uint32_t get_cr();
+ void set_cr(uint32_t value);
+ uint32_t get_xer();
+ void set_xer(uint32_t value);
+ uint64_t get_timebase();
+ void set_timebase(uint64_t newtb);
+ uint32_t get_decrementer();
+ void set_decrementer(uint32_t newdec);
+ uint32_t ppccom_translate_address_internal(int intention, offs_t &address);
+ void ppc4xx_set_irq_line(uint32_t bitmask, int state);
+ int ppc4xx_get_irq_line(uint32_t bitmask);
void ppc4xx_dma_update_irq_states();
int ppc4xx_dma_decrement_count(int dmachan);
- int ppc4xx_dma_fetch_transmit_byte(int dmachan, UINT8 *byte);
- int ppc4xx_dma_handle_receive_byte(int dmachan, UINT8 byte);
+ int ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte);
+ int ppc4xx_dma_handle_receive_byte(int dmachan, uint8_t byte);
void ppc4xx_dma_exec(int dmachan);
void ppc4xx_spu_update_irq_states();
- void ppc4xx_spu_rx_data(UINT8 data);
+ void ppc4xx_spu_rx_data(uint8_t data);
void ppc4xx_spu_timer_reset();
void alloc_handle(drcuml_state *drcuml, uml::code_handle **handleptr, const char *name);
void load_fast_iregs(drcuml_block *block);
void save_fast_iregs(drcuml_block *block);
void load_fast_fregs(drcuml_block *block);
void save_fast_fregs(drcuml_block *block);
- UINT32 compute_rlw_mask(UINT8 mb, UINT8 me);
- UINT32 compute_crf_mask(UINT8 crm);
- UINT32 compute_spr(UINT32 spr);
+ uint32_t compute_rlw_mask(uint8_t mb, uint8_t me);
+ uint32_t compute_crf_mask(uint8_t crm);
+ uint32_t compute_spr(uint32_t spr);
void code_flush_cache();
- void code_compile_block(UINT8 mode, offs_t pc);
+ void code_compile_block(uint8_t mode, offs_t pc);
void static_generate_entry_point();
void static_generate_nocode_handler();
void static_generate_out_of_cycles();
void static_generate_tlb_mismatch();
- void static_generate_exception(UINT8 exception, int recover, const char *name);
+ void static_generate_exception(uint8_t exception, int recover, const char *name);
void static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, uml::code_handle *&handleptr, uml::code_handle *masked);
void static_generate_swap_tgpr();
void static_generate_lsw_entries(int mode);
@@ -659,19 +659,19 @@ protected:
void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- void generate_compute_flags(drcuml_block *block, const opcode_desc *desc, int updatecr, UINT32 xermask, int invertcarry);
- void generate_shift_flags(drcuml_block *block, const opcode_desc *desc, UINT32 op);
+ void generate_compute_flags(drcuml_block *block, const opcode_desc *desc, int updatecr, uint32_t xermask, int invertcarry);
+ void generate_shift_flags(drcuml_block *block, const opcode_desc *desc, uint32_t op);
void generate_fp_flags(drcuml_block *block, const opcode_desc *desc, int updatefprf);
- void generate_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int source, UINT8 link);
- void generate_branch_bo(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 bo, UINT32 bi, int source, int link);
+ void generate_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int source, uint8_t link);
+ void generate_branch_bo(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t bo, uint32_t bi, int source, int link);
int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
int generate_instruction_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
int generate_instruction_1f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
int generate_instruction_3b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
int generate_instruction_3f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op);
- const char *log_desc_flags_to_string(UINT32 flags);
- void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist);
+ void log_add_disasm_comment(drcuml_block *block, uint32_t pc, uint32_t op);
+ const char *log_desc_flags_to_string(uint32_t flags);
+ void log_register_list(drcuml_state *drcuml, const char *string, const uint32_t *reglist, const uint32_t *regnostarlist);
void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent);
};
@@ -680,79 +680,79 @@ protected:
//class ppc403_device : public ppc_device
//{
//public:
-// ppc403_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+// ppc403_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
//
//protected:
-// virtual UINT32 execute_input_lines() const { return 8; }
+// virtual uint32_t execute_input_lines() const { return 8; }
//};
//
//
//class ppc405_device : public ppc_device
//{
//public:
-// ppc405_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+// ppc405_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
//
//protected:
-// virtual UINT32 execute_input_lines() const { return 8; }
+// virtual uint32_t execute_input_lines() const { return 8; }
//};
class ppc603_device : public ppc_device
{
public:
- ppc603_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ ppc603_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
class ppc603e_device : public ppc_device
{
public:
- ppc603e_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ ppc603e_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
class ppc603r_device : public ppc_device
{
public:
- ppc603r_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ ppc603r_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
class ppc602_device : public ppc_device
{
public:
- ppc602_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ ppc602_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
class mpc8240_device : public ppc_device
{
public:
- mpc8240_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ mpc8240_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
class ppc601_device : public ppc_device
{
public:
- ppc601_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ ppc601_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
class ppc604_device : public ppc_device
{
public:
- ppc604_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ ppc604_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
class ppc4xx_device : public ppc_device
{
public:
- ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor);
+ ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, powerpc_flavor flavor, uint32_t cap, uint32_t tb_divisor);
void ppc4xx_spu_set_tx_handler(write8_delegate callback);
- void ppc4xx_spu_receive_byte(UINT8 byteval);
+ void ppc4xx_spu_receive_byte(uint8_t byteval);
void ppc4xx_set_dma_read_handler(int channel, read32_delegate callback, int rate);
void ppc4xx_set_dma_write_handler(int channel, write32_delegate callback, int rate);
@@ -763,7 +763,7 @@ public:
DECLARE_WRITE8_MEMBER( ppc4xx_spu_w );
protected:
- virtual UINT32 execute_input_lines() const override { return 5; }
+ virtual uint32_t execute_input_lines() const override { return 5; }
virtual void execute_set_input(int inputnum, int state) override;
};
@@ -771,21 +771,21 @@ protected:
class ppc403ga_device : public ppc4xx_device
{
public:
- ppc403ga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ ppc403ga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
class ppc403gcx_device : public ppc4xx_device
{
public:
- ppc403gcx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ ppc403gcx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
class ppc405gp_device : public ppc4xx_device
{
public:
- ppc405gp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ ppc405gp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};