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Diffstat (limited to 'src/devices/cpu/mips/mips3com.cpp')
-rw-r--r--src/devices/cpu/mips/mips3com.cpp18
1 files changed, 13 insertions, 5 deletions
diff --git a/src/devices/cpu/mips/mips3com.cpp b/src/devices/cpu/mips/mips3com.cpp
index f671ba2c335..2a9a933ef87 100644
--- a/src/devices/cpu/mips/mips3com.cpp
+++ b/src/devices/cpu/mips/mips3com.cpp
@@ -143,7 +143,7 @@ generate_tlb_index - generate a random tlb index
uint32_t mips3_device::generate_tlb_index()
{
// Actual hardware uses a free running counter to generate the index.
- // This impementation uses a linear congruential generator so that DRC and non-DRC code sequences match.
+ // This implementation uses a linear congruential generator so that DRC and non-DRC code sequences match.
m_tlb_seed = 214013 * m_tlb_seed + 2531011;
return (m_tlb_seed >> 16) & 0x3f;
}
@@ -336,8 +336,10 @@ uint32_t mips3_device::compute_prid_register()
return 0x5500;
case MIPS3_TYPE_R4600:
+ return 0x2020;
+
case MIPS3_TYPE_R4650:
- return 0x2000;
+ return 0x2200;
case MIPS3_TYPE_R4700:
return 0x2100;
@@ -364,6 +366,12 @@ uint32_t mips3_device::compute_prid_register()
//return 0x2000;
}
+uint32_t mips3_device::compute_fpu_prid_register()
+{
+ /* For most CPUs they are same */
+ return compute_prid_register();
+}
+
/*-------------------------------------------------
tlb_map_entry - map a single TLB
entry
@@ -414,15 +422,15 @@ void mips3_device::tlb_map_entry(int tlbindex)
/* valid? */
if ((lo & 2) != 0)
{
- flags |= VTLB_FLAG_VALID | VTLB_READ_ALLOWED | VTLB_FETCH_ALLOWED;
+ flags |= FLAG_VALID | READ_ALLOWED | FETCH_ALLOWED;
/* writable? */
if ((lo & 4) != 0)
- flags |= VTLB_WRITE_ALLOWED;
+ flags |= WRITE_ALLOWED;
/* mirror the flags for user mode if the VPN is in user space */
if (effvpn < (0x80000000 >> MIPS3_MIN_PAGE_SHIFT))
- flags |= (flags << 4) & (VTLB_USER_READ_ALLOWED | VTLB_USER_WRITE_ALLOWED | VTLB_USER_FETCH_ALLOWED);
+ flags |= (flags << 4) & (USER_READ_ALLOWED | USER_WRITE_ALLOWED | USER_FETCH_ALLOWED);
}
/* load the virtual TLB with the corresponding entries */