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Diffstat (limited to 'src/devices/cpu/mips/mips1.cpp')
-rw-r--r--src/devices/cpu/mips/mips1.cpp58
1 files changed, 37 insertions, 21 deletions
diff --git a/src/devices/cpu/mips/mips1.cpp b/src/devices/cpu/mips/mips1.cpp
index b85d2e29d63..c8c31e6c05f 100644
--- a/src/devices/cpu/mips/mips1.cpp
+++ b/src/devices/cpu/mips/mips1.cpp
@@ -642,13 +642,21 @@ device_memory_interface::space_config_vector mips1core_device_base::memory_space
};
}
-bool mips1core_device_base::memory_translate(int spacenum, int intention, offs_t &address)
+bool mips1core_device_base::memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space)
+{
+ target_space = &space(spacenum);
+ if(spacenum != AS_PROGRAM)
+ return true;
+ return memory_translate(intention, address, true);
+}
+
+bool mips1core_device_base::memory_translate(int intention, offs_t &address, bool debug)
{
// check for kernel memory address
if (BIT(address, 31))
{
// check debug or kernel mode
- if ((intention & TRANSLATE_DEBUG_MASK) || !(SR & SR_KUc))
+ if (debug || !(SR & SR_KUc))
{
switch (address & 0xe0000000)
{
@@ -873,13 +881,13 @@ void mips1core_device_base::generate_exception(u32 exception, bool refill)
void mips1core_device_base::address_error(int intention, u32 const address)
{
- if (!machine().side_effects_disabled() && !(intention & TRANSLATE_DEBUG_MASK))
+ if (!machine().side_effects_disabled())
{
logerror("address_error 0x%08x (%s)\n", address, machine().describe_context());
m_cop0[COP0_BadVAddr] = address;
- generate_exception((intention & TRANSLATE_WRITE) ? EXCEPTION_ADDRSTORE : EXCEPTION_ADDRLOAD);
+ generate_exception((intention & TR_WRITE) ? EXCEPTION_ADDRSTORE : EXCEPTION_ADDRLOAD);
// address errors shouldn't typically occur, so a breakpoint is handy
machine().debug_break();
@@ -1097,11 +1105,11 @@ template <typename T, bool Aligned, typename U> std::enable_if_t<std::is_convert
// alignment error
if (Aligned && (address & (sizeof(T) - 1)))
{
- address_error(TRANSLATE_READ, address);
+ address_error(TR_READ, address);
return;
}
- if (memory_translate(m_data_spacenum, TRANSLATE_READ, address))
+ if (memory_translate(TR_READ, address, false))
{
// align address for ld[lr] instructions
if (!Aligned)
@@ -1127,11 +1135,11 @@ template <typename T, bool Aligned, typename U> std::enable_if_t<std::is_convert
// alignment error
if (Aligned && (address & (sizeof(T) - 1)))
{
- address_error(TRANSLATE_WRITE, address);
+ address_error(TR_WRITE, address);
return;
}
- if (memory_translate(m_data_spacenum, TRANSLATE_WRITE, address))
+ if (memory_translate(TR_WRITE, address, false))
{
// align address for sd[lr] instructions
if (!Aligned)
@@ -1151,13 +1159,13 @@ bool mips1core_device_base::fetch(u32 address, std::function<void(u32)> &&apply)
// alignment error
if (address & 3)
{
- address_error(TRANSLATE_FETCH, address);
+ address_error(TR_FETCH, address);
return false;
}
- if (memory_translate(0, TRANSLATE_FETCH, address))
+ if (memory_translate(TR_FETCH, address, false))
{
- u32 const data = space(0).read_dword(address);
+ u32 const data = space(AS_PROGRAM).read_dword(address);
if (m_bus_error)
{
@@ -1271,9 +1279,9 @@ void mips1_device_base::device_reset()
// initialize tlb mru index with identity mapping
for (unsigned i = 0; i < std::size(m_tlb); i++)
{
- m_tlb_mru[TRANSLATE_READ][i] = i;
- m_tlb_mru[TRANSLATE_WRITE][i] = i;
- m_tlb_mru[TRANSLATE_FETCH][i] = i;
+ m_tlb_mru[TR_READ][i] = i;
+ m_tlb_mru[TR_WRITE][i] = i;
+ m_tlb_mru[TR_FETCH][i] = i;
}
}
@@ -1945,13 +1953,21 @@ template <typename T> void mips1_device_base::set_cop1_reg(unsigned const reg, T
m_f[reg] = data;
}
-bool mips1_device_base::memory_translate(int spacenum, int intention, offs_t &address)
+bool mips1_device_base::memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space)
+{
+ target_space = &space(spacenum);
+ if(spacenum != AS_PROGRAM)
+ return true;
+ return memory_translate(intention, address, true);
+}
+
+bool mips1_device_base::memory_translate(int intention, offs_t &address, bool debug)
{
// check for kernel memory address
if (BIT(address, 31))
{
// check debug or kernel mode
- if ((intention & TRANSLATE_DEBUG_MASK) || !(SR & SR_KUc))
+ if (debug || !(SR & SR_KUc))
{
switch (address & 0xe0000000)
{
@@ -1976,7 +1992,7 @@ bool mips1_device_base::memory_translate(int spacenum, int intention, offs_t &ad
// key is a combination of VPN and ASID
u32 const key = (address & EH_VPN) | (m_cop0[COP0_EntryHi] & EH_ASID);
- unsigned *mru = m_tlb_mru[intention & TRANSLATE_TYPE_MASK];
+ unsigned *mru = m_tlb_mru[intention];
bool refill = !BIT(address, 31);
bool modify = false;
@@ -1999,7 +2015,7 @@ bool mips1_device_base::memory_translate(int spacenum, int intention, offs_t &ad
}
// test dirty
- if ((intention & TRANSLATE_WRITE) && !(entry[1] & EL_D))
+ if ((intention & TR_WRITE) && !(entry[1] & EL_D))
{
refill = false;
modify = true;
@@ -2017,7 +2033,7 @@ bool mips1_device_base::memory_translate(int spacenum, int intention, offs_t &ad
return true;
}
- if (!machine().side_effects_disabled() && !(intention & TRANSLATE_DEBUG_MASK))
+ if (!machine().side_effects_disabled() && !debug)
{
if (VERBOSE & LOG_TLB)
{
@@ -2026,7 +2042,7 @@ bool mips1_device_base::memory_translate(int spacenum, int intention, offs_t &ad
(m_cop0[COP0_EntryHi] & EH_ASID) >> 6, address, machine().describe_context());
else
LOGMASKED(LOG_TLB, "asid %2d tlb miss %c address 0x%08x (%s)\n",
- (m_cop0[COP0_EntryHi] & EH_ASID) >> 6, (intention & TRANSLATE_WRITE) ? 'w' : 'r', address, machine().describe_context());
+ (m_cop0[COP0_EntryHi] & EH_ASID) >> 6, (intention & TR_WRITE) ? 'w' : 'r', address, machine().describe_context());
}
// load tlb exception registers
@@ -2034,7 +2050,7 @@ bool mips1_device_base::memory_translate(int spacenum, int intention, offs_t &ad
m_cop0[COP0_EntryHi] = key;
m_cop0[COP0_Context] = (m_cop0[COP0_Context] & PTE_BASE) | ((address >> 10) & BAD_VPN);
- generate_exception(modify ? EXCEPTION_TLBMOD : (intention & TRANSLATE_WRITE) ? EXCEPTION_TLBSTORE : EXCEPTION_TLBLOAD, refill);
+ generate_exception(modify ? EXCEPTION_TLBMOD : (intention & TR_WRITE) ? EXCEPTION_TLBSTORE : EXCEPTION_TLBLOAD, refill);
}
return false;