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Diffstat (limited to 'src/devices/cpu/m37710/m37710.cpp')
-rw-r--r--src/devices/cpu/m37710/m37710.cpp557
1 files changed, 318 insertions, 239 deletions
diff --git a/src/devices/cpu/m37710/m37710.cpp b/src/devices/cpu/m37710/m37710.cpp
index df78cdafe74..e0f3394ae77 100644
--- a/src/devices/cpu/m37710/m37710.cpp
+++ b/src/devices/cpu/m37710/m37710.cpp
@@ -1,5 +1,5 @@
// license:BSD-3-Clause
-// copyright-holders:R. Belmont, Karl Stenerud, hap
+// copyright-holders:R. Belmont, Karl Stenerud
/*
Mitsubishi M37702/37710/37720 CPU Emulator
@@ -31,6 +31,10 @@
- Unlike the 65C816, the program bank register (known here as PG) is
incremented when PC overflows from 0xFFFF, and may be incremented or
decremented when the address for a relative branch is calculated.
+ - The external bus, if used, allows for 16-bit transfers, and can be
+ dynamically reduced to 8 bits by asserting the BYTE input. (The
+ 65C816 has an 8-bit data bus.) Internal memory is also 16 bits wide,
+ but parallel port registers must be accessed as individual bytes.
The various 7700 series models differ primarily by their on board
peripherals. The 7750 and later models do include some additional
@@ -57,18 +61,17 @@
*/
#include "emu.h"
-#include "debugger.h"
#include "m37710.h"
+
#include "m37710cm.h"
#include "m37710il.h"
// verbose logging for peripherals, etc.
-#define LOG_GENERAL (1U << 0)
#define LOG_PORTS (1U << 1)
-#define LOG_AD (1U << 2)
-#define LOG_UART (1U << 3)
+#define LOG_AD (1U << 2)
+#define LOG_UART (1U << 3)
#define LOG_TIMER (1U << 4)
-#define LOG_INT (1U << 5)
+#define LOG_INT (1U << 5)
//#define VERBOSE (LOG_GENERAL | LOG_PORTS | LOG_AD | LOG_UART | LOG_TIMER | LOG_INT)
#include "logmacro.h"
@@ -77,39 +80,147 @@ DEFINE_DEVICE_TYPE(M37702M2, m37702m2_device, "m37702m2", "Mitsubishi M37702M2")
DEFINE_DEVICE_TYPE(M37702S1, m37702s1_device, "m37702s1", "Mitsubishi M37702S1")
DEFINE_DEVICE_TYPE(M37710S4, m37710s4_device, "m37710s4", "Mitsubishi M37710S4")
DEFINE_DEVICE_TYPE(M37720S1, m37720s1_device, "m37720s1", "Mitsubishi M37720S1")
+DEFINE_DEVICE_TYPE(M37730S2, m37730s2_device, "m37730s2", "Mitsubishi M37730S2")
+DEFINE_DEVICE_TYPE(M37732S4, m37732s4_device, "m37732s4", "Mitsubishi M37732S4")
// On-board RAM, ROM, and peripherals
+template <int Base>
+uint8_t m37710_cpu_device::port_r(offs_t offset)
+{
+ int p = (offset & ~1) + Base;
+
+ uint8_t result = 0;
+ if (BIT(offset, 0))
+ result = get_port_dir(p);
+ else
+ result = get_port_reg(p);
+
+ LOGMASKED(LOG_PORTS, "port_r from %02x: Port P%d %s = %x\n",
+ 0x02 + (Base + offset) * 2 - (Base & 1),
+ p,
+ BIT(offset, 0) ? "dir reg" : "reg", result);
+
+ return result;
+}
+
+template <int Base>
+void m37710_cpu_device::port_w(offs_t offset, uint8_t data)
+{
+ int p = (offset & ~1) + Base;
+
+ LOGMASKED(LOG_PORTS, "port_w %x to %02x: Port P%d %s = %x\n",
+ data,
+ 0x02 + (Base + offset) * 2 - (Base & 1),
+ p,
+ BIT(offset, 0) ? "dir reg" : "reg",
+ BIT(offset, 0) ? m_port_dir[p] : m_port_regs[p]);
+
+ if (BIT(offset, 0))
+ set_port_dir(p, data);
+ else
+ set_port_reg(p, data);
+}
+
+template <int Level>
+uint8_t m37710_cpu_device::int_control_r()
+{
+ return get_int_control(Level);
+}
+
+template <int Level>
+void m37710_cpu_device::int_control_w(uint8_t data)
+{
+ set_int_control(Level, data);
+}
+
+void m37710_cpu_device::ad_register_map(address_map &map)
+{
+ map(0x00001e, 0x00001e).rw(FUNC(m37710_cpu_device::ad_control_r), FUNC(m37710_cpu_device::ad_control_w));
+ map(0x00001f, 0x00001f).rw(FUNC(m37710_cpu_device::ad_sweep_r), FUNC(m37710_cpu_device::ad_sweep_w));
+ map(0x000020, 0x00002f).r(FUNC(m37710_cpu_device::ad_result_r));
+ map(0x000070, 0x000070).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_ADC>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_ADC>));
+}
+
+void m37710_cpu_device::uart0_register_map(address_map &map)
+{
+ map(0x000030, 0x000030).rw(FUNC(m37710_cpu_device::uart0_mode_r), FUNC(m37710_cpu_device::uart0_mode_w));
+ map(0x000031, 0x000031).w(FUNC(m37710_cpu_device::uart0_baud_w));
+ map(0x000032, 0x000033).w(FUNC(m37710_cpu_device::uart0_tbuf_w));
+ map(0x000034, 0x000034).rw(FUNC(m37710_cpu_device::uart0_ctrl_reg0_r), FUNC(m37710_cpu_device::uart0_ctrl_reg0_w));
+ map(0x000035, 0x000035).rw(FUNC(m37710_cpu_device::uart0_ctrl_reg1_r), FUNC(m37710_cpu_device::uart0_ctrl_reg1_w));
+ map(0x000036, 0x000037).r(FUNC(m37710_cpu_device::uart0_rbuf_r));
+ map(0x000071, 0x000071).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_UART0XMIT>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_UART0XMIT>));
+ map(0x000072, 0x000072).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_UART0RECV>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_UART0RECV>));
+}
+
+void m37710_cpu_device::uart1_register_map(address_map &map)
+{
+ map(0x000038, 0x000038).rw(FUNC(m37710_cpu_device::uart1_mode_r), FUNC(m37710_cpu_device::uart1_mode_w));
+ map(0x000039, 0x000039).w(FUNC(m37710_cpu_device::uart1_baud_w));
+ map(0x00003a, 0x00003b).w(FUNC(m37710_cpu_device::uart1_tbuf_w));
+ map(0x00003c, 0x00003c).rw(FUNC(m37710_cpu_device::uart1_ctrl_reg0_r), FUNC(m37710_cpu_device::uart1_ctrl_reg0_w));
+ map(0x00003d, 0x00003d).rw(FUNC(m37710_cpu_device::uart1_ctrl_reg1_r), FUNC(m37710_cpu_device::uart1_ctrl_reg1_w));
+ map(0x00003e, 0x00003f).r(FUNC(m37710_cpu_device::uart1_rbuf_r));
+ map(0x000073, 0x000073).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_UART1XMIT>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_UART1XMIT>));
+ map(0x000074, 0x000074).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_UART1RECV>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_UART1RECV>));
+}
+
+void m37710_cpu_device::timer_register_map(address_map &map)
+{
+ map(0x000040, 0x000040).rw(FUNC(m37710_cpu_device::count_start_r), FUNC(m37710_cpu_device::count_start_w));
+ map(0x000042, 0x000042).w(FUNC(m37710_cpu_device::one_shot_start_w));
+ map(0x000044, 0x000044).rw(FUNC(m37710_cpu_device::up_down_r), FUNC(m37710_cpu_device::up_down_w));
+ map(0x000046, 0x000055).rw(FUNC(m37710_cpu_device::timer_reg_r), FUNC(m37710_cpu_device::timer_reg_w));
+ map(0x000056, 0x00005d).rw(FUNC(m37710_cpu_device::timer_mode_r), FUNC(m37710_cpu_device::timer_mode_w));
+ map(0x000075, 0x000075).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERA0>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERA0>));
+ map(0x000076, 0x000076).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERA1>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERA1>));
+ map(0x000077, 0x000077).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERA2>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERA2>));
+ map(0x000078, 0x000078).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERA3>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERA3>));
+ map(0x000079, 0x000079).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERA4>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERA4>));
+ map(0x00007a, 0x00007a).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERB0>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERB0>));
+ map(0x00007b, 0x00007b).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERB1>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERB1>));
+ map(0x00007c, 0x00007c).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERB2>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERB2>));
+}
+
+void m37710_cpu_device::timer_6channel_register_map(address_map &map)
+{
+ map(0x000040, 0x000040).rw(FUNC(m37710_cpu_device::count_start_r), FUNC(m37710_cpu_device::count_start_w));
+ map(0x000042, 0x000042).w(FUNC(m37710_cpu_device::one_shot_start_w));
+ map(0x000044, 0x000044).rw(FUNC(m37710_cpu_device::up_down_r), FUNC(m37710_cpu_device::up_down_w));
+ map(0x000046, 0x000051).rw(FUNC(m37710_cpu_device::timer_reg_r), FUNC(m37710_cpu_device::timer_reg_w));
+ map(0x000056, 0x00005b).rw(FUNC(m37710_cpu_device::timer_mode_r), FUNC(m37710_cpu_device::timer_mode_w));
+ map(0x000075, 0x000075).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERA0>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERA0>));
+ map(0x000076, 0x000076).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERA1>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERA1>));
+ map(0x000077, 0x000077).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERA2>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERA2>));
+ map(0x000078, 0x000078).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERA3>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERA3>));
+ map(0x000079, 0x000079).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERA4>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERA4>));
+ map(0x00007a, 0x00007a).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_TIMERB0>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_TIMERB0>));
+}
+
+void m37710_cpu_device::irq_register_map(address_map &map)
+{
+ map(0x00007d, 0x00007d).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_IRQ0>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_IRQ0>));
+ map(0x00007e, 0x00007e).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_IRQ1>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_IRQ1>));
+ map(0x00007f, 0x00007f).rw(FUNC(m37710_cpu_device::int_control_r<M37710_LINE_IRQ2>), FUNC(m37710_cpu_device::int_control_w<M37710_LINE_IRQ2>));
+}
+
// M37702M2: 512 bytes internal RAM, 16K internal mask ROM
// (M37702E2: same with EPROM instead of mask ROM)
void m37702m2_device::map(address_map &map)
{
- map(0x000002, 0x000015).rw(FUNC(m37702m2_device::port_r), FUNC(m37702m2_device::port_w));
- map(0x00001e, 0x00001e).rw(FUNC(m37702m2_device::ad_control_r), FUNC(m37702m2_device::ad_control_w));
- map(0x00001f, 0x00001f).rw(FUNC(m37702m2_device::ad_sweep_r), FUNC(m37702m2_device::ad_sweep_w));
- map(0x000020, 0x00002f).r(FUNC(m37702m2_device::ad_result_r));
- map(0x000030, 0x000030).rw(FUNC(m37702m2_device::uart0_mode_r), FUNC(m37702m2_device::uart0_mode_w));
- map(0x000031, 0x000031).w(FUNC(m37702m2_device::uart0_baud_w));
- map(0x000032, 0x000033).w(FUNC(m37702m2_device::uart0_tbuf_w));
- map(0x000034, 0x000034).rw(FUNC(m37702m2_device::uart0_ctrl_reg0_r), FUNC(m37702m2_device::uart0_ctrl_reg0_w));
- map(0x000035, 0x000035).rw(FUNC(m37702m2_device::uart0_ctrl_reg1_r), FUNC(m37702m2_device::uart0_ctrl_reg1_w));
- map(0x000036, 0x000037).r(FUNC(m37702m2_device::uart0_rbuf_r));
- map(0x000038, 0x000038).rw(FUNC(m37702m2_device::uart1_mode_r), FUNC(m37702m2_device::uart1_mode_w));
- map(0x000039, 0x000039).w(FUNC(m37702m2_device::uart1_baud_w));
- map(0x00003a, 0x00003b).w(FUNC(m37702m2_device::uart1_tbuf_w));
- map(0x00003c, 0x00003c).rw(FUNC(m37702m2_device::uart1_ctrl_reg0_r), FUNC(m37702m2_device::uart1_ctrl_reg0_w));
- map(0x00003d, 0x00003d).rw(FUNC(m37702m2_device::uart1_ctrl_reg1_r), FUNC(m37702m2_device::uart1_ctrl_reg1_w));
- map(0x00003e, 0x00003f).r(FUNC(m37702m2_device::uart1_rbuf_r));
- map(0x000040, 0x000040).rw(FUNC(m37702m2_device::count_start_r), FUNC(m37702m2_device::count_start_w));
- map(0x000042, 0x000042).w(FUNC(m37702m2_device::one_shot_start_w));
- map(0x000044, 0x000044).rw(FUNC(m37702m2_device::up_down_r), FUNC(m37702m2_device::up_down_w));
- map(0x000046, 0x000055).rw(FUNC(m37702m2_device::timer_reg_r), FUNC(m37702m2_device::timer_reg_w));
- map(0x000056, 0x00005d).rw(FUNC(m37702m2_device::timer_mode_r), FUNC(m37702m2_device::timer_mode_w));
+ map(0x000000, 0x00007f).noprw();
+ map(0x000002, 0x000015).rw(FUNC(m37702m2_device::port_r<0>), FUNC(m37702m2_device::port_w<0>)).umask16(0x00ff);
+ map(0x000002, 0x000011).rw(FUNC(m37702m2_device::port_r<1>), FUNC(m37702m2_device::port_w<1>)).umask16(0xff00);
map(0x00005e, 0x00005e).rw(FUNC(m37702m2_device::proc_mode_r), FUNC(m37702m2_device::proc_mode_w));
map(0x000060, 0x000060).w(FUNC(m37702m2_device::watchdog_timer_w));
map(0x000061, 0x000061).rw(FUNC(m37702m2_device::watchdog_freq_r), FUNC(m37702m2_device::watchdog_freq_w));
- map(0x00006c, 0x00007f).rw(FUNC(m37702m2_device::int_control_r), FUNC(m37702m2_device::int_control_w));
+ ad_register_map(map);
+ uart0_register_map(map);
+ uart1_register_map(map);
+ timer_register_map(map);
+ irq_register_map(map);
map(0x000080, 0x00027f).ram();
map(0x00c000, 0x00ffff).rom().region(M37710_INTERNAL_ROM_REGION, 0);
}
@@ -118,31 +229,17 @@ void m37702m2_device::map(address_map &map)
// M37702S1: 512 bytes internal RAM, no internal ROM
void m37702s1_device::map(address_map &map)
{
- map(0x000002, 0x000015).rw(FUNC(m37702s1_device::port_r), FUNC(m37702s1_device::port_w));
- map(0x00001e, 0x00001e).rw(FUNC(m37702s1_device::ad_control_r), FUNC(m37702s1_device::ad_control_w));
- map(0x00001f, 0x00001f).rw(FUNC(m37702s1_device::ad_sweep_r), FUNC(m37702s1_device::ad_sweep_w));
- map(0x000020, 0x00002f).r(FUNC(m37702s1_device::ad_result_r));
- map(0x000030, 0x000030).rw(FUNC(m37702s1_device::uart0_mode_r), FUNC(m37702s1_device::uart0_mode_w));
- map(0x000031, 0x000031).w(FUNC(m37702s1_device::uart0_baud_w));
- map(0x000032, 0x000033).w(FUNC(m37702s1_device::uart0_tbuf_w));
- map(0x000034, 0x000034).rw(FUNC(m37702s1_device::uart0_ctrl_reg0_r), FUNC(m37702s1_device::uart0_ctrl_reg0_w));
- map(0x000035, 0x000035).rw(FUNC(m37702s1_device::uart0_ctrl_reg1_r), FUNC(m37702s1_device::uart0_ctrl_reg1_w));
- map(0x000036, 0x000037).r(FUNC(m37702s1_device::uart0_rbuf_r));
- map(0x000038, 0x000038).rw(FUNC(m37702s1_device::uart1_mode_r), FUNC(m37702s1_device::uart1_mode_w));
- map(0x000039, 0x000039).w(FUNC(m37702s1_device::uart1_baud_w));
- map(0x00003a, 0x00003b).w(FUNC(m37702s1_device::uart1_tbuf_w));
- map(0x00003c, 0x00003c).rw(FUNC(m37702s1_device::uart1_ctrl_reg0_r), FUNC(m37702s1_device::uart1_ctrl_reg0_w));
- map(0x00003d, 0x00003d).rw(FUNC(m37702s1_device::uart1_ctrl_reg1_r), FUNC(m37702s1_device::uart1_ctrl_reg1_w));
- map(0x00003e, 0x00003f).r(FUNC(m37702s1_device::uart1_rbuf_r));
- map(0x000040, 0x000040).rw(FUNC(m37702s1_device::count_start_r), FUNC(m37702s1_device::count_start_w));
- map(0x000042, 0x000042).w(FUNC(m37702s1_device::one_shot_start_w));
- map(0x000044, 0x000044).rw(FUNC(m37702s1_device::up_down_r), FUNC(m37702s1_device::up_down_w));
- map(0x000046, 0x000055).rw(FUNC(m37702s1_device::timer_reg_r), FUNC(m37702s1_device::timer_reg_w));
- map(0x000056, 0x00005d).rw(FUNC(m37702s1_device::timer_mode_r), FUNC(m37702s1_device::timer_mode_w));
+ map(0x000000, 0x00007f).noprw();
+ map(0x000002, 0x000015).rw(FUNC(m37702s1_device::port_r<0>), FUNC(m37702s1_device::port_w<0>)).umask16(0x00ff);
+ map(0x000002, 0x000011).rw(FUNC(m37702s1_device::port_r<1>), FUNC(m37702s1_device::port_w<1>)).umask16(0xff00);
map(0x00005e, 0x00005e).rw(FUNC(m37702s1_device::proc_mode_r), FUNC(m37702s1_device::proc_mode_w));
map(0x000060, 0x000060).w(FUNC(m37702s1_device::watchdog_timer_w));
map(0x000061, 0x000061).rw(FUNC(m37702s1_device::watchdog_freq_r), FUNC(m37702s1_device::watchdog_freq_w));
- map(0x00006c, 0x00007f).rw(FUNC(m37702s1_device::int_control_r), FUNC(m37702s1_device::int_control_w));
+ ad_register_map(map);
+ uart0_register_map(map);
+ uart1_register_map(map);
+ timer_register_map(map);
+ irq_register_map(map);
map(0x000080, 0x00027f).ram();
}
@@ -150,62 +247,32 @@ void m37702s1_device::map(address_map &map)
// M37710S4: 2048 bytes internal RAM, no internal ROM
void m37710s4_device::map(address_map &map)
{
- map(0x000002, 0x000015).rw(FUNC(m37710s4_device::port_r), FUNC(m37710s4_device::port_w)); // FIXME: P4-P8 only
+ map(0x000000, 0x000001).noprw();
+ map(0x00000a, 0x00007f).noprw();
+ map(0x00000a, 0x000015).rw(FUNC(m37710s4_device::port_r<4>), FUNC(m37710s4_device::port_w<4>)).umask16(0x00ff);
+ map(0x00000a, 0x000011).rw(FUNC(m37710s4_device::port_r<5>), FUNC(m37710s4_device::port_w<5>)).umask16(0xff00);
map(0x00001a, 0x00001d).w(FUNC(m37710s4_device::da_reg_w)).umask16(0x00ff);
- map(0x00001e, 0x00001e).rw(FUNC(m37710s4_device::ad_control_r), FUNC(m37710s4_device::ad_control_w));
- map(0x00001f, 0x00001f).rw(FUNC(m37710s4_device::ad_sweep_r), FUNC(m37710s4_device::ad_sweep_w));
- map(0x000020, 0x00002f).r(FUNC(m37710s4_device::ad_result_r));
- map(0x000030, 0x000030).rw(FUNC(m37710s4_device::uart0_mode_r), FUNC(m37710s4_device::uart0_mode_w));
- map(0x000031, 0x000031).w(FUNC(m37710s4_device::uart0_baud_w));
- map(0x000032, 0x000033).w(FUNC(m37710s4_device::uart0_tbuf_w));
- map(0x000034, 0x000034).rw(FUNC(m37710s4_device::uart0_ctrl_reg0_r), FUNC(m37710s4_device::uart0_ctrl_reg0_w));
- map(0x000035, 0x000035).rw(FUNC(m37710s4_device::uart0_ctrl_reg1_r), FUNC(m37710s4_device::uart0_ctrl_reg1_w));
- map(0x000036, 0x000037).r(FUNC(m37710s4_device::uart0_rbuf_r));
- map(0x000038, 0x000038).rw(FUNC(m37710s4_device::uart1_mode_r), FUNC(m37710s4_device::uart1_mode_w));
- map(0x000039, 0x000039).w(FUNC(m37710s4_device::uart1_baud_w));
- map(0x00003a, 0x00003b).w(FUNC(m37710s4_device::uart1_tbuf_w));
- map(0x00003c, 0x00003c).rw(FUNC(m37710s4_device::uart1_ctrl_reg0_r), FUNC(m37710s4_device::uart1_ctrl_reg0_w));
- map(0x00003d, 0x00003d).rw(FUNC(m37710s4_device::uart1_ctrl_reg1_r), FUNC(m37710s4_device::uart1_ctrl_reg1_w));
- map(0x00003e, 0x00003f).r(FUNC(m37710s4_device::uart1_rbuf_r));
- map(0x000040, 0x000040).rw(FUNC(m37710s4_device::count_start_r), FUNC(m37710s4_device::count_start_w));
- map(0x000042, 0x000042).w(FUNC(m37710s4_device::one_shot_start_w));
- map(0x000044, 0x000044).rw(FUNC(m37710s4_device::up_down_r), FUNC(m37710s4_device::up_down_w));
- map(0x000046, 0x000055).rw(FUNC(m37710s4_device::timer_reg_r), FUNC(m37710s4_device::timer_reg_w));
- map(0x000056, 0x00005d).rw(FUNC(m37710s4_device::timer_mode_r), FUNC(m37710s4_device::timer_mode_w));
map(0x00005e, 0x00005e).rw(FUNC(m37710s4_device::proc_mode_r), FUNC(m37710s4_device::proc_mode_w));
map(0x000060, 0x000060).w(FUNC(m37710s4_device::watchdog_timer_w));
map(0x000061, 0x000061).rw(FUNC(m37710s4_device::watchdog_freq_r), FUNC(m37710s4_device::watchdog_freq_w));
map(0x000062, 0x000062).rw(FUNC(m37710s4_device::waveform_mode_r), FUNC(m37710s4_device::waveform_mode_w));
map(0x000064, 0x000065).w(FUNC(m37710s4_device::pulse_output_w));
- map(0x00006c, 0x00007f).rw(FUNC(m37710s4_device::int_control_r), FUNC(m37710s4_device::int_control_w));
+ ad_register_map(map);
+ uart0_register_map(map);
+ uart1_register_map(map);
+ timer_register_map(map);
+ irq_register_map(map);
map(0x000080, 0x00087f).ram();
}
// M37720S1: 512 bytes internal RAM, no internal ROM, built-in DMA
void m37720s1_device::map(address_map &map)
{
- map(0x000002, 0x000019).rw(FUNC(m37720s1_device::port_r), FUNC(m37720s1_device::port_w)); // FIXME: P4-P10 only
+ map(0x000000, 0x000001).noprw();
+ map(0x00000a, 0x00007f).noprw();
+ map(0x00000a, 0x000019).rw(FUNC(m37720s1_device::port_r<4>), FUNC(m37720s1_device::port_w<4>)).umask16(0x00ff);
+ map(0x00000a, 0x000015).rw(FUNC(m37720s1_device::port_r<5>), FUNC(m37720s1_device::port_w<5>)).umask16(0xff00);
map(0x00001a, 0x00001d).w(FUNC(m37720s1_device::pulse_output_w)).umask16(0x00ff);
- map(0x00001e, 0x00001e).rw(FUNC(m37720s1_device::ad_control_r), FUNC(m37720s1_device::ad_control_w));
- map(0x00001f, 0x00001f).rw(FUNC(m37720s1_device::ad_sweep_r), FUNC(m37720s1_device::ad_sweep_w));
- map(0x000020, 0x00002f).r(FUNC(m37720s1_device::ad_result_r));
- map(0x000030, 0x000030).rw(FUNC(m37720s1_device::uart0_mode_r), FUNC(m37720s1_device::uart0_mode_w));
- map(0x000031, 0x000031).w(FUNC(m37720s1_device::uart0_baud_w));
- map(0x000032, 0x000033).w(FUNC(m37720s1_device::uart0_tbuf_w));
- map(0x000034, 0x000034).rw(FUNC(m37720s1_device::uart0_ctrl_reg0_r), FUNC(m37720s1_device::uart0_ctrl_reg0_w));
- map(0x000035, 0x000035).rw(FUNC(m37720s1_device::uart0_ctrl_reg1_r), FUNC(m37720s1_device::uart0_ctrl_reg1_w));
- map(0x000036, 0x000037).r(FUNC(m37720s1_device::uart0_rbuf_r));
- map(0x000038, 0x000038).rw(FUNC(m37720s1_device::uart1_mode_r), FUNC(m37720s1_device::uart1_mode_w));
- map(0x000039, 0x000039).w(FUNC(m37720s1_device::uart1_baud_w));
- map(0x00003a, 0x00003b).w(FUNC(m37720s1_device::uart1_tbuf_w));
- map(0x00003c, 0x00003c).rw(FUNC(m37720s1_device::uart1_ctrl_reg0_r), FUNC(m37720s1_device::uart1_ctrl_reg0_w));
- map(0x00003d, 0x00003d).rw(FUNC(m37720s1_device::uart1_ctrl_reg1_r), FUNC(m37720s1_device::uart1_ctrl_reg1_w));
- map(0x00003e, 0x00003f).r(FUNC(m37720s1_device::uart1_rbuf_r));
- map(0x000040, 0x000040).rw(FUNC(m37720s1_device::count_start_r), FUNC(m37720s1_device::count_start_w));
- map(0x000042, 0x000042).w(FUNC(m37720s1_device::one_shot_start_w));
- map(0x000044, 0x000044).rw(FUNC(m37720s1_device::up_down_r), FUNC(m37720s1_device::up_down_w));
- map(0x000046, 0x000055).rw(FUNC(m37720s1_device::timer_reg_r), FUNC(m37720s1_device::timer_reg_w));
- map(0x000056, 0x00005d).rw(FUNC(m37720s1_device::timer_mode_r), FUNC(m37720s1_device::timer_mode_w));
map(0x00005e, 0x00005e).rw(FUNC(m37720s1_device::proc_mode_r), FUNC(m37720s1_device::proc_mode_w));
map(0x000060, 0x000060).w(FUNC(m37720s1_device::watchdog_timer_w));
map(0x000061, 0x000061).rw(FUNC(m37720s1_device::watchdog_freq_r), FUNC(m37720s1_device::watchdog_freq_w));
@@ -213,19 +280,65 @@ void m37720s1_device::map(address_map &map)
map(0x000064, 0x000064).rw(FUNC(m37720s1_device::dram_control_r), FUNC(m37720s1_device::dram_control_w));
map(0x000066, 0x000066).w(FUNC(m37720s1_device::refresh_timer_w));
map(0x000068, 0x000069).rw(FUNC(m37720s1_device::dmac_control_r), FUNC(m37720s1_device::dmac_control_w));
- map(0x00006c, 0x00007f).rw(FUNC(m37720s1_device::int_control_r), FUNC(m37720s1_device::int_control_w));
+ map(0x00006c, 0x00006c).rw(FUNC(m37720s1_device::int_control_r<M37710_LINE_DMA0>), FUNC(m37720s1_device::int_control_w<M37710_LINE_DMA0>));
+ map(0x00006d, 0x00006d).rw(FUNC(m37720s1_device::int_control_r<M37710_LINE_DMA1>), FUNC(m37720s1_device::int_control_w<M37710_LINE_DMA1>));
+ map(0x00006e, 0x00006e).rw(FUNC(m37720s1_device::int_control_r<M37710_LINE_DMA2>), FUNC(m37720s1_device::int_control_w<M37710_LINE_DMA2>));
+ map(0x00006f, 0x00006f).rw(FUNC(m37720s1_device::int_control_r<M37710_LINE_DMA3>), FUNC(m37720s1_device::int_control_w<M37710_LINE_DMA3>));
+ ad_register_map(map);
+ uart0_register_map(map);
+ uart1_register_map(map);
+ timer_register_map(map);
+ irq_register_map(map);
map(0x000080, 0x00027f).ram();
}
+// M37730S2: 1024 bytes internal RAM, no internal ROM
+void m37730s2_device::map(address_map &map)
+{
+ map(0x000000, 0x000001).noprw();
+ map(0x00000a, 0x00007f).noprw();
+ map(0x00000a, 0x000015).rw(FUNC(m37730s2_device::port_r<4>), FUNC(m37730s2_device::port_w<4>)).umask16(0x00ff);
+ map(0x00000a, 0x00000d).rw(FUNC(m37730s2_device::port_r<5>), FUNC(m37730s2_device::port_w<5>)).umask16(0xff00);
+ map(0x00005e, 0x00005e).rw(FUNC(m37730s2_device::proc_mode_r), FUNC(m37730s2_device::proc_mode_w));
+ map(0x000060, 0x000060).w(FUNC(m37730s2_device::watchdog_timer_w));
+ map(0x000061, 0x000061).rw(FUNC(m37730s2_device::watchdog_freq_r), FUNC(m37730s2_device::watchdog_freq_w));
+ map(0x000062, 0x000062).rw(FUNC(m37730s2_device::waveform_mode_r), FUNC(m37730s2_device::waveform_mode_w));
+ map(0x000064, 0x000065).w(FUNC(m37730s2_device::pulse_output_w));
+ uart0_register_map(map);
+ timer_6channel_register_map(map);
+ irq_register_map(map);
+ map(0x000080, 0x00047f).ram();
+}
+
+// M37732S4: 2048 bytes internal RAM, no internal ROM
+void m37732s4_device::map(address_map &map)
+{
+ map(0x000000, 0x000001).noprw();
+ map(0x00000a, 0x00007f).noprw();
+ map(0x00000a, 0x000015).rw(FUNC(m37732s4_device::port_r<4>), FUNC(m37732s4_device::port_w<4>)).umask16(0x00ff);
+ map(0x00000a, 0x00000d).rw(FUNC(m37732s4_device::port_r<5>), FUNC(m37732s4_device::port_w<5>)).umask16(0xff00);
+ map(0x00005e, 0x00005e).rw(FUNC(m37732s4_device::proc_mode_r), FUNC(m37732s4_device::proc_mode_w));
+ map(0x000060, 0x000060).w(FUNC(m37732s4_device::watchdog_timer_w));
+ map(0x000061, 0x000061).rw(FUNC(m37732s4_device::watchdog_freq_r), FUNC(m37732s4_device::watchdog_freq_w));
+ map(0x000062, 0x000062).rw(FUNC(m37732s4_device::waveform_mode_r), FUNC(m37732s4_device::waveform_mode_w));
+ map(0x000064, 0x000065).w(FUNC(m37732s4_device::pulse_output_w));
+ ad_register_map(map);
+ uart0_register_map(map);
+ uart1_register_map(map);
+ timer_register_map(map);
+ irq_register_map(map);
+ map(0x000080, 0x00087f).ram();
+}
+
// many other combinations of RAM and ROM size exist
m37710_cpu_device::m37710_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor map_delegate)
: cpu_device(mconfig, type, tag, owner, clock)
, m_program_config("program", ENDIANNESS_LITTLE, 16, 24, 0, map_delegate)
- , m_port_in_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}}
- , m_port_out_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}}
- , m_analog_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}}
+ , m_port_in_cb(*this, 0xff)
+ , m_port_out_cb(*this)
+ , m_analog_cb(*this, 0)
{
}
@@ -258,6 +371,16 @@ m37720s1_device::m37720s1_device(const machine_config &mconfig, const char *tag,
{
}
+m37730s2_device::m37730s2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : m37710_cpu_device(mconfig, M37730S2, tag, owner, clock, address_map_constructor(FUNC(m37730s2_device::map), this))
+{
+}
+
+m37732s4_device::m37732s4_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : m37710_cpu_device(mconfig, M37732S4, tag, owner, clock, address_map_constructor(FUNC(m37732s4_device::map), this))
+{
+}
+
std::vector<std::pair<int, const address_space_config *>> m37710_cpu_device::memory_space_config() const
{
return std::vector<std::pair<int, const address_space_config *>> {
@@ -267,30 +390,6 @@ std::vector<std::pair<int, const address_space_config *>> m37710_cpu_device::mem
/* interrupt control mapping */
-const int m37710_cpu_device::m37710_int_reg_map[M37710_MASKABLE_INTERRUPTS] =
-{
- M37710_LINE_DMA0, // level 3 (0x6c)
- M37710_LINE_DMA1, // level 2 (0x6d)
- M37710_LINE_DMA2, // level 1 (0x6e)
- M37710_LINE_DMA3, // level 0 (0x6f)
- M37710_LINE_ADC, // level 4 (0x70)
- M37710_LINE_UART0XMIT, // level 7 (0x71)
- M37710_LINE_UART0RECV, // level 8 (0x72)
- M37710_LINE_UART1XMIT, // level 5 (0x73)
- M37710_LINE_UART1RECV, // level 6 (0x74)
- M37710_LINE_TIMERA0, // level 16 (0x75)
- M37710_LINE_TIMERA1, // level 15 (0x76)
- M37710_LINE_TIMERA2, // level 14 (0x77)
- M37710_LINE_TIMERA3, // level 13 (0x78)
- M37710_LINE_TIMERA4, // level 12 (0x79)
- M37710_LINE_TIMERB0, // level 11 (0x7a)
- M37710_LINE_TIMERB1, // level 10 (0x7b)
- M37710_LINE_TIMERB2, // level 9 (0x7c)
- M37710_LINE_IRQ0, // level 19 (0x7d)
- M37710_LINE_IRQ1, // level 18 (0x7e)
- M37710_LINE_IRQ2, // level 17 (0x7f)
-};
-
const int m37710_cpu_device::m37710_irq_vectors[M37710_INTERRUPT_MAX] =
{
// maskable
@@ -470,60 +569,49 @@ void m37710_cpu_device::m37710_recalc_timer(int timer)
}
}
-uint8_t m37710_cpu_device::port_r(offs_t offset)
+uint8_t m37710_cpu_device::get_port_reg(int p)
{
- int p = (offset & 0x1c) >> 1 | (offset & 0x01);
+ assert(p >= 0 && p < 11);
- uint8_t result = 0;
- if (p < 11)
- {
- if (BIT(offset, 1))
- result = m_port_dir[p];
- else
- {
- uint8_t d = m_port_dir[p];
- if (d != 0xff)
- result = (m_port_in_cb[p](0, ~d) & ~d) | (m_port_regs[p] & d);
- else
- result = m_port_regs[p];
- }
- }
+ uint8_t d = m_port_dir[p];
+ if (d != 0xff)
+ return (m_port_in_cb[p](0, ~d) & ~d) | (m_port_regs[p] & d);
+ else
+ return m_port_regs[p];
+}
- LOGMASKED(LOG_PORTS, "port_r from %02x: Port P%d %s = %x\n", (int)offset + 0x02, p, BIT(offset, 1) ? "dir reg" : "reg", result);
+uint8_t m37710_cpu_device::get_port_dir(int p)
+{
+ assert(p >= 0 && p < 11);
- return result;
+ return m_port_dir[p];
}
-void m37710_cpu_device::port_w(offs_t offset, uint8_t data)
+void m37710_cpu_device::set_port_reg(int p, uint8_t data)
{
- int p = (offset & 0x1c) >> 1 | (offset & 0x01);
+ assert(p >= 0 && p < 11);
- if (p < 11)
- {
- LOGMASKED(LOG_PORTS, "port_w %x to %02x: Port P%d %s = %x\n", data, (int)offset + 0x02, p,
- BIT(offset, 1) ? "dir reg" : "reg",
- BIT(offset, 1) ? m_port_dir[p] : m_port_regs[p]);
+ uint8_t d = m_port_dir[p];
+ if (d != 0)
+ m_port_out_cb[p](0, data & d, d);
+ m_port_regs[p] = data;
+}
- if (BIT(offset, 1))
- m_port_dir[p] = data;
- else
- {
- uint8_t d = m_port_dir[p];
- if (d != 0)
- m_port_out_cb[p](0, data & d, d);
- m_port_regs[p] = data;
- }
- }
+void m37710_cpu_device::set_port_dir(int p, uint8_t data)
+{
+ assert(p >= 0 && p < 11);
+
+ m_port_dir[p] = data;
}
void m37710_cpu_device::da_reg_w(offs_t offset, uint8_t data)
{
- LOGMASKED(LOG_GENERAL, "da_reg_w %x to %02X: D/A %d\n", data, (int)(offset * 2) + 0x1a, offset);
+ LOG("da_reg_w %x to %02X: D/A %d\n", data, (int)(offset * 2) + 0x1a, offset);
}
void m37710_cpu_device::pulse_output_w(offs_t offset, uint8_t data)
{
- LOGMASKED(LOG_GENERAL, "pulse_output_w %x: Pulse output data register %d\n", data, offset);
+ LOG("pulse_output_w %x: Pulse output data register %d\n", data, offset);
}
uint8_t m37710_cpu_device::ad_control_r()
@@ -588,14 +676,14 @@ uint16_t m37710_cpu_device::ad_result_r(offs_t offset)
{
uint16_t result = m_ad_result[offset];
- LOGMASKED(LOG_AD, "ad_result_r from %02x: A/D %d = %x (PC=%x)\n", (int)(offset * 2) + 0x20, offset, result, REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_AD, "ad_result_r from %02x: A/D %d = %x (PC=%x)\n", (int)(offset * 2) + 0x20, offset, result, REG_PG | REG_PC);
return result;
}
uint8_t m37710_cpu_device::uart0_mode_r()
{
- LOGMASKED(LOG_UART, "uart0_mode_r: UART0 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[0], REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_UART, "uart0_mode_r: UART0 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[0], REG_PG | REG_PC);
return m_uart_mode[0];
}
@@ -609,7 +697,7 @@ void m37710_cpu_device::uart0_mode_w(uint8_t data)
uint8_t m37710_cpu_device::uart1_mode_r()
{
- LOGMASKED(LOG_UART, "uart1_mode_r: UART1 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[1], REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_UART, "uart1_mode_r: UART1 transmit/recv mode = %x (PC=%x)\n", m_uart_mode[1], REG_PG | REG_PC);
return m_uart_mode[1];
}
@@ -647,7 +735,7 @@ void m37710_cpu_device::uart1_tbuf_w(uint16_t data)
uint8_t m37710_cpu_device::uart0_ctrl_reg0_r()
{
- LOGMASKED(LOG_UART, "uart0_ctrl_reg0_r: UART0 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[0], REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_UART, "uart0_ctrl_reg0_r: UART0 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[0], REG_PG | REG_PC);
return m_uart_ctrl_reg0[0];
}
@@ -662,7 +750,7 @@ void m37710_cpu_device::uart0_ctrl_reg0_w(uint8_t data)
uint8_t m37710_cpu_device::uart1_ctrl_reg0_r()
{
- LOGMASKED(LOG_UART, "uart1_ctrl_reg0_r: UART1 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[1], REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_UART, "uart1_ctrl_reg0_r: UART1 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[1], REG_PG | REG_PC);
return m_uart_ctrl_reg0[1];
}
@@ -677,7 +765,7 @@ void m37710_cpu_device::uart1_ctrl_reg0_w(uint8_t data)
uint8_t m37710_cpu_device::uart0_ctrl_reg1_r()
{
- LOGMASKED(LOG_UART, "uart0_ctrl_reg1_r: UART0 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[0], REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_UART, "uart0_ctrl_reg1_r: UART0 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[0], REG_PG | REG_PC);
return m_uart_ctrl_reg1[0];
}
@@ -691,7 +779,7 @@ void m37710_cpu_device::uart0_ctrl_reg1_w(uint8_t data)
uint8_t m37710_cpu_device::uart1_ctrl_reg1_r()
{
- LOGMASKED(LOG_UART, "uart1_ctrl_reg1_r: UART1 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[1], REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_UART, "uart1_ctrl_reg1_r: UART1 transmit/recv ctrl 1 = %x (PC=%x)\n", m_uart_ctrl_reg1[1], REG_PG | REG_PC);
return m_uart_ctrl_reg1[1];
}
@@ -705,21 +793,21 @@ void m37710_cpu_device::uart1_ctrl_reg1_w(uint8_t data)
uint16_t m37710_cpu_device::uart0_rbuf_r()
{
- LOGMASKED(LOG_UART, "uart0_rbuf_r: UART0 recv buf (PC=%x)\n", REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_UART, "uart0_rbuf_r: UART0 recv buf (PC=%x)\n", REG_PG | REG_PC);
return 0;
}
uint16_t m37710_cpu_device::uart1_rbuf_r()
{
- LOGMASKED(LOG_UART, "uart1_rbuf_r: UART1 recv buf (PC=%x)\n", REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_UART, "uart1_rbuf_r: UART1 recv buf (PC=%x)\n", REG_PG | REG_PC);
return 0;
}
uint8_t m37710_cpu_device::count_start_r()
{
- LOGMASKED(LOG_TIMER, "count_start_r: Count start = %x (PC=%x)\n", m_count_start, REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_TIMER, "count_start_r: Count start = %x (PC=%x)\n", m_count_start, REG_PG | REG_PC);
return m_count_start;
}
@@ -745,7 +833,7 @@ void m37710_cpu_device::one_shot_start_w(uint8_t data)
uint8_t m37710_cpu_device::up_down_r()
{
- LOGMASKED(LOG_TIMER, "up_down_r: Up-down register = %x (PC=%x)\n", m_up_down_reg, REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_TIMER, "up_down_r: Up-down register = %x (PC=%x)\n", m_up_down_reg, REG_PG | REG_PC);
// bits 7-5 read back as 0
return m_up_down_reg & 0x1f;
@@ -772,7 +860,7 @@ void m37710_cpu_device::timer_reg_w(offs_t offset, uint16_t data, uint16_t mem_m
uint8_t m37710_cpu_device::timer_mode_r(offs_t offset)
{
- LOGMASKED(LOG_TIMER, "timer_mode_r from %02x: Timer %s mode = %x (PC=%x)\n", (int)offset + 0x56, m37710_tnames[offset], m_timer_mode[offset], REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_TIMER, "timer_mode_r from %02x: Timer %s mode = %x (PC=%x)\n", (int)offset + 0x56, m37710_tnames[offset], m_timer_mode[offset], REG_PG | REG_PC);
return m_timer_mode[offset];
}
@@ -786,14 +874,14 @@ void m37710_cpu_device::timer_mode_w(offs_t offset, uint8_t data)
uint8_t m37710_cpu_device::proc_mode_r(offs_t offset)
{
- LOGMASKED(LOG_GENERAL, "proc_mode_r: Processor mode = %x (PC=%x)\n", m_proc_mode, REG_PB<<16 | REG_PC);
+ LOG("proc_mode_r: Processor mode = %x (PC=%x)\n", m_proc_mode, REG_PG | REG_PC);
return m_proc_mode & 0xf7;
}
void m37710_cpu_device::proc_mode_w(uint8_t data)
{
- LOGMASKED(LOG_GENERAL, "proc_mode_w %x: Processor mode = %x\n", data, m_proc_mode);
+ LOG("proc_mode_w %x: Processor mode = %x\n", data, m_proc_mode);
m_proc_mode = data;
}
@@ -810,54 +898,54 @@ uint8_t m37710_cpu_device::watchdog_freq_r()
void m37710_cpu_device::watchdog_freq_w(uint8_t data)
{
- LOGMASKED(LOG_GENERAL, "watchdog_freq_w %x: Watchdog timer frequency = %x\n", data, m_watchdog_freq);
+ LOG("watchdog_freq_w %x: Watchdog timer frequency = %x\n", data, m_watchdog_freq);
m_watchdog_freq = data;
}
uint8_t m37710_cpu_device::waveform_mode_r()
{
- LOGMASKED(LOG_GENERAL, "waveform_mode_r: Waveform output mode (PC=%x)\n", REG_PB<<16 | REG_PC);
+ LOG("waveform_mode_r: Waveform output mode (PC=%x)\n", REG_PG | REG_PC);
return 0;
}
void m37710_cpu_device::waveform_mode_w(uint8_t data)
{
- LOGMASKED(LOG_GENERAL, "waveform_mode_w %x: Waveform output mode\n", data);
+ LOG("waveform_mode_w %x: Waveform output mode\n", data);
}
uint8_t m37710_cpu_device::rto_control_r()
{
- LOGMASKED(LOG_GENERAL, "rto_control_r: Real-time output control = %x (PC=%x)\n", m_rto_control, REG_PB<<16 | REG_PC);
+ LOG("rto_control_r: Real-time output control = %x (PC=%x)\n", m_rto_control, REG_PG | REG_PC);
return m_rto_control;
}
void m37710_cpu_device::rto_control_w(uint8_t data)
{
- LOGMASKED(LOG_GENERAL, "rto_control_w %x: Real-time output control = %x\n", data, m_rto_control);
+ LOG("rto_control_w %x: Real-time output control = %x\n", data, m_rto_control);
m_rto_control = data;
}
uint8_t m37710_cpu_device::dram_control_r()
{
- LOGMASKED(LOG_GENERAL, "dram_control_r: DRAM control = %x (PC=%x)\n", m_dram_control, REG_PB<<16 | REG_PC);
+ LOG("dram_control_r: DRAM control = %x (PC=%x)\n", m_dram_control, REG_PG | REG_PC);
return m_dram_control;
}
void m37710_cpu_device::dram_control_w(uint8_t data)
{
- LOGMASKED(LOG_GENERAL, "dram_control_w %x: DRAM control = %x\n", data, m_dram_control);
+ LOG("dram_control_w %x: DRAM control = %x\n", data, m_dram_control);
m_dram_control = data;
}
void m37710_cpu_device::refresh_timer_w(uint8_t data)
{
- LOGMASKED(LOG_GENERAL, "refresh_timer_w %x: Set refresh timer\n", data);
+ LOG("refresh_timer_w %x: Set refresh timer\n", data);
}
uint16_t m37710_cpu_device::dmac_control_r(offs_t offset, uint16_t mem_mask)
@@ -867,29 +955,27 @@ uint16_t m37710_cpu_device::dmac_control_r(offs_t offset, uint16_t mem_mask)
void m37710_cpu_device::dmac_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
- LOGMASKED(LOG_GENERAL, "dmac_control_w %04x & %04x: DMAC control = %04x\n", data, mem_mask, m_dmac_control);
+ LOG("dmac_control_w %04x & %04x: DMAC control = %04x\n", data, mem_mask, m_dmac_control);
m_dmac_control = (data & mem_mask) | (m_timer_reg[offset] & ~mem_mask);
}
-uint8_t m37710_cpu_device::int_control_r(offs_t offset)
+uint8_t m37710_cpu_device::get_int_control(int level)
{
- assert(offset < M37710_MASKABLE_INTERRUPTS);
- int level = m37710_int_reg_map[offset];
+ assert(level < M37710_MASKABLE_INTERRUPTS);
- //LOGMASKED(LOG_INT, "int_control_r from %02x: %s IRQ ctrl = %x (PC=%x)\n", (int)offset + 0x6c, m37710_intnames[level], m_int_control[level], REG_PB<<16 | REG_PC);
+ //LOGMASKED(LOG_INT, "int_control_r: %s IRQ ctrl = %x (PC=%x)\n", m37710_intnames[level], m_int_control[level], REG_PG | REG_PC);
uint8_t result = m_int_control[level];
return result;
}
-void m37710_cpu_device::int_control_w(offs_t offset, uint8_t data)
+void m37710_cpu_device::set_int_control(int level, uint8_t data)
{
- assert(offset < M37710_MASKABLE_INTERRUPTS);
- int level = m37710_int_reg_map[offset];
+ assert(level < M37710_MASKABLE_INTERRUPTS);
- LOGMASKED(LOG_INT, "int_control_w %x to %02x: %s IRQ ctrl = %x\n", data, (int)offset + 0x6c, m37710_intnames[level], m_int_control[level]);
+ LOGMASKED(LOG_INT, "int_control_w %x: %s IRQ ctrl = %x\n", data, m37710_intnames[level], m_int_control[level]);
m_int_control[level] = data;
@@ -971,7 +1057,7 @@ void m37710_cpu_device::m37710i_update_irqs()
if (!FLAG_I && thispri > curpri && thispri > m_ipl)
{
// mark us as the best candidate
- LOGMASKED(LOG_INT, "%s interrupt active with priority %d (PC=%x)\n", m37710_intnames[curirq], thispri, REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_INT, "%s interrupt active with priority %d (PC=%x)\n", m37710_intnames[curirq], thispri, REG_PG | REG_PC);
wantedIRQ = curirq;
curpri = thispri;
}
@@ -979,7 +1065,7 @@ void m37710_cpu_device::m37710i_update_irqs()
else
{
// non-maskable
- LOGMASKED(LOG_INT, "%s interrupt active (PC=%x)\n", m37710_intnames[curirq], REG_PB<<16 | REG_PC);
+ LOGMASKED(LOG_INT, "%s interrupt active (PC=%x)\n", m37710_intnames[curirq], REG_PG | REG_PC);
wantedIRQ = curirq;
curpri = 7;
break; // no more processing, NMIs always win
@@ -989,7 +1075,7 @@ void m37710_cpu_device::m37710i_update_irqs()
if (wantedIRQ != -1)
{
- standard_irq_callback(wantedIRQ);
+ standard_irq_callback(wantedIRQ, REG_PG | REG_PC);
// make sure we're running to service the interrupt
CPU_STOPPED &= ~STOP_LEVEL_WAI;
@@ -1000,16 +1086,16 @@ void m37710_cpu_device::m37710i_update_irqs()
// let's do it...
// push PB, then PC, then status
CLK(13);
- m37710i_push_8(REG_PB>>16);
+ m37710i_push_8(REG_PG>>16);
m37710i_push_16(REG_PC);
m37710i_push_8(m_ipl);
- m37710i_push_8(m37710i_get_reg_p());
+ m37710i_push_8(m37710i_get_reg_ps());
// set I to 1, set IPL to the interrupt we're taking
FLAG_I = IFLAG_SET;
m_ipl = curpri;
- // then PB=0, PC=(vector)
- REG_PB = 0;
+ // then PG=0, PC=(vector)
+ REG_PG = 0;
REG_PC = m37710_read_16(m37710_irq_vectors[wantedIRQ]);
}
}
@@ -1077,9 +1163,9 @@ void m37710_cpu_device::device_reset()
IRQ_DELAY = 0;
/* 37710 boots in full native mode */
- REG_D = 0;
- REG_PB = 0;
- REG_DB = 0;
+ REG_DPR = 0;
+ REG_PG = 0;
+ REG_DT = 0;
REG_S = (REG_S & 0xff) | 0x100;
REG_XH = REG_X & 0xff00; REG_X &= 0xff;
REG_YH = REG_Y & 0xff00; REG_Y &= 0xff;
@@ -1214,9 +1300,9 @@ void m37710_cpu_device::device_start()
m_s = 0;
m_pc = 0;
m_ppc = 0;
- m_pb = 0;
- m_db = 0;
- m_d = 0;
+ m_pg = 0;
+ m_dt = 0;
+ m_dpr = 0;
m_flag_e = 0;
m_flag_m = 0;
m_flag_x = 0;
@@ -1253,15 +1339,8 @@ void m37710_cpu_device::device_start()
m_watchdog_freq = 0;
std::fill(std::begin(m_int_control), std::end(m_int_control), 0);
- m_program = &space(AS_PROGRAM);
- m_cache = m_program->cache<1, 0, ENDIANNESS_LITTLE>();
-
- for (auto &cb : m_port_in_cb)
- cb.resolve_safe(0xff);
- for (auto &cb : m_port_out_cb)
- cb.resolve_safe();
- for (auto &cb : m_analog_cb)
- cb.resolve_safe(0);
+ space(AS_PROGRAM).cache(m_cache);
+ space(AS_PROGRAM).specific(m_program);
m_ICount = 0;
@@ -1270,12 +1349,12 @@ void m37710_cpu_device::device_start()
for (int i = 0; i < 8; i++)
{
- m_timers[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(m37710_cpu_device::m37710_timer_cb), this));
+ m_timers[i] = timer_alloc(FUNC(m37710_cpu_device::m37710_timer_cb), this);
m_reload[i] = attotime::never;
m_timer_out[i] = 0;
}
- m_ad_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(m37710_cpu_device::ad_timer_cb), this));
+ m_ad_timer = timer_alloc(FUNC(m37710_cpu_device::ad_timer_cb), this);
save_item(NAME(m_a));
save_item(NAME(m_b));
@@ -1288,9 +1367,9 @@ void m37710_cpu_device::device_start()
save_item(NAME(m_s));
save_item(NAME(m_pc));
save_item(NAME(m_ppc));
- save_item(NAME(m_pb));
- save_item(NAME(m_db));
- save_item(NAME(m_d));
+ save_item(NAME(m_pg));
+ save_item(NAME(m_dt));
+ save_item(NAME(m_dpr));
save_item(NAME(m_flag_e));
save_item(NAME(m_flag_m));
save_item(NAME(m_flag_x));
@@ -1339,11 +1418,11 @@ void m37710_cpu_device::device_start()
machine().save().register_postload(save_prepost_delegate(save_prepost_delegate(FUNC(m37710_cpu_device::m37710_restore_state), this)));
state_add( M37710_PC, "PC", m_pc).formatstr("%04X");
- state_add( M37710_PB, "PB", m_debugger_pb).callimport().callexport().formatstr("%02X");
- state_add( M37710_DB, "DB", m_debugger_db).callimport().callexport().formatstr("%02X");
- state_add( M37710_D, "D", m_d).formatstr("%04X");
+ state_add( M37710_PG, "PG", m_debugger_pg).callimport().callexport().formatstr("%02X");
+ state_add( M37710_DT, "DT", m_debugger_dt).callimport().callexport().formatstr("%02X");
+ state_add( M37710_DPR, "DPR", m_dpr).formatstr("%04X");
state_add( M37710_S, "S", m_s).formatstr("%04X");
- state_add( M37710_P, "P", m_debugger_p).callimport().callexport().formatstr("%04X");
+ state_add( M37710_PS, "PS", m_debugger_ps).callimport().callexport().formatstr("%04X");
state_add( M37710_E, "E", m_flag_e).formatstr("%01X");
state_add( M37710_A, "A", m_debugger_a).callimport().callexport().formatstr("%04X");
state_add( M37710_B, "B", m_debugger_b).callimport().callexport().formatstr("%04X");
@@ -1353,7 +1432,7 @@ void m37710_cpu_device::device_start()
state_add( STATE_GENPC, "GENPC", m_debugger_pc ).callimport().callexport().noshow();
state_add( STATE_GENPCBASE, "CURPC", m_debugger_pc ).callimport().callexport().noshow();
- state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_p ).formatstr("%8s").noshow();
+ state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_ps ).formatstr("%8s").noshow();
set_icountptr(m_ICount);
}
@@ -1363,17 +1442,17 @@ void m37710_cpu_device::state_import(const device_state_entry &entry)
{
switch (entry.index())
{
- case M37710_PB:
- m37710_set_reg(M37710_PB, m_debugger_pb);
+ case M37710_PG:
+ m37710_set_reg(M37710_PG, m_debugger_pg);
break;
- case M37710_DB:
- m37710_set_reg(M37710_DB, m_debugger_db);
+ case M37710_DT:
+ m37710_set_reg(M37710_DT, m_debugger_dt);
break;
- case M37710_P:
- m37710_set_reg(M37710_P, m_debugger_p&0xff);
- m_ipl = (m_debugger_p>>8)&0xff;
+ case M37710_PS:
+ m37710_set_reg(M37710_PS, m_debugger_ps&0xff);
+ m_ipl = (m_debugger_ps>>8)&0xff;
break;
case M37710_A:
@@ -1386,7 +1465,7 @@ void m37710_cpu_device::state_import(const device_state_entry &entry)
case STATE_GENPC:
case STATE_GENPCBASE:
- REG_PB = m_debugger_pc & 0xff0000;
+ REG_PG = m_debugger_pc & 0xff0000;
m37710_set_pc(m_debugger_pc & 0xffff);
break;
}
@@ -1397,16 +1476,16 @@ void m37710_cpu_device::state_export(const device_state_entry &entry)
{
switch (entry.index())
{
- case M37710_PB:
- m_debugger_pb = m_pb >> 16;
+ case M37710_PG:
+ m_debugger_pg = m_pg >> 16;
break;
- case M37710_DB:
- m_debugger_db = m_db >> 16;
+ case M37710_DT:
+ m_debugger_dt = m_dt >> 16;
break;
- case M37710_P:
- m_debugger_p = (m_flag_n&0x80) | ((m_flag_v>>1)&0x40) | m_flag_m | m_flag_x | m_flag_d | m_flag_i | ((!m_flag_z)<<1) | ((m_flag_c>>8)&1) | (m_ipl<<8);
+ case M37710_PS:
+ m_debugger_ps = (m_flag_n&0x80) | ((m_flag_v>>1)&0x40) | m_flag_m | m_flag_x | m_flag_d | m_flag_i | ((!m_flag_z)<<1) | ((m_flag_c>>8)&1) | (m_ipl<<8);
break;
case M37710_A:
@@ -1419,7 +1498,7 @@ void m37710_cpu_device::state_export(const device_state_entry &entry)
case STATE_GENPC:
case STATE_GENPCBASE:
- m_debugger_pc = (REG_PB | REG_PC);
+ m_debugger_pc = (REG_PG | REG_PC);
break;
}
}
@@ -1498,12 +1577,12 @@ void m37710_cpu_device::m37710i_set_execution_mode(uint32_t mode)
void m37710_cpu_device::m37710i_interrupt_software(uint32_t vector)
{
CLK(13);
- m37710i_push_8(REG_PB>>16);
+ m37710i_push_8(REG_PG>>16);
m37710i_push_16(REG_PC);
m37710i_push_8(m_ipl);
- m37710i_push_8(m37710i_get_reg_p());
+ m37710i_push_8(m37710i_get_reg_ps());
FLAG_I = IFLAG_SET;
- REG_PB = 0;
+ REG_PG = 0;
REG_PC = m37710_read_16(vector);
}