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-rw-r--r--src/devices/cpu/h8/h8.cpp111
-rw-r--r--src/devices/cpu/h8/h8.h38
-rw-r--r--src/devices/cpu/h8/h8.lst69
-rw-r--r--src/devices/cpu/h8/h83002.cpp11
-rw-r--r--src/devices/cpu/h8/h83002.h4
-rw-r--r--src/devices/cpu/h8/h83006.cpp15
-rw-r--r--src/devices/cpu/h8/h83006.h4
-rw-r--r--src/devices/cpu/h8/h83008.cpp10
-rw-r--r--src/devices/cpu/h8/h83008.h4
-rw-r--r--src/devices/cpu/h8/h83048.cpp16
-rw-r--r--src/devices/cpu/h8/h83048.h4
-rw-r--r--src/devices/cpu/h8/h83337.cpp20
-rw-r--r--src/devices/cpu/h8/h83337.h4
-rw-r--r--src/devices/cpu/h8/h8_adc.cpp21
-rw-r--r--src/devices/cpu/h8/h8_dma.cpp320
-rw-r--r--src/devices/cpu/h8/h8_dma.h127
-rw-r--r--src/devices/cpu/h8/h8_dtc.cpp269
-rw-r--r--src/devices/cpu/h8/h8_dtc.h74
-rw-r--r--src/devices/cpu/h8/h8_intc.cpp26
-rw-r--r--src/devices/cpu/h8/h8_port.cpp16
-rw-r--r--src/devices/cpu/h8/h8_sci.cpp163
-rw-r--r--src/devices/cpu/h8/h8_sci.h1
-rw-r--r--src/devices/cpu/h8/h8_timer16.cpp108
-rw-r--r--src/devices/cpu/h8/h8_timer8.cpp45
-rw-r--r--src/devices/cpu/h8/h8_watchdog.cpp125
-rw-r--r--src/devices/cpu/h8/h8_watchdog.h99
-rw-r--r--src/devices/cpu/h8/h8s2000.h4
-rw-r--r--src/devices/cpu/h8/h8s2245.cpp255
-rw-r--r--src/devices/cpu/h8/h8s2245.h11
-rw-r--r--src/devices/cpu/h8/h8s2320.cpp320
-rw-r--r--src/devices/cpu/h8/h8s2320.h12
-rw-r--r--src/devices/cpu/h8/h8s2357.cpp16
-rw-r--r--src/devices/cpu/h8/h8s2357.h6
-rw-r--r--src/devices/cpu/h8/h8s2655.cpp14
-rw-r--r--src/devices/cpu/h8/h8s2655.h4
35 files changed, 1862 insertions, 484 deletions
diff --git a/src/devices/cpu/h8/h8.cpp b/src/devices/cpu/h8/h8.cpp
index 36da1c92f17..efaac3c3380 100644
--- a/src/devices/cpu/h8/h8.cpp
+++ b/src/devices/cpu/h8/h8.cpp
@@ -12,6 +12,8 @@
#include "emu.h"
#include "debugger.h"
#include "h8.h"
+#include "h8_dma.h"
+#include "h8_dtc.h"
h8_device::h8_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, bool mode_a16, address_map_delegate map_delegate) :
cpu_device(mconfig, type, name, tag, owner, clock, shortname, source),
@@ -69,14 +71,14 @@ void h8_device::device_start()
state_add(H8_E5, "E5", R[13]).noshow();
state_add(H8_E6, "E6", R[14]).noshow();
state_add(H8_E7, "E7", R[15]).noshow();
- state_add(H8_R0, "ER0", TMPR).callimport().formatstr("%9s");
- state_add(H8_R1, "ER1", TMPR).callimport().formatstr("%9s");
- state_add(H8_R2, "ER2", TMPR).callimport().formatstr("%9s");
- state_add(H8_R3, "ER3", TMPR).callimport().formatstr("%9s");
- state_add(H8_R4, "ER4", TMPR).callimport().formatstr("%9s");
- state_add(H8_R5, "ER5", TMPR).callimport().formatstr("%9s");
- state_add(H8_R6, "ER6", TMPR).callimport().formatstr("%9s");
- state_add(H8_R7, "ER7", TMPR).callimport().formatstr("%9s");
+ state_add(H8_R0, "ER0", TMPR).callimport().callexport().formatstr("%9s");
+ state_add(H8_R1, "ER1", TMPR).callimport().callexport().formatstr("%9s");
+ state_add(H8_R2, "ER2", TMPR).callimport().callexport().formatstr("%9s");
+ state_add(H8_R3, "ER3", TMPR).callimport().callexport().formatstr("%9s");
+ state_add(H8_R4, "ER4", TMPR).callimport().callexport().formatstr("%9s");
+ state_add(H8_R5, "ER5", TMPR).callimport().callexport().formatstr("%9s");
+ state_add(H8_R6, "ER6", TMPR).callimport().callexport().formatstr("%9s");
+ state_add(H8_R7, "ER7", TMPR).callimport().callexport().formatstr("%9s");
}
save_item(NAME(PPC));
@@ -110,20 +112,54 @@ void h8_device::device_start()
MACF = 0;
inst_state = STATE_RESET;
inst_substate = 0;
+ count_before_instruction_step = 0;
+ requested_state = -1;
+ dma_device = NULL;
+ dtc_device = NULL;
}
void h8_device::device_reset()
{
inst_state = STATE_RESET;
inst_substate = 0;
+ count_before_instruction_step = 0;
+ requested_state = -1;
irq_vector = 0;
irq_level = -1;
irq_nmi = false;
taken_irq_vector = 0;
taken_irq_level = -1;
+ current_dma = NULL;
+ current_dtc = NULL;
}
+bool h8_device::trigger_dma(int vector)
+{
+ return (dma_device && dma_device->trigger_dma(vector)) || (dtc_device && dtc_device->trigger_dtc(vector));
+}
+
+void h8_device::set_current_dma(h8_dma_state *state)
+{
+ current_dma = state;
+ if(!state)
+ logerror("DMA done\n");
+ else
+ logerror("New current dma s=%x d=%x is=%d id=%d count=%x m=%d\n",
+ state->source, state->dest, state->incs, state->incd,
+ state->count, state->mode_16 ? 16 : 8);
+
+}
+
+void h8_device::set_current_dtc(h8_dtc_state *state)
+{
+ current_dtc = state;
+}
+
+void h8_device::request_state(int state)
+{
+ requested_state = state;
+}
UINT32 h8_device::execute_min_cycles() const
{
@@ -153,7 +189,17 @@ void h8_device::execute_run()
{
internal_update(total_cycles());
- if(inst_substate)
+ icount -= count_before_instruction_step;
+ if(icount < 0) {
+ count_before_instruction_step = -icount;
+ icount = 0;
+ } else
+ count_before_instruction_step = 0;
+
+ while(bcount && icount <= bcount)
+ internal_update(total_cycles() + icount - bcount);
+
+ if(icount > 0 && inst_substate)
do_exec_partial();
while(icount > 0) {
@@ -165,11 +211,16 @@ void h8_device::execute_run()
}
do_exec_full();
}
- while(bcount && icount && icount <= bcount)
- internal_update(total_cycles() + icount - bcount);
- if(inst_substate)
+ if(icount > 0)
+ while(bcount && icount <= bcount)
+ internal_update(total_cycles() + icount - bcount);
+ if(icount > 0 && inst_substate)
do_exec_partial();
}
+ if(icount < 0) {
+ count_before_instruction_step = -icount;
+ icount = 0;
+ }
}
void h8_device::add_event(UINT64 &event_time, UINT64 new_event)
@@ -214,6 +265,20 @@ void h8_device::state_import(const device_state_entry &entry)
void h8_device::state_export(const device_state_entry &entry)
{
+ switch(entry.index()) {
+ case H8_R0:
+ case H8_R1:
+ case H8_R2:
+ case H8_R3:
+ case H8_R4:
+ case H8_R5:
+ case H8_R6:
+ case H8_R7: {
+ int r = entry.index() - H8_R0;
+ TMPR = (R[r + 8] << 16) | R[r];
+ break;
+ }
+ }
}
void h8_device::state_string_export(const device_state_entry &entry, std::string &str) const
@@ -269,7 +334,7 @@ UINT32 h8_device::disasm_max_opcode_bytes() const
return 10;
}
-void h8_device::disassemble_am(char *&buffer, int am, offs_t pc, const UINT8 *oprom, UINT32 opcode, int offset)
+void h8_device::disassemble_am(char *&buffer, int am, offs_t pc, const UINT8 *oprom, UINT32 opcode, int slot, int offset)
{
static const char *const r8_names[16] = {
"r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h",
@@ -394,7 +459,7 @@ void h8_device::disassemble_am(char *&buffer, int am, offs_t pc, const UINT8 *op
break;
case DASM_abs32:
- if(offset >= 8)
+ if(slot == 3)
buffer += sprintf(buffer, "@%08x", (oprom[offset-6] << 24) | (oprom[offset-5] << 16) | (oprom[offset-4] << 8) | oprom[offset-3]);
else
buffer += sprintf(buffer, "@%08x", (oprom[offset-4] << 24) | (oprom[offset-3] << 16) | (oprom[offset-2] << 8) | oprom[offset-1]);
@@ -494,12 +559,12 @@ offs_t h8_device::disassemble_generic(char *buffer, offs_t pc, const UINT8 *opro
if(e.am1 != DASM_none) {
*buffer++ = ' ';
- disassemble_am(buffer, e.am1, pc, oprom, slot[e.slot], e.flags & DASMFLAG_LENGTHMASK);
+ disassemble_am(buffer, e.am1, pc, oprom, slot[e.slot], e.slot, e.flags & DASMFLAG_LENGTHMASK);
}
if(e.am2 != DASM_none) {
*buffer++ = ',';
*buffer++ = ' ';
- disassemble_am(buffer, e.am2, pc, oprom, slot[e.slot], e.flags & DASMFLAG_LENGTHMASK);
+ disassemble_am(buffer, e.am2, pc, oprom, slot[e.slot], e.slot, e.flags & DASMFLAG_LENGTHMASK);
}
return e.flags | DASMFLAG_SUPPORTED;
}
@@ -530,7 +595,6 @@ UINT8 h8_device::read8(UINT32 adr)
void h8_device::write8(UINT32 adr, UINT8 data)
{
- // logerror("W %06x %02x\n", adr & 0xffffff, data);
icount--;
program->write_byte(adr, data);
}
@@ -543,7 +607,6 @@ UINT16 h8_device::read16(UINT32 adr)
void h8_device::write16(UINT32 adr, UINT16 data)
{
- // logerror("W %06x %04x\n", adr & 0xfffffe, data);
icount--;
program->write_word(adr & ~1, data);
}
@@ -555,7 +618,14 @@ bool h8_device::exr_in_stack() const
void h8_device::prefetch_done()
{
- if(irq_vector) {
+ if(requested_state != -1) {
+ inst_state = requested_state;
+ requested_state = -1;
+ } else if(current_dma)
+ inst_state = STATE_DMA;
+ else if(current_dtc)
+ inst_state = STATE_DTC;
+ else if(irq_vector) {
inst_state = STATE_IRQ;
taken_irq_vector = irq_vector;
taken_irq_level = irq_level;
@@ -592,7 +662,8 @@ void h8_device::internal(int cycles)
void h8_device::illegal()
{
- throw emu_fatalerror("%s: Illegal instruction at address %x\n", tag(), PPC);
+ logerror("Illegal instruction at address %x\n", PPC);
+ icount = -10000000;
}
int h8_device::trace_setup()
diff --git a/src/devices/cpu/h8/h8.h b/src/devices/cpu/h8/h8.h
index 8ed2bee2796..be466fae2d2 100644
--- a/src/devices/cpu/h8/h8.h
+++ b/src/devices/cpu/h8/h8.h
@@ -12,6 +12,11 @@
#ifndef __H8_H__
#define __H8_H__
+class h8_dma_device;
+class h8_dtc_device;
+struct h8_dma_state;
+struct h8_dtc_state;
+
class h8_device : public cpu_device {
public:
enum {
@@ -46,11 +51,25 @@ public:
ADC_7
};
+ enum {
+ STATE_RESET = 0x10000,
+ STATE_IRQ = 0x10001,
+ STATE_TRACE = 0x10002,
+ STATE_DMA = 0x10003,
+ STATE_DTC = 0x10004,
+ STATE_DTC_VECTOR = 0x10005,
+ STATE_DTC_WRITEBACK = 0x10006
+ };
+
h8_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, bool mode_a16, address_map_delegate map_delegate);
void internal_update();
-
void set_irq(int irq_vector, int irq_level, bool irq_nmi);
+ bool trigger_dma(int vector);
+ void set_current_dma(h8_dma_state *state);
+ void set_current_dtc(h8_dtc_state *state);
+ void request_state(int state);
+ bool access_is_dma() const { return inst_state == STATE_DMA || inst_state == STATE_DTC; }
protected:
struct disasm_entry {
@@ -63,12 +82,6 @@ protected:
};
enum {
- STATE_RESET = 0x10000,
- STATE_IRQ = 0x10001,
- STATE_TRACE = 0x10002
- };
-
- enum {
F_I = 0x80,
F_UI = 0x40,
F_H = 0x20,
@@ -167,6 +180,10 @@ protected:
address_space_config program_config, io_config;
address_space *program, *io;
direct_read_data *direct;
+ h8_dma_device *dma_device;
+ h8_dtc_device *dtc_device;
+ h8_dma_state *current_dma;
+ h8_dtc_state *current_dtc;
UINT32 PPC; /* previous program counter */
UINT32 NPC; /* next start-of-instruction program counter */
@@ -183,8 +200,8 @@ protected:
bool has_exr, has_trace, supports_advanced, mode_advanced, mac_saturating;
- int inst_state, inst_substate;
- int icount, bcount;
+ int inst_state, inst_substate, requested_state;
+ int icount, bcount, count_before_instruction_step;
int irq_vector, taken_irq_vector;
int irq_level, taken_irq_level;
bool irq_required, irq_nmi;
@@ -192,7 +209,7 @@ protected:
static const disasm_entry disasm_entries[];
offs_t disassemble_generic(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options, const disasm_entry *table);
- void disassemble_am(char *&buffer, int am, offs_t pc, const UINT8 *oprom, UINT32 opcode, int offset);
+ void disassemble_am(char *&buffer, int am, offs_t pc, const UINT8 *oprom, UINT32 opcode, int slot, int offset);
virtual void do_exec_full();
virtual void do_exec_partial();
@@ -447,6 +464,7 @@ protected:
O(state_reset);
O(state_irq);
+ O(state_dma);
#undef O
};
diff --git a/src/devices/cpu/h8/h8.lst b/src/devices/cpu/h8/h8.lst
index 56fcd25a548..4763ca6f2cc 100644
--- a/src/devices/cpu/h8/h8.lst
+++ b/src/devices/cpu/h8/h8.lst
@@ -175,6 +175,75 @@ macro jsr32 %opc %spreg
internal(1);
prefetch_noirq();
+10003 dma
+ if(current_dma->mode_16) {
+ TMP1 = read16(current_dma->source);
+ write16(current_dma->dest, TMP1);
+ } else {
+ TMP1 = read8(current_dma->source);
+ write8(current_dma->dest, TMP1);
+ }
+ current_dma->source += current_dma->incs;
+ current_dma->dest += current_dma->incd;
+ current_dma->count--;
+ if(!current_dma->count) {
+ UINT8 id = current_dma->id;
+ current_dma = nullptr;
+ dma_device->count_done(id);
+ }
+ prefetch_done();
+
+10004 dtc s20
+ if(current_dtc->sra & 0x01000000) {
+ TMP1 = read16(current_dtc->sra & 0xffffff);
+ write16(current_dtc->dar & 0xffffff, TMP1);
+ } else {
+ TMP1 = read8(current_dtc->sra & 0xffffff);
+ write8(current_dtc->dar & 0xffffff, TMP1);
+ }
+ current_dtc->sra = (current_dtc->sra & 0xff000000) | ((current_dtc->sra + current_dtc->incs) & 0x00ffffff);
+ current_dtc->dar = (current_dtc->dar & 0xff000000) | ((current_dtc->dar + current_dtc->incd) & 0x00ffffff);
+ current_dtc->count--;
+ if(!current_dtc->count) {
+ UINT8 id = current_dtc->id;
+ current_dtc = nullptr;
+ dtc_device->count_done(id);
+ }
+ prefetch_done();
+
+10005 dtc_vector s20
+ TMP1 = dtc_device->get_waiting_vector();
+ if(TMP1 < h8_dtc_device::DTC_CHAINED) {
+ TMP2 = dtc_device->get_vector_address(TMP1);
+ TMP2 = read16(TMP2);
+ TMP2 |= 0xff0000;
+ } else {
+ TMP1 -= h8_dtc_device::DTC_CHAINED;
+ TMP2 = dtc_device->get_object(TMP1)->base + 12;
+ }
+
+ dtc_device->get_object(TMP1)->base = TMP2;
+ dtc_device->get_object(TMP1)->sra = read16(TMP2) << 16;
+ dtc_device->get_object(TMP1)->sra |= read16(TMP2+2);
+ dtc_device->get_object(TMP1)->dar = read16(TMP2+4) << 16;
+ dtc_device->get_object(TMP1)->dar |= read16(TMP2+6);
+ dtc_device->get_object(TMP1)->cr = read16(TMP2+8) << 16;
+ dtc_device->get_object(TMP1)->cr |= read16(TMP2+10);
+ dtc_device->vector_done(TMP1);
+ prefetch_done();
+
+10006 dtc_writeback s20
+ TMP1 = dtc_device->get_waiting_writeback();
+ TMP2 = dtc_device->get_object(TMP1)->base;
+ write16(TMP2, dtc_device->get_object(TMP1)->sra >> 16);
+ write16(TMP2+2, dtc_device->get_object(TMP1)->sra);
+ write16(TMP2+4, dtc_device->get_object(TMP1)->dar >> 16);
+ write16(TMP2+6, dtc_device->get_object(TMP1)->dar);
+ write16(TMP2+8, dtc_device->get_object(TMP1)->cr >> 16);
+ write16(TMP2+10, dtc_device->get_object(TMP1)->cr);
+ dtc_device->writeback_done(TMP1);
+ prefetch_done();
+
0000 ffff 0 nop - -
prefetch();
diff --git a/src/devices/cpu/h8/h83002.cpp b/src/devices/cpu/h8/h83002.cpp
index 96fc201dfab..0b9a8036983 100644
--- a/src/devices/cpu/h8/h83002.cpp
+++ b/src/devices/cpu/h8/h83002.cpp
@@ -23,8 +23,10 @@ h83002_device::h83002_device(const machine_config &mconfig, const char *tag, dev
timer16_3(*this, "timer16:3"),
timer16_4(*this, "timer16:4"),
sci0(*this, "sci0"),
- sci1(*this, "sci1"), syscr(0)
+ sci1(*this, "sci1"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
}
static MACHINE_CONFIG_FRAGMENT(h83002)
@@ -45,6 +47,7 @@ static MACHINE_CONFIG_FRAGMENT(h83002)
MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:4", 2, 2, "intc", 40)
MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
+ MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
MACHINE_CONFIG_END
DEVICE_ADDRESS_MAP_START(map, 16, h83002_device)
@@ -89,6 +92,9 @@ DEVICE_ADDRESS_MAP_START(map, 16, h83002_device)
AM_RANGE(0xffff98, 0xffff9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
AM_RANGE(0xffff9c, 0xffff9f) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tbr_r, tbr_w )
+ AM_RANGE(0xffffa8, 0xffffa9) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
+ AM_RANGE(0xffffaa, 0xffffab) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
+
AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
@@ -191,6 +197,7 @@ void h83002_device::internal_update(UINT64 current_time)
add_event(event_time, timer16_2->internal_update(current_time));
add_event(event_time, timer16_3->internal_update(current_time));
add_event(event_time, timer16_4->internal_update(current_time));
+ add_event(event_time, watchdog->internal_update(current_time));
recompute_bcount(event_time);
}
@@ -215,5 +222,5 @@ WRITE8_MEMBER(h83002_device::syscr_w)
{
syscr = data;
update_irq_filter();
- logerror("%s: syscr = %02x\n", tag(), data);
+ logerror("syscr = %02x\n", data);
}
diff --git a/src/devices/cpu/h8/h83002.h b/src/devices/cpu/h8/h83002.h
index 860aee68ccc..64e38f43897 100644
--- a/src/devices/cpu/h8/h83002.h
+++ b/src/devices/cpu/h8/h83002.h
@@ -18,8 +18,9 @@
#include "h8_adc.h"
#include "h8_port.h"
#include "h8_intc.h"
-#include "h8_sci.h"
#include "h8_timer16.h"
+#include "h8_sci.h"
+#include "h8_watchdog.h"
class h83002_device : public h8h_device {
public:
@@ -46,6 +47,7 @@ protected:
required_device<h8h_timer16_channel_device> timer16_4;
required_device<h8_sci_device> sci0;
required_device<h8_sci_device> sci1;
+ required_device<h8_watchdog_device> watchdog;
UINT8 syscr;
diff --git a/src/devices/cpu/h8/h83006.cpp b/src/devices/cpu/h8/h83006.cpp
index 431d257a4b4..04c51cd720c 100644
--- a/src/devices/cpu/h8/h83006.cpp
+++ b/src/devices/cpu/h8/h83006.cpp
@@ -28,8 +28,11 @@ h83006_device::h83006_device(const machine_config &mconfig, device_type type, co
timer16_2(*this, "timer16:2"),
sci0(*this, "sci0"),
sci1(*this, "sci1"),
- sci2(*this, "sci2"), syscr(0), ram_start(0)
+ sci2(*this, "sci2"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
+ ram_start = 0;
}
h83006_device::h83006_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
@@ -53,8 +56,10 @@ h83006_device::h83006_device(const machine_config &mconfig, const char *tag, dev
timer16_2(*this, "timer16:2"),
sci0(*this, "sci0"),
sci1(*this, "sci1"),
- sci2(*this, "sci2"), syscr(0)
+ sci2(*this, "sci2"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
ram_start = 0xfff720;
}
@@ -86,6 +91,7 @@ static MACHINE_CONFIG_FRAGMENT(h83006)
MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
MCFG_H8_SCI_ADD("sci2", "intc", 60, 61, 62, 63)
+ MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
MACHINE_CONFIG_END
DEVICE_ADDRESS_MAP_START(map, 16, h83006_device)
@@ -132,6 +138,8 @@ DEVICE_ADDRESS_MAP_START(map, 16, h83006_device)
AM_RANGE(0xffff84, 0xffff87) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
+ AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
+ AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_3", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
AM_RANGE(0xffff92, 0xffff93) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
@@ -242,6 +250,7 @@ void h83006_device::internal_update(UINT64 current_time)
add_event(event_time, timer16_0->internal_update(current_time));
add_event(event_time, timer16_1->internal_update(current_time));
add_event(event_time, timer16_2->internal_update(current_time));
+ add_event(event_time, watchdog->internal_update(current_time));
recompute_bcount(event_time);
}
@@ -267,5 +276,5 @@ WRITE8_MEMBER(h83006_device::syscr_w)
{
syscr = data;
update_irq_filter();
- logerror("%s: syscr = %02x\n", tag(), data);
+ logerror("syscr = %02x\n", data);
}
diff --git a/src/devices/cpu/h8/h83006.h b/src/devices/cpu/h8/h83006.h
index bb2fe644a47..34427c94644 100644
--- a/src/devices/cpu/h8/h83006.h
+++ b/src/devices/cpu/h8/h83006.h
@@ -18,9 +18,10 @@
#include "h8_adc.h"
#include "h8_port.h"
#include "h8_intc.h"
-#include "h8_sci.h"
#include "h8_timer8.h"
#include "h8_timer16.h"
+#include "h8_sci.h"
+#include "h8_watchdog.h"
class h83006_device : public h8h_device {
public:
@@ -51,6 +52,7 @@ protected:
required_device<h8_sci_device> sci0;
required_device<h8_sci_device> sci1;
required_device<h8_sci_device> sci2;
+ required_device<h8_watchdog_device> watchdog;
UINT8 syscr;
UINT32 ram_start;
diff --git a/src/devices/cpu/h8/h83008.cpp b/src/devices/cpu/h8/h83008.cpp
index 33b49317a89..abc7d49ec97 100644
--- a/src/devices/cpu/h8/h83008.cpp
+++ b/src/devices/cpu/h8/h83008.cpp
@@ -25,8 +25,10 @@ h83008_device::h83008_device(const machine_config &mconfig, const char *tag, dev
timer16_1(*this, "timer16:1"),
timer16_2(*this, "timer16:2"),
sci0(*this, "sci0"),
- sci1(*this, "sci1"), syscr(0)
+ sci1(*this, "sci1"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
}
static MACHINE_CONFIG_FRAGMENT(h83008)
@@ -49,6 +51,7 @@ static MACHINE_CONFIG_FRAGMENT(h83008)
MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:2", 2, 2, "intc", 32)
MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
+ MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
MACHINE_CONFIG_END
DEVICE_ADDRESS_MAP_START(map, 16, h83008_device)
@@ -95,6 +98,8 @@ DEVICE_ADDRESS_MAP_START(map, 16, h83008_device)
AM_RANGE(0xffff84, 0xffff87) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
+ AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
+ AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_3", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
AM_RANGE(0xffff92, 0xffff93) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
@@ -197,6 +202,7 @@ void h83008_device::internal_update(UINT64 current_time)
add_event(event_time, timer16_0->internal_update(current_time));
add_event(event_time, timer16_1->internal_update(current_time));
add_event(event_time, timer16_2->internal_update(current_time));
+ add_event(event_time, watchdog->internal_update(current_time));
recompute_bcount(event_time);
}
@@ -222,5 +228,5 @@ WRITE8_MEMBER(h83008_device::syscr_w)
{
syscr = data;
update_irq_filter();
- logerror("%s: syscr = %02x\n", tag(), data);
+ logerror("syscr = %02x\n", data);
}
diff --git a/src/devices/cpu/h8/h83008.h b/src/devices/cpu/h8/h83008.h
index 8a19568f43f..e3f9a50054d 100644
--- a/src/devices/cpu/h8/h83008.h
+++ b/src/devices/cpu/h8/h83008.h
@@ -18,9 +18,10 @@
#include "h8_adc.h"
#include "h8_port.h"
#include "h8_intc.h"
-#include "h8_sci.h"
#include "h8_timer8.h"
#include "h8_timer16.h"
+#include "h8_sci.h"
+#include "h8_watchdog.h"
class h83008_device : public h8h_device {
public:
@@ -49,6 +50,7 @@ protected:
required_device<h8h_timer16_channel_device> timer16_2;
required_device<h8_sci_device> sci0;
required_device<h8_sci_device> sci1;
+ required_device<h8_watchdog_device> watchdog;
UINT8 syscr;
diff --git a/src/devices/cpu/h8/h83048.cpp b/src/devices/cpu/h8/h83048.cpp
index 0cad91b1d72..9fb781d465f 100644
--- a/src/devices/cpu/h8/h83048.cpp
+++ b/src/devices/cpu/h8/h83048.cpp
@@ -30,8 +30,11 @@ h83048_device::h83048_device(const machine_config &mconfig, device_type type, co
timer16_3(*this, "timer16:3"),
timer16_4(*this, "timer16:4"),
sci0(*this, "sci0"),
- sci1(*this, "sci1"), ram_start(0), syscr(0)
+ sci1(*this, "sci1"),
+ watchdog(*this, "watchdog")
{
+ ram_start = 0;
+ syscr = 0;
}
h83048_device::h83048_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
@@ -56,8 +59,10 @@ h83048_device::h83048_device(const machine_config &mconfig, const char *tag, dev
timer16_3(*this, "timer16:3"),
timer16_4(*this, "timer16:4"),
sci0(*this, "sci0"),
- sci1(*this, "sci1")
+ sci1(*this, "sci1"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
ram_start = 0xffef10;
}
@@ -101,6 +106,7 @@ static MACHINE_CONFIG_FRAGMENT(h83048)
MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:4", 2, 2, "intc", 40)
MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
+ MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
MACHINE_CONFIG_END
DEVICE_ADDRESS_MAP_START(map, 16, h83048_device)
@@ -145,6 +151,9 @@ DEVICE_ADDRESS_MAP_START(map, 16, h83048_device)
AM_RANGE(0xffff98, 0xffff9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
AM_RANGE(0xffff9c, 0xffff9f) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tbr_r, tbr_w )
+ AM_RANGE(0xffffa8, 0xffffa9) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
+ AM_RANGE(0xffffaa, 0xffffab) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
+
AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
@@ -258,6 +267,7 @@ void h83048_device::internal_update(UINT64 current_time)
add_event(event_time, timer16_2->internal_update(current_time));
add_event(event_time, timer16_3->internal_update(current_time));
add_event(event_time, timer16_4->internal_update(current_time));
+ add_event(event_time, watchdog->internal_update(current_time));
recompute_bcount(event_time);
}
@@ -282,5 +292,5 @@ WRITE8_MEMBER(h83048_device::syscr_w)
{
syscr = data;
update_irq_filter();
- logerror("%s: syscr = %02x\n", tag(), data);
+ logerror("syscr = %02x\n", data);
}
diff --git a/src/devices/cpu/h8/h83048.h b/src/devices/cpu/h8/h83048.h
index e29af57fb3e..34cb2358f3b 100644
--- a/src/devices/cpu/h8/h83048.h
+++ b/src/devices/cpu/h8/h83048.h
@@ -26,8 +26,9 @@
#include "h8_adc.h"
#include "h8_port.h"
#include "h8_intc.h"
-#include "h8_sci.h"
#include "h8_timer16.h"
+#include "h8_sci.h"
+#include "h8_watchdog.h"
class h83048_device : public h8h_device {
public:
@@ -59,6 +60,7 @@ protected:
required_device<h8h_timer16_channel_device> timer16_4;
required_device<h8_sci_device> sci0;
required_device<h8_sci_device> sci1;
+ required_device<h8_watchdog_device> watchdog;
UINT32 ram_start;
UINT8 syscr;
diff --git a/src/devices/cpu/h8/h83337.cpp b/src/devices/cpu/h8/h83337.cpp
index dc0e4c50bb2..b325fc75496 100644
--- a/src/devices/cpu/h8/h83337.cpp
+++ b/src/devices/cpu/h8/h83337.cpp
@@ -26,8 +26,11 @@ h83337_device::h83337_device(const machine_config &mconfig, device_type type, co
timer16(*this, "timer16"),
timer16_0(*this, "timer16:0"),
sci0(*this, "sci0"),
- sci1(*this, "sci1"), syscr(0), ram_start(0)
+ sci1(*this, "sci1"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
+ ram_start = 0;
}
h83337_device::h83337_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
@@ -48,8 +51,10 @@ h83337_device::h83337_device(const machine_config &mconfig, const char *tag, dev
timer16(*this, "timer16"),
timer16_0(*this, "timer16:0"),
sci0(*this, "sci0"),
- sci1(*this, "sci1"), syscr(0)
+ sci1(*this, "sci1"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
ram_start = 0xf780;
}
@@ -83,6 +88,7 @@ static MACHINE_CONFIG_FRAGMENT(h83337)
MCFG_H8_TIMER16_CHANNEL_ADD("timer16:0", 4, 0, "intc", 32)
MCFG_H8_SCI_ADD("sci0", "intc", 27, 28, 29, 30)
MCFG_H8_SCI_ADD("sci1", "intc", 31, 32, 33, 34)
+ MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 36, h8_watchdog_device::B)
MACHINE_CONFIG_END
DEVICE_ADDRESS_MAP_START(map, 16, h83337_device)
@@ -102,6 +108,7 @@ DEVICE_ADDRESS_MAP_START(map, 16, h83337_device)
// AM_RANGE(0xff96, 0xff97) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tocr_r, tocr_w, 0x00ff)
AM_RANGE(0xff98, 0xff9f) AM_DEVREAD( "timer16:0", h8_timer16_channel_device, tgr_r )
+ AM_RANGE(0xffa8, 0xffa9) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
AM_RANGE(0xffac, 0xffad) AM_DEVREADWRITE8("port1", h8_port_device, pcr_r, pcr_w, 0xff00)
AM_RANGE(0xffac, 0xffad) AM_DEVREADWRITE8("port2", h8_port_device, pcr_r, pcr_w, 0x00ff)
AM_RANGE(0xffae, 0xffaf) AM_DEVREADWRITE8("port3", h8_port_device, pcr_r, pcr_w, 0xff00)
@@ -188,6 +195,7 @@ void h83337_device::internal_update(UINT64 current_time)
add_event(event_time, timer8_0->internal_update(current_time));
add_event(event_time, timer8_1->internal_update(current_time));
add_event(event_time, timer16_0->internal_update(current_time));
+ add_event(event_time, watchdog->internal_update(current_time));
recompute_bcount(event_time);
}
@@ -211,7 +219,7 @@ READ8_MEMBER(h83337_device::syscr_r)
WRITE8_MEMBER(h83337_device::syscr_w)
{
syscr = data;
- logerror("%s: syscr = %02x\n", tag(), data);
+ logerror("syscr = %02x\n", data);
}
READ8_MEMBER(h83337_device::wscr_r)
@@ -221,7 +229,7 @@ READ8_MEMBER(h83337_device::wscr_r)
WRITE8_MEMBER(h83337_device::wscr_w)
{
- logerror("%s: wscr = %02x\n", tag(), data);
+ logerror("wscr = %02x\n", data);
}
READ8_MEMBER(h83337_device::stcr_r)
@@ -231,7 +239,7 @@ READ8_MEMBER(h83337_device::stcr_r)
WRITE8_MEMBER(h83337_device::stcr_w)
{
- logerror("%s: stcr = %02x\n", tag(), data);
+ logerror("stcr = %02x\n", data);
timer8_0->set_extra_clock_bit(data & 0x01);
timer8_1->set_extra_clock_bit(data & 0x02);
}
@@ -243,5 +251,5 @@ READ8_MEMBER(h83337_device::mdcr_r)
WRITE8_MEMBER(h83337_device::mdcr_w)
{
- logerror("%s: mdcr = %02x\n", tag(), data);
+ logerror("mdcr = %02x\n", data);
}
diff --git a/src/devices/cpu/h8/h83337.h b/src/devices/cpu/h8/h83337.h
index 9ece1765979..9862ca00347 100644
--- a/src/devices/cpu/h8/h83337.h
+++ b/src/devices/cpu/h8/h83337.h
@@ -22,12 +22,13 @@
#define __H83337_H__
#include "h8.h"
+#include "h8_intc.h"
#include "h8_adc.h"
#include "h8_port.h"
-#include "h8_intc.h"
#include "h8_timer8.h"
#include "h8_timer16.h"
#include "h8_sci.h"
+#include "h8_watchdog.h"
class h83337_device : public h8_device {
public:
@@ -61,6 +62,7 @@ protected:
required_device<h8_timer16_channel_device> timer16_0;
required_device<h8_sci_device> sci0;
required_device<h8_sci_device> sci1;
+ required_device<h8_watchdog_device> watchdog;
UINT8 syscr;
UINT32 ram_start;
diff --git a/src/devices/cpu/h8/h8_adc.cpp b/src/devices/cpu/h8/h8_adc.cpp
index 7e76bf28114..7207c917ea9 100644
--- a/src/devices/cpu/h8/h8_adc.cpp
+++ b/src/devices/cpu/h8/h8_adc.cpp
@@ -3,6 +3,11 @@
#include "emu.h"
#include "h8_adc.h"
+// Verbosity level
+// 0 = no messages
+// 1 = everything
+const int V = 0;
+
const device_type H8_ADC_3337 = &device_creator<h8_adc_3337_device>;
const device_type H8_ADC_3006 = &device_creator<h8_adc_3006_device>;
const device_type H8_ADC_2245 = &device_creator<h8_adc_2245_device>;
@@ -27,31 +32,31 @@ void h8_adc_device::set_info(const char *_intc_tag, int _intc_vector)
READ8_MEMBER(h8_adc_device::addr8_r)
{
- logerror("%s: addr8_r %d %03x\n", tag(), offset, addr[offset >> 1]);
+ if(V>=1) logerror("addr8_r %d %03x\n", offset, addr[offset >> 1]);
return offset & 1 ? addr[offset >> 1] >> 2 : addr[offset >> 1] << 6;
}
READ16_MEMBER(h8_adc_device::addr16_r)
{
- logerror("%s: addr16_r %d %03x\n", tag(), offset, addr[offset]);
+ if(V>=1) logerror("addr16_r %d %03x\n", offset, addr[offset]);
return addr[offset];
}
READ8_MEMBER(h8_adc_device::adcsr_r)
{
- logerror("%s: adcsr_r %02x\n", tag(), adcsr);
+ if(V>=1) logerror("adcsr_r %02x\n", adcsr);
return adcsr;
}
READ8_MEMBER(h8_adc_device::adcr_r)
{
- logerror("%s: adcr_r %02x\n", tag(), adcr);
+ if(V>=1) logerror("adcr_r %02x\n", adcr);
return adcr;
}
WRITE8_MEMBER(h8_adc_device::adcsr_w)
{
- logerror("%s: adcsr_w %02x\n", tag(), data);
+ if(V>=1) logerror("adcsr_w %02x\n", data);
UINT8 prev = adcsr;
adcsr = (data & 0x7f) | (adcsr & data & F_ADF);
mode_update();
@@ -72,7 +77,7 @@ WRITE8_MEMBER(h8_adc_device::adcsr_w)
WRITE8_MEMBER(h8_adc_device::adcr_w)
{
- logerror("%s: adcr_w %02x\n", tag(), data);
+ if(V>=1) logerror("adcr_w %02x\n", data);
adcr = data;
mode_update();
}
@@ -163,13 +168,13 @@ void h8_adc_device::conversion_wait(bool first, bool poweron, UINT64 current_tim
void h8_adc_device::buffer_value(int port, int buffer)
{
buf[buffer] = io->read_word(2*(h8_device::ADC_0 + port));
- logerror("%s: adc buffer %d -> %d:%03x\n", tag(), port, buffer, buf[buffer]);
+ if(V>=1) logerror("adc buffer %d -> %d:%03x\n", port, buffer, buf[buffer]);
}
void h8_adc_device::commit_value(int reg, int buffer)
{
reg &= register_mask;
- logerror("%s: adc commit %d -> %d:%03x\n", tag(), buffer, reg, buf[buffer]);
+ if(V>=1) logerror("adc commit %d -> %d:%03x\n", buffer, reg, buf[buffer]);
addr[reg] = buf[buffer];
}
diff --git a/src/devices/cpu/h8/h8_dma.cpp b/src/devices/cpu/h8/h8_dma.cpp
new file mode 100644
index 00000000000..637e1a98b5c
--- /dev/null
+++ b/src/devices/cpu/h8/h8_dma.cpp
@@ -0,0 +1,320 @@
+#include "emu.h"
+#include "h8_dma.h"
+
+const device_type H8_DMA = &device_creator<h8_dma_device>;
+const device_type H8_DMA_CHANNEL = &device_creator<h8_dma_channel_device>;
+
+h8_dma_device::h8_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
+ device_t(mconfig, H8_DMA, "H8 DMA controller", tag, owner, clock, "h8_dma", __FILE__),
+ dmach0(*this, "0"),
+ dmach1(*this, "1")
+{
+}
+
+void h8_dma_device::device_start()
+{
+ dmach0->set_id(0<<1);
+ dmach1->set_id(1<<1);
+}
+
+void h8_dma_device::device_reset()
+{
+ dmabcr = 0x0000;
+ dmawer = 0x00;
+}
+
+bool h8_dma_device::trigger_dma(int vector)
+{
+ // Don't shortcut! Both dmas may be started
+ bool start0 = dmach0->start_test(vector);
+ bool start1 = dmach1->start_test(vector);
+
+ return start0 || start1;
+}
+
+void h8_dma_device::count_done(int id)
+{
+ if(id & 2)
+ dmach1->count_done(id & 1);
+ else
+ dmach0->count_done(id & 1);
+}
+
+void h8_dma_device::clear_dte(int id)
+{
+ dmabcr &= ~(0x0010 << id);
+}
+
+READ8_MEMBER(h8_dma_device::dmawer_r)
+{
+ logerror("dmawer_r %02x\n", dmawer);
+ return dmawer;
+}
+
+WRITE8_MEMBER(h8_dma_device::dmawer_w)
+{
+ dmawer = data;
+ logerror("dmawer_w %02x\n", data);
+}
+
+READ8_MEMBER(h8_dma_device::dmatcr_r)
+{
+ logerror("dmatcr_r %02x\n", dmatcr);
+ return dmatcr;
+}
+
+WRITE8_MEMBER(h8_dma_device::dmatcr_w)
+{
+ dmatcr = data;
+ logerror("dmatcr_w %02x\n", data);
+}
+
+READ16_MEMBER(h8_dma_device::dmabcr_r)
+{
+ logerror("dmabcr_r %04x\n", dmabcr);
+ return dmabcr;
+}
+
+WRITE16_MEMBER(h8_dma_device::dmabcr_w)
+{
+ COMBINE_DATA(&dmabcr);
+ logerror("dmabcr_w %04x\n", dmabcr);
+ dmach0->set_bcr(dmabcr & 0x4000, dmabcr & 0x1000, dmabcr >> 8, dmabcr >> 4, dmabcr >> 0);
+ dmach1->set_bcr(dmabcr & 0x8000, dmabcr & 0x2000, dmabcr >> 10, dmabcr >> 6, dmabcr >> 2);
+}
+
+
+
+h8_dma_channel_device::h8_dma_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
+ device_t(mconfig, H8_DMA_CHANNEL, "H8 DMA channel", tag, owner, clock, "h8_dma_channel", __FILE__),
+ dmac(*this, "^"),
+ cpu(*this, "^^")
+{
+}
+
+void h8_dma_channel_device::set_info(const char *_intc, int _irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf)
+{
+ intc_tag = _intc;
+ irq_base = _irq_base;
+ activation_vectors[ 0] = v0;
+ activation_vectors[ 1] = v1;
+ activation_vectors[ 2] = v2;
+ activation_vectors[ 3] = v3;
+ activation_vectors[ 4] = v4;
+ activation_vectors[ 5] = v5;
+ activation_vectors[ 6] = v6;
+ activation_vectors[ 7] = v7;
+ activation_vectors[ 8] = v8;
+ activation_vectors[ 9] = v9;
+ activation_vectors[10] = va;
+ activation_vectors[11] = vb;
+ activation_vectors[12] = vc;
+ activation_vectors[13] = vd;
+ activation_vectors[14] = ve;
+ activation_vectors[15] = vf;
+ memset(state, 0, sizeof(state));
+}
+
+void h8_dma_channel_device::device_start()
+{
+}
+
+void h8_dma_channel_device::device_reset()
+{
+ dmacr = 0x0000;
+ mar[0] = mar[1] = 0;
+ ioar[0] = ioar[1] = 0;
+ etcr[0] = etcr[1] = 0;
+ fae = sae = false;
+ dta = dte = dtie = 0;
+}
+
+void h8_dma_channel_device::set_id(int id)
+{
+ state[0].id = id;
+ state[1].id = id | 1;
+
+}
+
+READ16_MEMBER(h8_dma_channel_device::marah_r)
+{
+ logerror("marah_r %06x\n", mar[0]);
+ return mar[0] >> 16;
+}
+
+WRITE16_MEMBER(h8_dma_channel_device::marah_w)
+{
+ if(ACCESSING_BITS_0_7)
+ mar[0] = ((data & 0x00ff) << 16) | (mar[0] & 0xffff);
+ logerror("marah_w %06x\n", mar[0]);
+}
+
+READ16_MEMBER(h8_dma_channel_device::maral_r)
+{
+ logerror("maral_r %06x\n", mar[0]);
+ return mar[0];
+}
+
+WRITE16_MEMBER(h8_dma_channel_device::maral_w)
+{
+ mar[0] = (mar[0] & ~mem_mask) | (data & mem_mask);
+ logerror("maral_w %06x\n", mar[0]);
+}
+
+READ16_MEMBER(h8_dma_channel_device::ioara_r)
+{
+ logerror("iorar_r %04x\n", ioar[0]);
+ return ioar[0];
+}
+
+WRITE16_MEMBER(h8_dma_channel_device::ioara_w)
+{
+ COMBINE_DATA(&ioar[0]);
+ logerror("ioara_w %04x\n", ioar[0]);
+}
+
+READ16_MEMBER(h8_dma_channel_device::etcra_r)
+{
+ logerror("etcra_r %04x\n", etcr[0]);
+ return etcr[0];
+}
+
+WRITE16_MEMBER(h8_dma_channel_device::etcra_w)
+{
+ COMBINE_DATA(&etcr[0]);
+ logerror("etcra_w %04x\n", etcr[0]);
+}
+
+READ16_MEMBER(h8_dma_channel_device::marbh_r)
+{
+ logerror("marbh_r %06x\n", mar[1]);
+ return mar[1] >> 16;
+}
+
+WRITE16_MEMBER(h8_dma_channel_device::marbh_w)
+{
+ if(ACCESSING_BITS_0_7)
+ mar[1] = ((data & 0x00ff) << 16) | (mar[1] & 0xffff);
+ logerror("marbh_w %06x\n", mar[1]);
+}
+
+READ16_MEMBER(h8_dma_channel_device::marbl_r)
+{
+ logerror("marbl_r %06x\n", mar[1]);
+ return mar[1];
+}
+
+WRITE16_MEMBER(h8_dma_channel_device::marbl_w)
+{
+ mar[1] = (mar[1] & ~mem_mask) | (data & mem_mask);
+ logerror("marbl_w %06x\n", mar[1]);
+}
+
+READ16_MEMBER(h8_dma_channel_device::ioarb_r)
+{
+ logerror("ioarb_r %04x\n", ioar[1]);
+ return ioar[1];
+}
+
+WRITE16_MEMBER(h8_dma_channel_device::ioarb_w)
+{
+ COMBINE_DATA(&ioar[1]);
+ logerror("ioarb_w %04x\n", ioar[1]);
+}
+
+READ16_MEMBER(h8_dma_channel_device::etcrb_r)
+{
+ logerror("etcrb_r %04x\n", etcr[1]);
+ return etcr[1];
+}
+
+WRITE16_MEMBER(h8_dma_channel_device::etcrb_w)
+{
+ COMBINE_DATA(&etcr[1]);
+ logerror("etcrb_w %04x\n", etcr[1]);
+}
+
+READ16_MEMBER(h8_dma_channel_device::dmacr_r)
+{
+ logerror("dmacr_r %04x\n", dmacr);
+ return dmacr;
+}
+
+WRITE16_MEMBER(h8_dma_channel_device::dmacr_w)
+{
+ COMBINE_DATA(&dmacr);
+ logerror("dmacr_w %04x\n", dmacr);
+ start_test(-1);
+}
+
+void h8_dma_channel_device::set_bcr(bool _fae, bool _sae, UINT8 _dta, UINT8 _dte, UINT8 _dtie)
+{
+ fae = _fae;
+ sae = _sae;
+ dta = _dta & 3;
+ dte = _dte & 3;
+ dtie = _dtie & 3;
+ logerror("fae=%d sae=%d dta=%d dte=%d dtie=%d\n", fae, sae, dta & 3, dte & 3, dtie & 3);
+ start_test(-1);
+}
+
+bool h8_dma_channel_device::start_test(int vector)
+{
+ if(fae) {
+ if(dte != 3)
+ return false;
+
+ if(dmacr & 0x0800)
+ throw emu_fatalerror("%s: DMA startup test in full address/block mode unimplemented.\n", tag());
+ else {
+ if((dmacr & 0x0006) == 0x0006) {
+ start(0);
+ return true;
+ } else
+ throw emu_fatalerror("%s: DMA startup test in full address/normal mode/dreq unimplemented.\n", tag());
+ }
+ } else {
+ if(dte == 0)
+ return false;
+
+ throw emu_fatalerror("%s: DMA startup test in short address mode unimplemented.\n", tag());
+ }
+}
+
+void h8_dma_channel_device::start(int submodule)
+{
+ if(fae) {
+ if(dmacr & 0x0800)
+ throw emu_fatalerror("%s: DMA start in full address/block mode unimplemented.\n", tag());
+ else {
+ state[submodule].source = mar[0];
+ state[submodule].dest = mar[1];
+ state[submodule].count = etcr[0] ? etcr[0] : 0x10000;
+ state[submodule].mode_16 = dmacr & 0x8000;
+ INT32 step = state[submodule].mode_16 ? 2 : 1;
+ state[submodule].incs = dmacr & 0x2000 ? dmacr & 0x4000 ? -step : step : 0;
+ state[submodule].incd = dmacr & 0x0020 ? dmacr & 0x0040 ? -step : step : 0;
+ cpu->set_current_dma(state + submodule);
+ }
+ } else {
+ throw emu_fatalerror("%s: DMA start in short address mode unimplemented.\n", tag());
+ }
+}
+
+
+void h8_dma_channel_device::count_done(int submodule)
+{
+ logerror("count done on %d\n", submodule);
+ if(fae) {
+ if(dmacr & 0x0800)
+ throw emu_fatalerror("%s: DMA count done full address/block mode unimplemented.\n", tag());
+ else {
+ dte &= ~1;
+ dmac->clear_dte(state[0].id);
+ if(dtie & 1)
+ throw emu_fatalerror("%s: DMA end-of-transfer interrupt in full address/normal mode unimplemented.\n", tag());
+ }
+ } else {
+ throw emu_fatalerror("%s: DMA count done in short address mode unimplemented.\n", tag());
+ }
+}
diff --git a/src/devices/cpu/h8/h8_dma.h b/src/devices/cpu/h8/h8_dma.h
new file mode 100644
index 00000000000..e241fb5653e
--- /dev/null
+++ b/src/devices/cpu/h8/h8_dma.h
@@ -0,0 +1,127 @@
+// license:BSD-3-Clause
+// copyright-holders:Olivier Galibert
+/***************************************************************************
+
+ h8_dma.h
+
+ H8 DMA Controller
+
+***************************************************************************/
+
+#ifndef __H8_DMA_H__
+#define __H8_DMA_H__
+
+#include "h8.h"
+#include "h8_intc.h"
+
+struct h8_dma_state {
+ UINT32 source, dest;
+ INT32 incs, incd;
+ UINT32 count;
+ int id;
+ bool mode_16;
+};
+
+#define MCFG_H8_DMA_ADD( _tag ) \
+ MCFG_DEVICE_ADD( _tag, H8_DMA, 0 )
+
+#define MCFG_H8_DMA_CHANNEL_ADD( _tag, intc, irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf ) \
+ MCFG_DEVICE_ADD( _tag, H8_DMA_CHANNEL, 0 ) \
+ downcast<h8_dma_channel_device *>(device)->set_info(intc, irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf);
+
+class h8_dma_channel_device;
+
+class h8_dma_device : public device_t {
+public:
+ h8_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+ DECLARE_READ8_MEMBER(dmawer_r);
+ DECLARE_WRITE8_MEMBER(dmawer_w);
+ DECLARE_READ8_MEMBER(dmatcr_r);
+ DECLARE_WRITE8_MEMBER(dmatcr_w);
+ DECLARE_READ16_MEMBER(dmabcr_r);
+ DECLARE_WRITE16_MEMBER(dmabcr_w);
+
+ bool trigger_dma(int vector);
+ void count_done(int id);
+ void clear_dte(int id);
+
+protected:
+ required_device<h8_dma_channel_device> dmach0, dmach1;
+
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ UINT8 dmawer, dmatcr;
+ UINT16 dmabcr;
+};
+
+class h8_dma_channel_device : public device_t {
+public:
+ enum {
+ NONE = -1,
+ DREQ_LEVEL = -2,
+ DREQ_EDGE = -3
+ };
+
+ enum {
+ MODE8_MEM_MEM,
+ MODE8_DACK_MEM,
+ MODE8_MEM_DACK,
+ MODE16_MEM_MEM,
+ MODE16_DACK_MEM,
+ MODE16_MEM_DACK
+ };
+
+ h8_dma_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+ void set_info(const char *intc, int irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf);
+
+ DECLARE_READ16_MEMBER(marah_r);
+ DECLARE_WRITE16_MEMBER(marah_w);
+ DECLARE_READ16_MEMBER(maral_r);
+ DECLARE_WRITE16_MEMBER(maral_w);
+ DECLARE_READ16_MEMBER(ioara_r);
+ DECLARE_WRITE16_MEMBER(ioara_w);
+ DECLARE_READ16_MEMBER(etcra_r);
+ DECLARE_WRITE16_MEMBER(etcra_w);
+ DECLARE_READ16_MEMBER(marbh_r);
+ DECLARE_WRITE16_MEMBER(marbh_w);
+ DECLARE_READ16_MEMBER(marbl_r);
+ DECLARE_WRITE16_MEMBER(marbl_w);
+ DECLARE_READ16_MEMBER(ioarb_r);
+ DECLARE_WRITE16_MEMBER(ioarb_w);
+ DECLARE_READ16_MEMBER(etcrb_r);
+ DECLARE_WRITE16_MEMBER(etcrb_w);
+ DECLARE_READ16_MEMBER(dmacr_r);
+ DECLARE_WRITE16_MEMBER(dmacr_w);
+
+ void set_id(int id);
+ void set_bcr(bool fae, bool sae, UINT8 dta, UINT8 dte, UINT8 dtie);
+ bool start_test(int vector);
+ void count_done(int submodule);
+protected:
+ required_device<h8_dma_device> dmac;
+ required_device<h8_device> cpu;
+ h8_intc_device *intc;
+ const char *intc_tag;
+ h8_dma_state state[2];
+ int irq_base;
+
+ int activation_vectors[16];
+
+ UINT32 mar[2];
+ UINT16 ioar[2], etcr[2], dmacr;
+ UINT8 dta, dte, dtie;
+ bool fae, sae;
+
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ void start(int submodule);
+};
+
+extern const device_type H8_DMA;
+extern const device_type H8_DMA_CHANNEL;
+
+#endif
diff --git a/src/devices/cpu/h8/h8_dtc.cpp b/src/devices/cpu/h8/h8_dtc.cpp
new file mode 100644
index 00000000000..0efb6200a54
--- /dev/null
+++ b/src/devices/cpu/h8/h8_dtc.cpp
@@ -0,0 +1,269 @@
+#include "emu.h"
+#include "h8_dtc.h"
+
+// Verbosity level
+// 0 = no messages
+// 1 = in-memory registers once read
+// 2 = everything
+const int V = 0;
+
+const device_type H8_DTC = &device_creator<h8_dtc_device>;
+
+const int h8_dtc_device::vector_to_enable[92] = {
+ -1, -1, -1, -1, -1, -1, -1, -1, // NMI at 7
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, 1, 2, 3, 4, 5, 6, 7, // IRQ 0-7
+ -1, -1, -1, -1, 9, -1, -1, -1, // SWDTEND, WOVI, CMI, (reserved), ADI
+ 10, 11, 12, 13, -1, -1, -1, -1, // TGI0A, TGI0B, TGI0C, TGI0D, TGI0V
+ 14, 15, -1, -1, 16, 17, -1, -1, // TGI1A, TGI1B, TGI1V, TGI1U, TGI2A, TGI2B, TGI2V, TGI2U
+ -1, -1, -1, -1, -1, -1, -1, -1, // TGI3A, TGI3B, TGI3C, TGI3D, TGI3V
+ -1, -1, -1, -1, -1, -1, -1, -1, // TGI4A, TGI4B, TGI4V, TGI4U, TGI5A, TGI5B, TGI5V, TGI5U
+ 28, 29, -1, -1, 30, 31, -1, -1, // CMIA0, CMIB0, OVI0, CMIA1, CMIB1, OVI1
+ -1, -1, -1, -1, -1, -1, -1, -1, // DEND0A, DEND0B, DEND1B, DEND1B
+ -1, 36, 37, -1, -1, 38, 39, -1, // ERI0, RXI0, TXI0, TEI0, ERI1, RXI1, TXI1, TEI1
+ -1, 40, 41, -1 // ERI2, RXI2, TXI2, TEI2
+};
+
+h8_dtc_device::h8_dtc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
+ device_t(mconfig, H8_DTC, "H8 DTC controller", tag, owner, clock, "h8_dtc", __FILE__),
+ cpu(*this, DEVICE_SELF_OWNER)
+{
+}
+
+void h8_dtc_device::set_info(const char *_intc_tag, int _irq)
+{
+ intc_tag = _intc_tag;
+ irq = _irq;
+}
+
+void h8_dtc_device::device_start()
+{
+ intc = siblingdevice<h8_intc_device>(intc_tag);
+}
+
+void h8_dtc_device::device_reset()
+{
+ memset(dtcer, 0x00, sizeof(dtcer));
+ memset(states, 0, sizeof(states));
+ for(UINT8 i=0; i<sizeof(states)/sizeof(states[0]); i++)
+ states[i].id = i;
+ dtvecr = 0x00;
+ cur_active_vector = -1;
+}
+
+READ8_MEMBER(h8_dtc_device::dtcer_r)
+{
+ if(V>=2) logerror("dtcer_r %x, %02x\n", offset, dtcer[offset]);
+ return dtcer[offset];
+}
+
+WRITE8_MEMBER(h8_dtc_device::dtcer_w)
+{
+ dtcer[offset] = data;
+ if(V>=2) logerror("dtcer_w %x, %02x\n", offset, data);
+}
+
+READ8_MEMBER(h8_dtc_device::dtvecr_r)
+{
+ if(V>=2) logerror("dtvecr_r %02x\n", dtvecr);
+ return dtvecr;
+}
+
+WRITE8_MEMBER(h8_dtc_device::dtvecr_w)
+{
+ dtvecr = data;
+ if(V>=2) logerror("dtvecr_w %02x\n", data);
+}
+
+void h8_dtc_device::edge(int vector)
+{
+ for(std::list<int>::const_iterator i = waiting_vector.begin(); i != waiting_vector.end(); i++)
+ if(*i == vector)
+ return;
+ for(std::list<int>::const_iterator i = waiting_writeback.begin(); i != waiting_writeback.end(); i++)
+ if(*i == vector)
+ return;
+ if(waiting_vector.empty() && waiting_writeback.empty())
+ cpu->request_state(h8_device::STATE_DTC_VECTOR);
+ waiting_vector.push_back(vector);
+}
+
+int h8_dtc_device::get_waiting_vector()
+{
+ assert(!waiting_vector.empty());
+ return waiting_vector.front();
+}
+
+int h8_dtc_device::get_waiting_writeback()
+{
+ assert(!waiting_writeback.empty());
+ return waiting_writeback.front();
+}
+
+void h8_dtc_device::queue(int vector)
+{
+ int ps = -1;
+ int cs = cur_active_vector;
+ while(cs != -1 && cs < vector) {
+ ps = cs;
+ cs = states[cs].next;
+ }
+
+ states[vector].next = cs;
+ if(ps == -1) {
+ cur_active_vector = vector;
+ cpu->set_current_dtc(&states[vector]);
+ } else
+ states[ps].next = vector;
+}
+
+void h8_dtc_device::vector_done(int vector)
+{
+ std::list<int>::iterator wi;
+ for(wi = waiting_vector.begin(); wi != waiting_vector.end() && *wi != vector && *wi != vector + DTC_CHAINED; wi++);
+ assert(wi != waiting_vector.end());
+ waiting_vector.erase(wi);
+
+ h8_dtc_state *state = states + vector;
+ UINT32 sra = state->sra;
+ UINT32 dar = state->dar;
+ UINT32 cr = state->cr;
+
+ UINT32 mode = sra & 0x0c000000;
+ if(V>=1) logerror("regs at %08x sra=%08x dar=%08x cr=%08x %s mode\n", state->base, sra, dar, cr,
+ mode == 0x00000000 || mode == 0x0c000000 ? "normal" : mode == 0x04000000 ? "repeat" : "block");
+ state->incs = sra & 0x80000000 ?
+ sra & 0x40000000 ? sra & 0x01000000 ? -2 : -1 :
+ sra & 0x01000000 ? 2 : 1 :
+ 0;
+ state->incd = sra & 0x20000000 ?
+ sra & 0x10000000 ? sra & 0x01000000 ? -2 : -1 :
+ sra & 0x01000000 ? 2 : 1 :
+ 0;
+
+ switch(mode) {
+ case 0x00000000: case 0x0c0000000:
+ state->count = 1;
+ break;
+ case 0x04000000:
+ state->count = 1;
+ break;
+ case 0x08000000:
+ state->count = (cr >> 16) & 255;
+ if(!state->count)
+ state->count = 256;
+ break;
+ }
+
+ queue(vector);
+
+ if(!waiting_vector.empty())
+ cpu->request_state(h8_device::STATE_DTC_VECTOR);
+ else if(!waiting_writeback.empty())
+ cpu->request_state(h8_device::STATE_DTC_WRITEBACK);
+
+}
+
+void h8_dtc_device::writeback_done(int vector)
+{
+ std::list<int>::iterator wi;
+ for(wi = waiting_writeback.begin(); wi != waiting_writeback.end() && *wi != vector; wi++);
+ assert(wi != waiting_writeback.end());
+ waiting_writeback.erase(wi);
+
+
+ h8_dtc_state *state = states + vector;
+ bool done = false;
+ switch(state->sra & 0x0c000000) {
+ case 0x00000000: case 0x0c0000000:
+ done = !(state->cr & 0xffff0000);
+ break;
+
+ case 0x04000000:
+ break;
+
+ case 0x08000000:
+ done = !(state->cr & 0x0000ffff);
+ break;
+ }
+
+ if(done && state->dar & 0x80000000) {
+ cpu->request_state(h8_device::STATE_DTC_VECTOR);
+ waiting_vector.push_back(vector + DTC_CHAINED);
+ return;
+ }
+
+ if(done || (state->dar & 0x40000000)) {
+ if(vector) {
+ int slot = vector_to_enable[vector];
+ assert(slot != -1);
+ dtcer[slot >> 3] &= ~(0x01 << (7-(slot & 7)));
+ intc->internal_interrupt(vector);
+ } else {
+ logerror("Software dtc done\n");
+ exit(0);
+ }
+ }
+
+ if(!waiting_vector.empty())
+ cpu->request_state(h8_device::STATE_DTC_VECTOR);
+ else if(!waiting_writeback.empty())
+ cpu->request_state(h8_device::STATE_DTC_WRITEBACK);
+}
+
+bool h8_dtc_device::trigger_dtc(int vector)
+{
+ int slot = vector_to_enable[vector];
+ if(slot == -1)
+ return false;
+ if(dtcer[slot >> 3] & (0x01 << (7-(slot & 7)))) {
+ edge(vector);
+ return true;
+ }
+ return false;
+}
+
+void h8_dtc_device::count_done(int id)
+{
+ assert(cur_active_vector == id);
+ cur_active_vector = states[id].next;
+ if(cur_active_vector != -1)
+ cpu->set_current_dtc(states + cur_active_vector);
+
+ h8_dtc_state *state = states + id;
+ switch(state->sra & 0x0c000000) {
+ case 0x00000000: case 0x0c0000000:
+ state->cr -= 0x00010000;
+ break;
+
+ case 0x04000000:
+ state->cr = (state->cr & 0xff00ffff) | ((state->cr - 0x00010000) & 0x00ff0000);
+ if(!(state->cr & 0x00ff0000)) {
+ int cnt = (state->cr >> 24) & 0xff;
+ if(!cnt)
+ cnt = 256;
+ if(state->sra & 0x02000000)
+ state->sra = (state->sra & 0xff000000) | ((state->sra - cnt*state->incs) & 0xffffff);
+ else
+ state->dar = (state->dar & 0xff000000) | ((state->dar - cnt*state->incd) & 0xffffff);
+ state->cr |= (state->cr >> 8) & 0x00ff0000;
+ }
+ break;
+
+ case 0x08000000: {
+ int cnt = (state->cr >> 16) & 0xff;
+ if(!cnt)
+ cnt = 256;
+ if(state->sra & 0x02000000)
+ state->sra = (state->sra & 0xff000000) | ((state->sra - cnt*state->incs) & 0xffffff);
+ else
+ state->dar = (state->dar & 0xff000000) | ((state->dar - cnt*state->incd) & 0xffffff);
+ state->cr = (state->cr & 0xff000000) | ((state->cr >> 8) & 0x00ff0000) | ((state->cr - 0x00000001) & 0x0000ffff);
+ break;
+ }
+ }
+ if(waiting_vector.empty() && waiting_writeback.empty())
+ cpu->request_state(h8_device::STATE_DTC_WRITEBACK);
+ waiting_writeback.push_back(id);
+}
+
diff --git a/src/devices/cpu/h8/h8_dtc.h b/src/devices/cpu/h8/h8_dtc.h
new file mode 100644
index 00000000000..cdccf42758a
--- /dev/null
+++ b/src/devices/cpu/h8/h8_dtc.h
@@ -0,0 +1,74 @@
+// license:BSD-3-Clause
+// copyright-holders:Olivier Galibert
+/***************************************************************************
+
+ h8_dtc.h
+
+ H8 Data Transfer Controller
+
+***************************************************************************/
+
+#ifndef __H8_DTC_H__
+#define __H8_DTC_H__
+
+#include "h8_intc.h"
+
+#include <list>
+
+#define MCFG_H8_DTC_ADD( _tag, intc, irq ) \
+ MCFG_DEVICE_ADD( _tag, H8_DTC, 0 ) \
+ downcast<h8_dtc_device *>(device)->set_info(intc, irq);
+
+struct h8_dtc_state {
+ UINT32 base, sra, dar, cr;
+ INT32 incs, incd;
+ UINT32 count;
+ int id;
+ int next;
+};
+
+class h8_dtc_device : public device_t {
+public:
+ enum { DTC_CHAINED = 1000 };
+
+ h8_dtc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ void set_info(const char *intc, int irq);
+
+ DECLARE_READ8_MEMBER(dtcer_r);
+ DECLARE_WRITE8_MEMBER(dtcer_w);
+ DECLARE_READ8_MEMBER(dtvecr_r);
+ DECLARE_WRITE8_MEMBER(dtvecr_w);
+
+ bool trigger_dtc(int vector);
+ void count_done(int id);
+
+ inline h8_dtc_state *get_object(int vector) { return states + vector; }
+ inline UINT32 get_vector_address(int vector) { return 0x400 | ((vector ? vector : dtvecr & 0x7f) << 1); }
+ int get_waiting_vector();
+ int get_waiting_writeback();
+ void vector_done(int vector);
+ void writeback_done(int vector);
+
+protected:
+ static const int vector_to_enable[];
+ required_device<h8_device> cpu;
+ h8_intc_device *intc;
+ const char *intc_tag;
+ int irq;
+ h8_dtc_state states[92];
+
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ UINT8 dtcer[6], dtvecr;
+ int cur_active_vector;
+
+ std::list<int> waiting_vector, waiting_writeback;
+
+ void edge(int vector);
+ void queue(int vector);
+};
+
+extern const device_type H8_DTC;
+
+#endif
diff --git a/src/devices/cpu/h8/h8_intc.cpp b/src/devices/cpu/h8/h8_intc.cpp
index 7a77a988aa0..ad41b2cc2cd 100644
--- a/src/devices/cpu/h8/h8_intc.cpp
+++ b/src/devices/cpu/h8/h8_intc.cpp
@@ -46,7 +46,7 @@ void h8_intc_device::device_reset()
int h8_intc_device::interrupt_taken(int vector)
{
if(0)
- logerror("%s: taking internal interrupt %d\n", tag(), vector);
+ logerror("taking internal interrupt %d\n", vector);
pending_irqs[vector >> 5] &= ~(1 << (vector & 31));
if(vector >= irq_vector_base && vector < irq_vector_base + 8) {
int irq = vector - irq_vector_base;
@@ -64,9 +64,11 @@ int h8_intc_device::interrupt_taken(int vector)
void h8_intc_device::internal_interrupt(int vector)
{
if(0)
- logerror("%s: internal interrupt %d\n", tag(), vector);
- pending_irqs[vector >> 5] |= 1 << (vector & 31);
- update_irq_state();
+ logerror("internal interrupt %d\n", vector);
+ if(!cpu->trigger_dma(vector)) {
+ pending_irqs[vector >> 5] |= 1 << (vector & 31);
+ update_irq_state();
+ }
}
void h8_intc_device::set_input(int inputnum, int state)
@@ -110,13 +112,13 @@ READ8_MEMBER(h8_intc_device::ier_r)
WRITE8_MEMBER(h8_intc_device::ier_w)
{
ier = data;
- logerror("%s: ier = %02x\n", tag(), data);
+ logerror("ier = %02x\n", data);
update_irq_state();
}
void h8_intc_device::check_level_irqs(bool force_update)
{
- logerror("%s: irq_input=%02x\n", tag(), irq_input);
+ logerror("irq_input=%02x\n", irq_input);
bool update = force_update;
for(int i=0; i<8; i++) {
unsigned char mask = 1 << i;
@@ -138,7 +140,7 @@ READ8_MEMBER(h8_intc_device::iscr_r)
WRITE8_MEMBER(h8_intc_device::iscr_w)
{
iscr = data;
- logerror("%s: iscr = %02x\n", tag(), iscr);
+ logerror("iscr = %02x\n", iscr);
update_irq_types();
}
@@ -223,7 +225,7 @@ READ8_MEMBER(h8h_intc_device::isr_r)
WRITE8_MEMBER(h8h_intc_device::isr_w)
{
isr &= data; // edge/level
- logerror("%s: isr = %02x / %02x\n", tag(), data, isr);
+ logerror("isr = %02x / %02x\n", data, isr);
check_level_irqs(true);
}
@@ -235,7 +237,7 @@ READ8_MEMBER(h8h_intc_device::icr_r)
WRITE8_MEMBER(h8h_intc_device::icr_w)
{
icr = (icr & (0xff << (8*offset))) | (data << (8*offset));
- logerror("%s: icr %d = %02x\n", tag(), offset, data);
+ logerror("icr %d = %02x\n", offset, data);
}
READ8_MEMBER(h8h_intc_device::icrc_r)
@@ -256,7 +258,7 @@ READ8_MEMBER(h8h_intc_device::iscrh_r)
WRITE8_MEMBER(h8h_intc_device::iscrh_w)
{
iscr = (iscr & 0x00ff) | (data << 8);
- logerror("%s: iscr = %04x\n", tag(), iscr);
+ logerror("iscr = %04x\n", iscr);
update_irq_types();
}
@@ -268,7 +270,7 @@ READ8_MEMBER(h8h_intc_device::iscrl_r)
WRITE8_MEMBER(h8h_intc_device::iscrl_w)
{
iscr = (iscr & 0xff00) | data;
- logerror("%s: iscr = %04x\n", tag(), iscr);
+ logerror("iscr = %04x\n", iscr);
update_irq_types();
}
@@ -338,7 +340,7 @@ READ8_MEMBER(h8s_intc_device::ipr_r)
WRITE8_MEMBER(h8s_intc_device::ipr_w)
{
ipr[offset] = data;
- logerror("%s: ipr %d = %02x\n", tag(), offset, data);
+ logerror("ipr %d = %02x\n", offset, data);
}
READ8_MEMBER(h8s_intc_device::iprk_r)
diff --git a/src/devices/cpu/h8/h8_port.cpp b/src/devices/cpu/h8/h8_port.cpp
index 6896a5b167a..c610f0bde29 100644
--- a/src/devices/cpu/h8/h8_port.cpp
+++ b/src/devices/cpu/h8/h8_port.cpp
@@ -20,21 +20,21 @@ void h8_port_device::set_info(int _address, UINT8 _default_ddr, UINT8 _mask)
WRITE8_MEMBER(h8_port_device::ddr_w)
{
- // logerror("%s: ddr_w %02x\n", tag(), data);
+ // logerror("ddr_w %02x\n", data);
ddr = data;
update_output();
}
WRITE8_MEMBER(h8_port_device::dr_w)
{
- // logerror("%s: dr_w %02x\n", tag(), data);
+ // logerror("dr_w %02x\n", data);
dr = data;
update_output();
}
READ8_MEMBER(h8_port_device::dr_r)
{
- // logerror("%s: dr_r %02x\n", tag(), (dr | mask) & 0xff);
+ // logerror("dr_r %02x\n", (dr | mask) & 0xff);
return dr | mask;
}
@@ -44,31 +44,31 @@ READ8_MEMBER(h8_port_device::port_r)
if((ddr & ~mask) != UINT8(~mask))
res |= io->read_word(address) & ~ddr;
- // logerror("%s: port_r %02x (%02x %02x)\n", tag(), res, ddr & ~mask, UINT8(~mask));
+ // logerror("port_r %02x (%02x %02x)\n", res, ddr & ~mask, UINT8(~mask));
return res;
}
WRITE8_MEMBER(h8_port_device::pcr_w)
{
- logerror("%s: pcr_w %02x\n", tag(), data);
+ logerror("pcr_w %02x\n", data);
pcr = data;
}
READ8_MEMBER(h8_port_device::pcr_r)
{
- logerror("%s: dr_r %02x\n", tag(), (pcr | mask) & 0xff);
+ logerror("dr_r %02x\n", (pcr | mask) & 0xff);
return pcr | mask;
}
WRITE8_MEMBER(h8_port_device::odr_w)
{
- logerror("%s: odr_w %02x\n", tag(), data);
+ logerror("odr_w %02x\n", data);
odr = data;
}
READ8_MEMBER(h8_port_device::odr_r)
{
- logerror("%s: odr_r %02x\n", tag(), (odr | mask) & 0xff);
+ logerror("odr_r %02x\n", (odr | mask) & 0xff);
return odr | ~mask;
}
diff --git a/src/devices/cpu/h8/h8_sci.cpp b/src/devices/cpu/h8/h8_sci.cpp
index f3b26bd8198..e4806fa4138 100644
--- a/src/devices/cpu/h8/h8_sci.cpp
+++ b/src/devices/cpu/h8/h8_sci.cpp
@@ -3,6 +3,14 @@
#include "emu.h"
#include "h8_sci.h"
+// Verbosity level
+// 0 = no messages
+// 1 = transmitted/recieved bytes, reception errors and clock setup
+// 2 = everything but status register reads
+// 3 = everything
+const int V = 1;
+
+
const device_type H8_SCI = &device_creator<h8_sci_device>;
const char *const h8_sci_device::state_names[] = { "idle", "start", "bit", "parity", "stop", "last-tick" };
@@ -18,7 +26,7 @@ h8_sci_device::h8_sci_device(const machine_config &mconfig, const char *tag, dev
external_clock_period = attotime::never;
}
-void h8_sci_device::set_info(const char *_intc_tag,int eri, int rxi, int txi, int tei)
+void h8_sci_device::set_info(const char *_intc_tag, int eri, int rxi, int txi, int tei)
{
intc_tag = _intc_tag;
eri_int = eri;
@@ -35,33 +43,33 @@ void h8_sci_device::set_external_clock_period(const attotime &period)
WRITE8_MEMBER(h8_sci_device::smr_w)
{
smr = data;
- logerror("%s: smr_w %02x %s %c%c%c%s /%d (%06x)\n", tag(), data,
- data & SMR_CA ? "sync" : "async",
- data & SMR_CHR ? '7' : '8',
- data & SMR_PE ? data & SMR_OE ? 'o' : 'e' : 'n',
- data & SMR_STOP ? '2' : '1',
- data & SMR_MP ? " mp" : "",
- 1 << 2*(data & SMR_CKS),
- cpu->pc());
+ if(V>=2) logerror("smr_w %02x %s %c%c%c%s /%d (%06x)\n", data,
+ data & SMR_CA ? "sync" : "async",
+ data & SMR_CHR ? '7' : '8',
+ data & SMR_PE ? data & SMR_OE ? 'o' : 'e' : 'n',
+ data & SMR_STOP ? '2' : '1',
+ data & SMR_MP ? " mp" : "",
+ 1 << 2*(data & SMR_CKS),
+ cpu->pc());
clock_update();
}
READ8_MEMBER(h8_sci_device::smr_r)
{
- logerror("%s: smr_r %02x (%06x)\n", tag(), smr, cpu->pc());
+ if(V>=2) logerror("smr_r %02x (%06x)\n", smr, cpu->pc());
return smr;
}
WRITE8_MEMBER(h8_sci_device::brr_w)
{
brr = data;
- logerror("%s: brr_w %02x (%06x)\n", tag(), data, cpu->pc());
+ if(V>=2) logerror("brr_w %02x (%06x)\n", data, cpu->pc());
clock_update();
}
READ8_MEMBER(h8_sci_device::brr_r)
{
- logerror("%s: brr_r %02x (%06x)\n", tag(), brr, cpu->pc());
+ if(V>=2) logerror("brr_r %02x (%06x)\n", brr, cpu->pc());
return brr;
}
@@ -77,15 +85,15 @@ bool h8_sci_device::has_recv_error() const
WRITE8_MEMBER(h8_sci_device::scr_w)
{
- logerror("%s: scr_w %02x%s%s%s%s%s%s clk=%d (%06x)\n", tag(), data,
- data & SCR_TIE ? " txi" : "",
- data & SCR_RIE ? " rxi" : "",
- data & SCR_TE ? " tx" : "",
- data & SCR_RE ? " rx" : "",
- data & SCR_MPIE ? " mpi" : "",
- data & SCR_TEIE ? " tei" : "",
- data & SCR_CKE,
- cpu->pc());
+ if(V>=2) logerror("scr_w %02x%s%s%s%s%s%s clk=%d (%06x)\n", data,
+ data & SCR_TIE ? " txi" : "",
+ data & SCR_RIE ? " rxi" : "",
+ data & SCR_TE ? " tx" : "",
+ data & SCR_RE ? " rx" : "",
+ data & SCR_MPIE ? " mpi" : "",
+ data & SCR_TEIE ? " tei" : "",
+ data & SCR_CKE,
+ cpu->pc());
UINT8 delta = scr ^ data;
scr = data;
@@ -110,19 +118,24 @@ WRITE8_MEMBER(h8_sci_device::scr_w)
READ8_MEMBER(h8_sci_device::scr_r)
{
- logerror("%s: scr_r %02x (%06x)\n", tag(), scr, cpu->pc());
+ if(V>=2) logerror("scr_r %02x (%06x)\n", scr, cpu->pc());
return scr;
}
WRITE8_MEMBER(h8_sci_device::tdr_w)
{
- logerror("%s: tdr_w %02x (%06x)\n", tag(), data, cpu->pc());
+ if(V>=2) logerror("tdr_w %02x (%06x)\n", data, cpu->pc());
tdr = data;
+ if(cpu->access_is_dma()) {
+ ssr &= ~SSR_TDRE;
+ if(tx_state == ST_IDLE)
+ tx_start();
+ }
}
READ8_MEMBER(h8_sci_device::tdr_r)
{
- logerror("%s: tdr_r %02x (%06x)\n", tag(), tdr, cpu->pc());
+ if(V>=2) logerror("tdr_r %02x (%06x)\n", tdr, cpu->pc());
return tdr;
}
@@ -135,7 +148,7 @@ WRITE8_MEMBER(h8_sci_device::ssr_w)
if((ssr & SSR_TDRE) && !(data & SSR_TDRE))
ssr &= ~SSR_TEND;
ssr = ((ssr & ~SSR_MPBT) | (data & SSR_MPBT)) & (data | (SSR_TEND|SSR_MPB|SSR_MPBT));
- logerror("%s: ssr_w %02x -> %02x (%06x)\n", tag(), data, ssr, cpu->pc());
+ if(V>=2) logerror("ssr_w %02x -> %02x (%06x)\n", data, ssr, cpu->pc());
if(tx_state == ST_IDLE && !(ssr & SSR_TDRE))
tx_start();
@@ -146,24 +159,26 @@ WRITE8_MEMBER(h8_sci_device::ssr_w)
READ8_MEMBER(h8_sci_device::ssr_r)
{
- logerror("%s: ssr_r %02x (%06x)\n", tag(), ssr, cpu->pc());
+ if(V>=3) logerror("ssr_r %02x (%06x)\n", ssr, cpu->pc());
return ssr;
}
READ8_MEMBER(h8_sci_device::rdr_r)
{
- logerror("%s: rdr_r %02x (%06x)\n", tag(), rdr, cpu->pc());
+ if(V>=2) logerror("rdr_r %02x (%06x)\n", rdr, cpu->pc());
+ if(cpu->access_is_dma())
+ ssr &= ~SSR_RDRF;
return rdr;
}
WRITE8_MEMBER(h8_sci_device::scmr_w)
{
- logerror("%s: scmr_w %02x (%06x)\n", tag(), data, cpu->pc());
+ if(V>=2) logerror("scmr_w %02x (%06x)\n", data, cpu->pc());
}
READ8_MEMBER(h8_sci_device::scmr_r)
{
- logerror("%s: scmr_r (%06x)\n", tag(), cpu->pc());
+ if(V>=2) logerror("scmr_r (%06x)\n", cpu->pc());
return 0x00;
}
@@ -189,31 +204,43 @@ void h8_sci_device::clock_update()
clock_mode = CLKM_INTERNAL_ASYNC;
}
- switch(clock_mode) {
- case CLKM_INTERNAL_ASYNC:
- logerror("%s: clock internal at %d Hz, async, bitrate %d bps\n", tag(), int(cpu->clock() / divider), int(cpu->clock() / (divider*16)));
- break;
- case CLKM_INTERNAL_ASYNC_OUT:
- logerror("%s: clock internal at %d Hz, async, bitrate %d bps, output\n", tag(), int(cpu->clock() / divider), int(cpu->clock() / (divider*16)));
- break;
- case CLKM_EXTERNAL_ASYNC:
- if(!external_clock_period.is_never()) {
- clock_mode = CLKM_EXTERNAL_RATE_ASYNC;
- logerror("%s: clock external at %d Hz, async, bitrate %d bps\n", tag(), int(cpu->clock()*internal_to_external_ratio), int(cpu->clock()*internal_to_external_ratio/16));
- } else
- logerror("%s: clock external, async\n", tag());
- break;
- case CLKM_INTERNAL_SYNC_OUT:
- logerror("%s: clock internal at %d Hz, sync, output\n", tag(), int(cpu->clock() / (divider*2)));
- break;
+ if(clock_mode == CLKM_EXTERNAL_ASYNC && !external_clock_period.is_never())
+ clock_mode = CLKM_EXTERNAL_RATE_ASYNC;
+ if(clock_mode == CLKM_EXTERNAL_SYNC && !external_clock_period.is_never())
+ clock_mode = CLKM_EXTERNAL_RATE_SYNC;
- case CLKM_EXTERNAL_SYNC:
- if(!external_clock_period.is_never()) {
- clock_mode = CLKM_EXTERNAL_RATE_ASYNC;
- logerror("%s: clock external at %d Hz, sync\n", tag(), int(cpu->clock()*internal_to_external_ratio));
- } else
- logerror("%s: clock external, sync\n", tag());
- break;
+ if(V>=1) {
+ char buf[4096];
+ switch(clock_mode) {
+ case CLKM_INTERNAL_ASYNC:
+ sprintf(buf, "clock internal at %d Hz, async, bitrate %d bps\n", int(cpu->clock() / divider), int(cpu->clock() / (divider*16)));
+ break;
+ case CLKM_INTERNAL_ASYNC_OUT:
+ sprintf(buf, "clock internal at %d Hz, async, bitrate %d bps, output\n", int(cpu->clock() / divider), int(cpu->clock() / (divider*16)));
+ break;
+
+ case CLKM_EXTERNAL_ASYNC:
+ sprintf(buf, "clock external, async\n");
+ break;
+ case CLKM_EXTERNAL_RATE_ASYNC:
+ sprintf(buf, "clock external at %d Hz, async, bitrate %d bps\n", int(cpu->clock()*internal_to_external_ratio), int(cpu->clock()*internal_to_external_ratio/16));
+ break;
+
+ case CLKM_INTERNAL_SYNC_OUT:
+ sprintf(buf, "clock internal at %d Hz, sync, output\n", int(cpu->clock() / (divider*2)));
+ break;
+
+ case CLKM_EXTERNAL_SYNC:
+ sprintf(buf, "clock external, sync\n");
+ break;
+ case CLKM_EXTERNAL_RATE_SYNC:
+ sprintf(buf, "clock external at %d Hz, sync\n", int(cpu->clock()*internal_to_external_ratio));
+ break;
+ }
+ if(buf != last_clock_message) {
+ last_clock_message = buf;
+ logerror("%s", buf);
+ }
}
}
@@ -290,7 +317,7 @@ void h8_sci_device::device_timer(emu_timer &timer, device_timer_id id, int param
WRITE_LINE_MEMBER(h8_sci_device::rx_w)
{
rx_value = state;
- logerror("%s: rx=%d\n", tag(), state);
+ if(V>=2) logerror("rx=%d\n", state);
if(!rx_value && !(clock_state & CLK_RX) && rx_state != ST_IDLE)
clock_start(CLK_RX);
}
@@ -464,30 +491,30 @@ void h8_sci_device::clock_start(int mode)
case CLKM_INTERNAL_ASYNC:
case CLKM_INTERNAL_ASYNC_OUT:
case CLKM_INTERNAL_SYNC_OUT:
- logerror("%s: Starting internal clock\n", tag());
+ if(V>=2) logerror("Starting internal clock\n");
clock_base = cpu->total_cycles();
cpu->internal_update();
break;
case CLKM_EXTERNAL_RATE_ASYNC:
- logerror("%s: Simulating external clock async\n", tag());
+ if(V>=2) logerror("Simulating external clock async\n");
clock_base = UINT64(cpu->total_cycles()*internal_to_external_ratio);
cpu->internal_update();
break;
case CLKM_EXTERNAL_RATE_SYNC:
- logerror("%s: Simulating external clock sync\n", tag());
+ if(V>=2) logerror("Simulating external clock sync\n");
clock_base = UINT64(cpu->total_cycles()*2*internal_to_external_ratio);
cpu->internal_update();
break;
case CLKM_EXTERNAL_ASYNC:
- logerror("%s: Waiting for external clock async\n", tag());
+ if(V>=2) logerror("Waiting for external clock async\n");
ext_clock_counter = 15;
break;
case CLKM_EXTERNAL_SYNC:
- logerror("%s: Waiting for external clock sync\n", tag());
+ if(V>=2) logerror("Waiting for external clock sync\n");
break;
}
} else
@@ -505,7 +532,7 @@ void h8_sci_device::tx_start()
ssr |= SSR_TDRE;
tsr = tdr;
tx_parity = smr & SMR_OE ? 0 : 1;
- logerror("%s: start transmit %02x\n", tag(), tsr);
+ if(V>=1) logerror("start transmit %02x '%c'\n", tsr, tsr >= 32 && tsr < 127 ? tsr : '.');
if(scr & SCR_TIE)
intc->internal_interrupt(txi_int);
if(smr & SMR_CA) {
@@ -522,7 +549,7 @@ void h8_sci_device::tx_start()
void h8_sci_device::tx_dropped_edge()
{
- logerror("%s: tx_dropped_edge state=%s bit=%d\n", tag(), state_names[tx_state], tx_bit);
+ if(V>=2) logerror("tx_dropped_edge state=%s bit=%d\n", state_names[tx_state], tx_bit);
switch(tx_state) {
case ST_START:
tx_cb(false);
@@ -587,7 +614,7 @@ void h8_sci_device::tx_dropped_edge()
default:
abort();
}
- logerror("%s: -> state=%s bit=%d\n", tag(), state_names[tx_state], tx_bit);
+ if(V>=2) logerror(" -> state=%s bit=%d\n", state_names[tx_state], tx_bit);
}
void h8_sci_device::rx_start()
@@ -595,7 +622,7 @@ void h8_sci_device::rx_start()
ssr |= SSR_TDRE;
rx_parity = smr & SMR_OE ? 0 : 1;
rsr = 0x00;
- logerror("%s: start receive\n", tag());
+ if(V>=2) logerror("start receive\n");
if(smr & SMR_CA) {
rx_state = ST_BIT;
rx_bit = 8;
@@ -613,13 +640,13 @@ void h8_sci_device::rx_done()
if(!(ssr & SSR_FER)) {
if((smr & SMR_PE) && rx_parity) {
ssr |= SSR_PER;
- logerror("%s: Receive parity error\n", tag());
+ if(V>=1) logerror("Receive parity error\n");
} else if(ssr & SSR_RDRF) {
ssr |= SSR_ORER;
- logerror("%s: Receive overrun\n", tag());
+ if(V>=1) logerror("Receive overrun\n");
} else {
ssr |= SSR_RDRF;
- logerror("%s: Received %02x\n", tag(), rsr);
+ if(V>=1) logerror("Received %02x '%c'\n", rsr, rsr >= 32 && rsr < 127 ? rsr : '.');
rdr = rsr;
}
}
@@ -639,7 +666,7 @@ void h8_sci_device::rx_done()
void h8_sci_device::rx_raised_edge()
{
- logerror("%s: rx_raised_edge state=%s bit=%d\n", tag(), state_names[rx_state], rx_bit);
+ if(V>=2) logerror("rx_raised_edge state=%s bit=%d\n", state_names[rx_state], rx_bit);
switch(rx_state) {
case ST_START:
if(rx_value) {
@@ -690,5 +717,5 @@ void h8_sci_device::rx_raised_edge()
default:
abort();
}
- logerror("%s: -> state=%s, bit=%d\n", tag(), state_names[rx_state], rx_bit);
+ if(V>=2) logerror(" -> state=%s, bit=%d\n", state_names[rx_state], rx_bit);
}
diff --git a/src/devices/cpu/h8/h8_sci.h b/src/devices/cpu/h8/h8_sci.h
index 9b88fcc98a0..285360afea1 100644
--- a/src/devices/cpu/h8/h8_sci.h
+++ b/src/devices/cpu/h8/h8_sci.h
@@ -124,6 +124,7 @@ protected:
UINT8 rdr, tdr, smr, scr, ssr, brr, rsr, tsr;
UINT64 clock_base, divider;
+ std::string last_clock_message;
virtual void device_start() override;
virtual void device_reset() override;
diff --git a/src/devices/cpu/h8/h8_timer16.cpp b/src/devices/cpu/h8/h8_timer16.cpp
index fd4e47a13a2..4c7bec631a5 100644
--- a/src/devices/cpu/h8/h8_timer16.cpp
+++ b/src/devices/cpu/h8/h8_timer16.cpp
@@ -3,7 +3,10 @@
#include "emu.h"
#include "h8_timer16.h"
-#define LOG_EVENT_TIME 0
+// Verbosity level
+// 0 = no messages
+// 1 = everything
+const int V = 0;
const device_type H8_TIMER16 = &device_creator<h8_timer16_device>;
const device_type H8_TIMER16_CHANNEL = &device_creator<h8_timer16_channel_device>;
@@ -49,7 +52,7 @@ WRITE8_MEMBER(h8_timer16_channel_device::tcr_w)
{
update_counter();
tcr = data;
- logerror("%s: tcr_w %02x\n", tag(), data);
+ if(V>=1) logerror("tcr_w %02x\n", data);
tcr_update();
recalc_event();
}
@@ -61,7 +64,7 @@ READ8_MEMBER(h8_timer16_channel_device::tmdr_r)
WRITE8_MEMBER(h8_timer16_channel_device::tmdr_w)
{
- logerror("%s: tmdr_w %02x\n", tag(), data);
+ if(V>=1) logerror("tmdr_w %02x\n", data);
}
READ8_MEMBER(h8_timer16_channel_device::tior_r)
@@ -71,7 +74,7 @@ READ8_MEMBER(h8_timer16_channel_device::tior_r)
WRITE8_MEMBER(h8_timer16_channel_device::tior_w)
{
- logerror("%s: tior_w %d, %02x\n", tag(), offset, data);
+ if(V>=1) logerror("tior_w %d, %02x\n", offset, data);
}
void h8_timer16_channel_device::set_ier(UINT8 value)
@@ -96,18 +99,17 @@ READ8_MEMBER(h8_timer16_channel_device::tier_r)
WRITE8_MEMBER(h8_timer16_channel_device::tier_w)
{
update_counter();
- logerror("%s: tier_w %02x\n", tag(), data);
+ if(V>=1) logerror("tier_w %02x\n", data);
tier = data;
tier_update();
- logerror("%s: irq %c%c%c%c%c%c trigger=%d\n",
- tag(),
- ier & IRQ_A ? 'a' : '.',
- ier & IRQ_B ? 'b' : '.',
- ier & IRQ_C ? 'c' : '.',
- ier & IRQ_D ? 'd' : '.',
- ier & IRQ_V ? 'v' : '.',
- ier & IRQ_U ? 'u' : '.',
- ier & IRQ_TRIG ? 1 : 0);
+ if(V>=1) logerror("irq %c%c%c%c%c%c trigger=%d\n",
+ ier & IRQ_A ? 'a' : '.',
+ ier & IRQ_B ? 'b' : '.',
+ ier & IRQ_C ? 'c' : '.',
+ ier & IRQ_D ? 'd' : '.',
+ ier & IRQ_V ? 'v' : '.',
+ ier & IRQ_U ? 'u' : '.',
+ ier & IRQ_TRIG ? 1 : 0);
recalc_event();
}
@@ -118,7 +120,7 @@ READ8_MEMBER(h8_timer16_channel_device::tsr_r)
WRITE8_MEMBER(h8_timer16_channel_device::tsr_w)
{
- logerror("%s: tsr_w %02x\n", tag(), data);
+ if(V>=1) logerror("tsr_w %02x\n", data);
isr_update(data);
}
@@ -132,7 +134,7 @@ WRITE16_MEMBER(h8_timer16_channel_device::tcnt_w)
{
update_counter();
COMBINE_DATA(&tcnt);
- logerror("%s: tcnt_w %04x\n", tag(), tcnt);
+ if(V>=1) logerror("tcnt_w %04x\n", tcnt);
recalc_event();
}
@@ -145,8 +147,7 @@ WRITE16_MEMBER(h8_timer16_channel_device::tgr_w)
{
update_counter();
COMBINE_DATA(tgr + offset);
- if(1)
- logerror("%s: tgr%c_w %04x\n", tag(), 'a'+offset, tgr[offset]);
+ if(V>=1) logerror("tgr%c_w %04x\n", 'a'+offset, tgr[offset]);
recalc_event();
}
@@ -158,8 +159,7 @@ READ16_MEMBER(h8_timer16_channel_device::tbr_r)
WRITE16_MEMBER(h8_timer16_channel_device::tbr_w)
{
COMBINE_DATA(tgr + offset + tgr_count);
- if(1)
- logerror("%s: tbr%c_w %04x\n", tag(), 'a'+offset, tgr[offset]);
+ if(V>=1) logerror("tbr%c_w %04x\n", 'a'+offset, tgr[offset]);
}
void h8_timer16_channel_device::device_start()
@@ -208,8 +208,6 @@ UINT64 h8_timer16_channel_device::internal_update(UINT64 current_time)
{
if(event_time && current_time >= event_time) {
update_counter(current_time);
- if(0)
- logerror("%s: Reached event time (%ld), counter=%04x, dt=%d\n", tag(), long(current_time), tcnt, int(current_time - event_time));
recalc_event(current_time);
}
@@ -236,16 +234,8 @@ void h8_timer16_channel_device::update_counter(UINT64 cur_time)
new_time = (new_time + phase) >> clock_divider;
}
if(counter_incrementing) {
- int ott = tcnt;
int tt = tcnt + new_time - base_time;
tcnt = tt % counter_cycle;
- if(0)
- logerror("%s: Updating %d (%ld %ld) (%ld %ld) -> %d/%d\n",
- tag(),
- ott,
- long(last_clock_update), long(cur_time),
- long(base_time), long(new_time),
- tt, tcnt);
for(int i=0; i<tgr_count; i++)
if((ier & (1 << i)) && (tt == tgr[i] || tcnt == tgr[i]) && interrupt[i] != -1) {
@@ -307,9 +297,6 @@ void h8_timer16_channel_device::recalc_event(UINT64 cur_time)
new_delay = (0x10000 - tcnt) + tgr[i];
}
- if(0)
- logerror("%s: tcnt=%d tgr%c=%d cycle=%d -> delay=%d\n",
- tag(), tcnt, 'a'+i, tgr[i], counter_cycle, new_delay);
if(event_delay > new_delay)
event_delay = new_delay;
}
@@ -319,9 +306,6 @@ void h8_timer16_channel_device::recalc_event(UINT64 cur_time)
else
event_time = 0;
- if(event_time && LOG_EVENT_TIME)
- logerror("%s: next event in %d cycles (%ld)\n", tag(), int(event_time - cpu->total_cycles()), long(event_time));
-
} else {
logerror("decrementing counter\n");
exit(1);
@@ -370,7 +354,7 @@ READ8_MEMBER(h8_timer16_device::tstr_r)
WRITE8_MEMBER(h8_timer16_device::tstr_w)
{
- logerror("%s: tstr_w %02x\n", tag(), data);
+ if(V>=1) logerror("tstr_w %02x\n", data);
tstr = data;
for(int i=0; i<timer_count; i++)
timer_channel[i]->set_enable((tstr >> i) & 1);
@@ -383,7 +367,7 @@ READ8_MEMBER(h8_timer16_device::tsyr_r)
WRITE8_MEMBER(h8_timer16_device::tsyr_w)
{
- logerror("%s: tsyr_w %02x\n", tag(), data);
+ if(V>=1) logerror("tsyr_w %02x\n", data);
}
READ8_MEMBER(h8_timer16_device::tmdr_r)
@@ -393,7 +377,7 @@ READ8_MEMBER(h8_timer16_device::tmdr_r)
WRITE8_MEMBER(h8_timer16_device::tmdr_w)
{
- logerror("%s: tmdr_w %02x\n", tag(), data);
+ if(V>=1) logerror("tmdr_w %02x\n", data);
}
READ8_MEMBER(h8_timer16_device::tfcr_r)
@@ -403,7 +387,7 @@ READ8_MEMBER(h8_timer16_device::tfcr_r)
WRITE8_MEMBER(h8_timer16_device::tfcr_w)
{
- logerror("%s: tfcr_w %02x\n", tag(), data);
+ if(V>=1) logerror("tfcr_w %02x\n", data);
}
READ8_MEMBER(h8_timer16_device::toer_r)
@@ -413,7 +397,7 @@ READ8_MEMBER(h8_timer16_device::toer_r)
WRITE8_MEMBER(h8_timer16_device::toer_w)
{
- logerror("%s: toer_w %02x\n", tag(), data);
+ if(V>=1) logerror("toer_w %02x\n", data);
}
READ8_MEMBER(h8_timer16_device::tocr_r)
@@ -423,7 +407,7 @@ READ8_MEMBER(h8_timer16_device::tocr_r)
WRITE8_MEMBER(h8_timer16_device::tocr_w)
{
- logerror("%s: tocr_w %02x\n", tag(), data);
+ if(V>=1) logerror("tocr_w %02x\n", data);
}
READ8_MEMBER(h8_timer16_device::tisr_r)
@@ -434,14 +418,14 @@ READ8_MEMBER(h8_timer16_device::tisr_r)
for(int i=timer_count; i<4; i++)
r |= 0x11 <<i;
- logerror("%s: tisr%c_r %02x\n", tag(), 'a'+offset, r);
+ if(V>=1) logerror("tisr%c_r %02x\n", 'a'+offset, r);
return r;
}
WRITE8_MEMBER(h8_timer16_device::tisr_w)
{
- logerror("%s: tisr%c_w %02x\n", tag(), 'a'+offset, data);
+ if(V>=1) logerror("tisr%c_w %02x\n", 'a'+offset, data);
for(int i=0; i<timer_count; i++)
timer_channel[i]->tisr_w(offset, data >> i);
}
@@ -458,7 +442,7 @@ WRITE8_MEMBER(h8_timer16_device::tisrc_w)
WRITE8_MEMBER(h8_timer16_device::tolr_w)
{
- logerror("%s: tocr_w %02x\n", tag(), data);
+ if(V>=1) logerror("tocr_w %02x\n", data);
}
@@ -590,16 +574,16 @@ void h8h_timer16_channel_device::tcr_update()
switch(tcr & 0x60) {
case 0x00:
tgr_clearing = TGR_CLEAR_NONE;
- logerror("%s: No automatic tcnt clearing\n", tag());
+ if(V>=1) logerror("No automatic tcnt clearing\n");
break;
case 0x20: case 0x40: {
tgr_clearing = tcr & 0x20 ? 0 : 1;
- logerror("%s: Auto-clear on tgr%c (%04x)\n", tag(), 'a'+tgr_clearing, tgr[tgr_clearing]);
+ if(V>=1) logerror("Auto-clear on tgr%c (%04x)\n", 'a'+tgr_clearing, tgr[tgr_clearing]);
break;
}
case 0x60:
tgr_clearing = TGR_CLEAR_EXT;
- logerror("%s: External sync clear\n", tag());
+ if(V>=1) logerror("External sync clear\n");
break;
}
@@ -607,23 +591,23 @@ void h8h_timer16_channel_device::tcr_update()
if(count_type < 4) {
clock_type = DIV_1;
clock_divider = count_type;
- logerror("%s: clock divider %d (%d)\n", tag(), clock_divider, 1 << clock_divider);
+ if(V>=1) logerror("clock divider %d (%d)\n", clock_divider, 1 << clock_divider);
if(count_type <= DIV_2)
phase = 0;
else {
switch(tcr & 0x18) {
case 0x00:
phase = 0;
- logerror("%s: Phase 0\n", tag());
+ if(V>=1) logerror("Phase 0\n");
break;
case 0x08:
phase = 1 << (clock_divider-1);
- logerror("%s: Phase 180\n", tag());
+ if(V>=1) logerror("Phase 180\n");
break;
case 0x10: case 0x18:
phase = 0;
clock_divider--;
- logerror("%s: Phase 0+180\n", tag());
+ if(V>=1) logerror("Phase 0+180\n");
break;
}
}
@@ -631,7 +615,7 @@ void h8h_timer16_channel_device::tcr_update()
clock_type = INPUT_A + (count_type-4);
clock_divider = 0;
phase = 0;
- logerror("%s: counting input %c\n", tag(), 'a'+count_type-INPUT_A);
+ if(V>=1) logerror("counting input %c\n", 'a'+count_type-INPUT_A);
}
}
@@ -702,18 +686,18 @@ void h8s_timer16_channel_device::tcr_update()
switch(tcr & 0x60) {
case 0x00:
tgr_clearing = TGR_CLEAR_NONE;
- logerror("%s: No automatic tcnt clearing\n", tag());
+ if(V>=1) logerror("No automatic tcnt clearing\n");
break;
case 0x20: case 0x40: {
tgr_clearing = tcr & 0x20 ? 0 : 1;
if(tgr_count > 2 && (tcr & 0x80))
tgr_clearing += 2;
- logerror("%s: Auto-clear on tgr%c\n", tag(), 'a'+tgr_clearing);
+ if(V>=1) logerror("Auto-clear on tgr%c\n", 'a'+tgr_clearing);
break;
}
case 0x60:
tgr_clearing = TGR_CLEAR_EXT;
- logerror("%s: External sync clear\n", tag());
+ if(V>=1) logerror("External sync clear\n");
break;
}
@@ -721,23 +705,23 @@ void h8s_timer16_channel_device::tcr_update()
if(count_type >= DIV_1 && clock_type <= DIV_4) {
clock_type = DIV_1;
clock_divider = count_type - DIV_1;
- logerror("%s: clock divider %d (%d)\n", tag(), clock_divider, 1 << clock_divider);
+ if(V>=1) logerror("clock divider %d (%d)\n", clock_divider, 1 << clock_divider);
if(!clock_divider)
phase = 0;
else {
switch(tcr & 0x18) {
case 0x00:
phase = 0;
- logerror("%s: Phase 0\n", tag());
+ if(V>=1) logerror("Phase 0\n");
break;
case 0x08:
phase = 1 << (clock_divider-1);
- logerror("%s: Phase 180\n", tag());
+ if(V>=1) logerror("Phase 180\n");
break;
case 0x10: case 0x18:
phase = 0;
clock_divider--;
- logerror("%s: Phase 0+180\n", tag());
+ if(V>=1) logerror("Phase 0+180\n");
break;
}
}
@@ -746,12 +730,12 @@ void h8s_timer16_channel_device::tcr_update()
clock_type = CHAIN;
clock_divider = 0;
phase = 0;
- logerror("%s: chained timer\n", tag());
+ if(V>=1) logerror("chained timer\n");
} else if(count_type >= INPUT_A && count_type <= INPUT_D) {
clock_type = count_type;
clock_divider = 0;
phase = 0;
- logerror("%s: counting input %c\n", tag(), 'a'+count_type-INPUT_A);
+ if(V>=1) logerror("counting input %c\n", 'a'+count_type-INPUT_A);
}
}
diff --git a/src/devices/cpu/h8/h8_timer8.cpp b/src/devices/cpu/h8/h8_timer8.cpp
index 29e156edfee..0b9d5da933c 100644
--- a/src/devices/cpu/h8/h8_timer8.cpp
+++ b/src/devices/cpu/h8/h8_timer8.cpp
@@ -3,6 +3,12 @@
#include "emu.h"
#include "h8_timer8.h"
+// Verbosity level
+// 0 = no messages
+// 1 = timer setup
+// 2 = everything
+const int V = 1;
+
const device_type H8_TIMER8_CHANNEL = &device_creator<h8_timer8_channel_device>;
const device_type H8H_TIMER8_CHANNEL = &device_creator<h8h_timer8_channel_device>;
@@ -61,70 +67,73 @@ void h8_timer8_channel_device::set_extra_clock_bit(bool bit)
void h8_timer8_channel_device::update_tcr()
{
+ char buf[4096];
+ char *p = buf;
switch(tcr & TCR_CKS) {
case 0:
clock_type = STOPPED;
clock_divider = 0;
- logerror("%s: clock stopped", tag());
+ if(V>=1) p += sprintf(p, "clock stopped");
break;
case 1: case 2: case 3:
clock_type = DIV;
clock_divider = div_tab[((tcr & TCR_CKS)-1)*2 + extra_clock_bit];
- logerror("%s: clock %dHz", tag(), cpu->clock()/clock_divider);
+ if(V>=1) p += sprintf(p, "clock %dHz", cpu->clock()/clock_divider);
break;
case 4:
clock_type = chain_type;
clock_divider = 0;
- logerror("%s: clock chained %s", tag(), clock_type == CHAIN_A ? "tcora" : "overflow");
+ if(V>=1) p += sprintf(p, "clock chained %s", clock_type == CHAIN_A ? "tcora" : "overflow");
break;
case 5:
clock_type = INPUT_UP;
clock_divider = 0;
- logerror("%s: clock external raising edge", tag());
+ if(V>=1) p += sprintf(p, "clock external raising edge");
break;
case 6:
clock_type = INPUT_DOWN;
clock_divider = 0;
- logerror("%s: clock external falling edge", tag());
+ if(V>=1) p += sprintf(p, "clock external falling edge");
break;
case 7:
clock_type = INPUT_UPDOWN;
clock_divider = 0;
- logerror("%s: clock external both edges", tag());
+ if(V>=1) p += sprintf(p, "clock external both edges");
break;
}
switch(tcr & TCR_CCLR) {
case 0x00:
clear_type = CLEAR_NONE;
- logerror(", no clear");
+ if(V>=1) p += sprintf(p, ", no clear");
break;
case 0x08:
clear_type = CLEAR_A;
- logerror(", clear on tcora");
+ if(V>=1) p += sprintf(p, ", clear on tcora");
break;
case 0x10:
clear_type = CLEAR_B;
- logerror(", clear on tcorb");
+ if(V>=1) p += sprintf(p, ", clear on tcorb");
break;
case 0x18:
clear_type = CLEAR_EXTERNAL;
- logerror(", clear on external");
+ if(V>=1) p += sprintf(p, ", clear on external");
break;
}
- logerror(", irq=%c%c%c\n",
- tcr & TCR_CMIEB ? 'b' : '-',
- tcr & TCR_CMIEA ? 'a' : '-',
- tcr & TCR_OVIE ? 'o' : '-');
+ if(V>=1) p += sprintf(p, ", irq=%c%c%c\n",
+ tcr & TCR_CMIEB ? 'b' : '-',
+ tcr & TCR_CMIEA ? 'a' : '-',
+ tcr & TCR_OVIE ? 'o' : '-');
+ logerror(buf);
}
READ8_MEMBER(h8_timer8_channel_device::tcsr_r)
@@ -140,7 +149,7 @@ WRITE8_MEMBER(h8_timer8_channel_device::tcsr_w)
tcsr = (tcsr & ~mask) | (data & mask);
tcsr &= data | 0x1f;
- logerror("%s: tcsr_w %02x\n", tag(), tcsr);
+ if(V>=2) logerror("tcsr_w %02x\n", tcsr);
recalc_event();
}
@@ -154,7 +163,7 @@ WRITE8_MEMBER(h8_timer8_channel_device::tcor_w)
{
update_counter();
tcor[offset] = data;
- logerror("%s: tcor%c_w %02x\n", tag(), 'a'+offset, data);
+ if(V>=2) logerror("tcor%c_w %02x\n", 'a'+offset, data);
recalc_event();
}
@@ -169,7 +178,7 @@ WRITE8_MEMBER(h8_timer8_channel_device::tcnt_w)
{
update_counter();
tcnt = data;
- logerror("%s: tcnt_w %02x\n", tag(), data);
+ if(V>=2) logerror("tcnt_w %02x\n", data);
recalc_event();
}
@@ -202,8 +211,6 @@ UINT64 h8_timer8_channel_device::internal_update(UINT64 current_time)
{
if(event_time && current_time >= event_time) {
update_counter(current_time);
- if(0)
- logerror("%s: Reached event time (%ld), counter=%02x, dt=%d\n", tag(), long(current_time), tcnt, int(current_time - event_time));
recalc_event(current_time);
}
diff --git a/src/devices/cpu/h8/h8_watchdog.cpp b/src/devices/cpu/h8/h8_watchdog.cpp
new file mode 100644
index 00000000000..91c097b8db1
--- /dev/null
+++ b/src/devices/cpu/h8/h8_watchdog.cpp
@@ -0,0 +1,125 @@
+#include "emu.h"
+#include "h8_watchdog.h"
+
+const device_type H8_WATCHDOG = &device_creator<h8_watchdog_device>;
+
+const int h8_watchdog_device::div_bh[8] = { 1, 6, 7, 9, 11, 13, 15, 17 };
+const int h8_watchdog_device::div_s [8] = { 1, 5, 6, 7, 8, 9, 11, 12 };
+
+h8_watchdog_device::h8_watchdog_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
+ device_t(mconfig, H8_WATCHDOG, "H8 watchdog", tag, owner, clock, "h8_watchdog", __FILE__),
+ cpu(*this, DEVICE_SELF_OWNER)
+{
+}
+
+void h8_watchdog_device::set_info(const char *_intc_tag, int _irq, int _type)
+{
+ intc_tag = _intc_tag;
+ irq = _irq;
+ type = _type;
+}
+
+
+UINT64 h8_watchdog_device::internal_update(UINT64 current_time)
+{
+ tcnt_update(current_time);
+ if(tcsr & TCSR_TME) {
+ int shift = (type == S ? div_s : div_bh)[tcsr & TCSR_CKS];
+ UINT64 spos = tcnt_cycle_base >> shift;
+ return (spos + 0x100 - tcnt) << shift;
+
+ } else
+ return 0;
+}
+
+void h8_watchdog_device::tcnt_update(UINT64 cur_time)
+{
+ if(tcsr & TCSR_TME) {
+ int shift = (type == S ? div_s : div_bh)[tcsr & TCSR_CKS];
+ if(!cur_time)
+ cur_time = cpu->total_cycles();
+ UINT64 spos = tcnt_cycle_base >> shift;
+ UINT64 epos = cur_time >> shift;
+
+ int next_tcnt = tcnt + int(epos - spos);
+ tcnt = next_tcnt;
+ tcnt_cycle_base = cur_time;
+ // logerror("%10lld tcnt %02x -> %03x shift=%d\n", cur_time, tcnt, next_tcnt, shift);
+
+ if(next_tcnt >= 0x100) {
+ logerror("watchdog triggered\n");
+ if(tcsr & TCSR_WT) {
+ if(type == B && !(tcsr & TCSR_NMI))
+ intc->internal_interrupt(3);
+ else
+ cpu->reset();
+ } else {
+ if(!(tcsr & TCSR_OVF)) {
+ tcsr |= TCSR_OVF;
+ intc->internal_interrupt(irq);
+ }
+ }
+ }
+ } else
+ tcnt = 0;
+
+}
+
+READ16_MEMBER(h8_watchdog_device::wd_r)
+{
+ tcnt_update();
+
+ logerror("read\n");
+ return 0;
+}
+
+WRITE16_MEMBER(h8_watchdog_device::wd_w)
+{
+ if(mem_mask != 0xffff)
+ return;
+
+ if((data & 0xff00) == 0xa500) {
+ tcnt_update();
+ if(!(tcsr & TCSR_TME) && (data & TCSR_TME))
+ tcnt_cycle_base = cpu->total_cycles();
+ tcsr = data & 0xff;
+ tcsr |= type == B ? 0x10 : 0x18;
+ cpu->internal_update();
+ }
+
+ if((data & 0xff00) == 0x5a00) {
+ if(tcsr & TCSR_TME) {
+ tcnt = data & 0xff;
+ tcnt_cycle_base = cpu->total_cycles();
+ // logerror("%10lld tcnt = %02x\n", tcnt_cycle_base, tcnt);
+ }
+ cpu->internal_update();
+ }
+}
+
+READ16_MEMBER(h8_watchdog_device::rst_r)
+{
+ logerror("rst_r\n");
+ return 0;
+}
+
+WRITE16_MEMBER(h8_watchdog_device::rst_w)
+{
+ if((data & 0xff00) == 0xa500)
+ logerror("wowf_w %02x\n", data & 0xff);
+ if((data & 0xff00) == 0x5a00)
+ logerror("rtse_w %02x\n", data & 0xff);
+}
+
+void h8_watchdog_device::device_start()
+{
+ intc = siblingdevice<h8_intc_device>(intc_tag);
+}
+
+void h8_watchdog_device::device_reset()
+{
+ tcnt = 0x00;
+ tcnt_cycle_base = cpu->total_cycles();
+ tcsr = type == B ? 0x10 : 0x18;
+ rst = type == S ? 0x1f : 0x3f;
+}
diff --git a/src/devices/cpu/h8/h8_watchdog.h b/src/devices/cpu/h8/h8_watchdog.h
new file mode 100644
index 00000000000..d5c0d5d21a1
--- /dev/null
+++ b/src/devices/cpu/h8/h8_watchdog.h
@@ -0,0 +1,99 @@
+/***************************************************************************
+
+ h8_watchdog.h
+
+ H8 watchdog/timer
+
+****************************************************************************
+
+ Copyright Olivier Galibert
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are
+ met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name 'MAME' nor the names of its contributors may be
+ used to endorse or promote products derived from this software
+ without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR
+ IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL OLIVIER GALIBERT BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+***************************************************************************/
+
+#ifndef __H8_WATCHDOG_H__
+#define __H8_WATCHDOG_H__
+
+#include "h8.h"
+#include "h8_intc.h"
+
+#define MCFG_H8_WATCHDOG_ADD( _tag, intc, irq, type ) \
+ MCFG_DEVICE_ADD( _tag, H8_WATCHDOG, 0 ) \
+ downcast<h8_watchdog_device *>(device)->set_info(intc, irq, type);
+
+class h8_watchdog_device : public device_t {
+public:
+ enum { B, H, S };
+
+ h8_watchdog_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+ void set_info(const char *intc, int irq, int type);
+
+ UINT64 internal_update(UINT64 current_time);
+
+ DECLARE_READ16_MEMBER(wd_r);
+ DECLARE_WRITE16_MEMBER(wd_w);
+ DECLARE_READ16_MEMBER(rst_r);
+ DECLARE_WRITE16_MEMBER(rst_w);
+
+protected:
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+private:
+ enum {
+ TCSR_CKS = 0x07,
+ TCSR_NMI = 0x08,
+ TCSR_TME = 0x20,
+ TCSR_WT = 0x40,
+ TCSR_OVF = 0x80,
+
+ RST_RSTS = 0x20,
+ RST_RSTE = 0x40,
+ RST_RSTEO = 0x40,
+ RST_WRST = 0x80
+ };
+
+ static const int div_bh[8];
+ static const int div_s[8];
+
+ required_device<h8_device> cpu;
+ h8_intc_device *intc;
+ const char *intc_tag;
+ int irq;
+ int type;
+ UINT8 tcnt, tcsr, rst;
+ UINT64 tcnt_cycle_base;
+
+ void tcnt_update(UINT64 current_time = 0);
+};
+
+extern const device_type H8_WATCHDOG;
+
+#endif
diff --git a/src/devices/cpu/h8/h8s2000.h b/src/devices/cpu/h8/h8s2000.h
index 46712311861..665f272fe5b 100644
--- a/src/devices/cpu/h8/h8s2000.h
+++ b/src/devices/cpu/h8/h8s2000.h
@@ -16,6 +16,7 @@
#define __H8S2000_H__
#include "h8h.h"
+#include "h8_dtc.h"
class h8s2000_device : public h8h_device {
public:
@@ -45,6 +46,9 @@ protected:
O(tas_r32ih);
O(state_trace);
+ O(state_dtc);
+ O(state_dtc_vector);
+ O(state_dtc_writeback);
#undef O
};
diff --git a/src/devices/cpu/h8/h8s2245.cpp b/src/devices/cpu/h8/h8s2245.cpp
index c89bdfa2e5e..88650f775bc 100644
--- a/src/devices/cpu/h8/h8s2245.cpp
+++ b/src/devices/cpu/h8/h8s2245.cpp
@@ -13,6 +13,7 @@ h8s2245_device::h8s2245_device(const machine_config &mconfig, device_type type,
h8s2000_device(mconfig, type, name, tag, owner, clock, shortname, source, address_map_delegate(FUNC(h8s2245_device::map), this)),
intc(*this, "intc"),
adc(*this, "adc"),
+ dtc(*this, "dtc"),
port1(*this, "port1"),
port2(*this, "port2"),
port3(*this, "port3"),
@@ -33,14 +34,18 @@ h8s2245_device::h8s2245_device(const machine_config &mconfig, device_type type,
timer16_2(*this, "timer16:2"),
sci0(*this, "sci0"),
sci1(*this, "sci1"),
- sci2(*this, "sci2"), ram_start(0), syscr(0)
+ sci2(*this, "sci2"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
+ ram_start = 0;
}
h8s2245_device::h8s2245_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
h8s2000_device(mconfig, H8S2245, "H8S/2245", tag, owner, clock, "h8s2245", __FILE__, address_map_delegate(FUNC(h8s2245_device::map), this)),
intc(*this, "intc"),
adc(*this, "adc"),
+ dtc(*this, "dtc"),
port1(*this, "port1"),
port2(*this, "port2"),
port3(*this, "port3"),
@@ -61,8 +66,10 @@ h8s2245_device::h8s2245_device(const machine_config &mconfig, const char *tag, d
timer16_2(*this, "timer16:2"),
sci0(*this, "sci0"),
sci1(*this, "sci1"),
- sci2(*this, "sci2")
+ sci2(*this, "sci2"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
ram_start = 0xffec00;
}
@@ -87,6 +94,7 @@ h8s2246_device::h8s2246_device(const machine_config &mconfig, const char *tag, d
static MACHINE_CONFIG_FRAGMENT(h8s2245)
MCFG_H8S_INTC_ADD("intc")
MCFG_H8_ADC_2245_ADD("adc", "intc", 28)
+ MCFG_H8_DTC_ADD("dtc", "intc", 24)
MCFG_H8_PORT_ADD("port1", h8_device::PORT_1, 0x00, 0x00)
MCFG_H8_PORT_ADD("port2", h8_device::PORT_2, 0x00, 0x00)
MCFG_H8_PORT_ADD("port3", h8_device::PORT_3, 0xc0, 0xc0)
@@ -133,116 +141,121 @@ static MACHINE_CONFIG_FRAGMENT(h8s2245)
MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
+ MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
MACHINE_CONFIG_END
DEVICE_ADDRESS_MAP_START(map, 16, h8s2245_device)
AM_RANGE(ram_start, 0xfffbff) AM_RAM
- AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port1", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port2", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffeb2, 0xfffeb3) AM_DEVWRITE8( "port3", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port5", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffeb8, 0xfffeb9) AM_DEVWRITE8( "porta", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portb", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portc", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "portd", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "porte", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portf", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portg", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffec0, 0xfffec1) AM_DEVREADWRITE8("intc", h8s_intc_device, icr_r, icr_w, 0xffff)
- AM_RANGE(0xfffec2, 0xfffec3) AM_DEVREADWRITE8("intc", h8s_intc_device, icrc_r, icrc_w, 0xff00)
- AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrh_r, iscrh_w, 0xff00)
- AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrl_r, iscrl_w, 0x00ff)
- AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, ier_r, ier_w, 0xff00)
- AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, isr_r, isr_w, 0x00ff)
- AM_RANGE(0xffff38, 0xffff39) AM_READWRITE8( syscr_r, syscr_w, 0x00ff)
-
- AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port1", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port2", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port3", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port4", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port5", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff58, 0xffff59) AM_DEVREAD8( "porta", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portb", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portc", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "portd", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "porte", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portf", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portg", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port1", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port2", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff62, 0xffff63) AM_DEVREADWRITE8("port3", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port5", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff68, 0xffff69) AM_DEVREADWRITE8("porta", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portb", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portc", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("portd", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("porte", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portf", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portg", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("porta", h8_port_device, pcr_r, pcr_w, 0xff00)
- AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("portb", h8_port_device, pcr_r, pcr_w, 0x00ff)
- AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portc", h8_port_device, pcr_r, pcr_w, 0xff00)
- AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portd", h8_port_device, pcr_r, pcr_w, 0x00ff)
- AM_RANGE(0xffff74, 0xffff75) AM_DEVREADWRITE8("porte", h8_port_device, pcr_r, pcr_w, 0xff00)
- AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("port3", h8_port_device, odr_r, odr_w, 0xff00)
- AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("porta", h8_port_device, odr_r, odr_w, 0x00ff)
- AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
- AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
- AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
- AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, tdr_r, tdr_w, 0x00ff)
- AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREADWRITE8("sci0", h8_sci_device, ssr_r, ssr_w, 0xff00)
- AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREAD8( "sci0", h8_sci_device, rdr_r, 0x00ff)
- AM_RANGE(0xffff7e, 0xffff7f) AM_DEVREADWRITE8("sci0", h8_sci_device, scmr_r, scmr_w, 0xff00)
- AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, smr_r, smr_w, 0xff00)
- AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, brr_r, brr_w, 0x00ff)
- AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, scr_r, scr_w, 0xff00)
- AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, tdr_r, tdr_w, 0x00ff)
- AM_RANGE(0xffff84, 0xffff85) AM_DEVREADWRITE8("sci1", h8_sci_device, ssr_r, ssr_w, 0xff00)
- AM_RANGE(0xffff84, 0xffff85) AM_DEVREAD8( "sci1", h8_sci_device, rdr_r, 0x00ff)
- AM_RANGE(0xffff86, 0xffff87) AM_DEVREADWRITE8("sci1", h8_sci_device, scmr_r, scmr_w, 0xff00)
- AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, smr_r, smr_w, 0xff00)
- AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, brr_r, brr_w, 0x00ff)
- AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, scr_r, scr_w, 0xff00)
- AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, tdr_r, tdr_w, 0x00ff)
- AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE8("sci2", h8_sci_device, ssr_r, ssr_w, 0xff00)
- AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREAD8( "sci2", h8_sci_device, rdr_r, 0x00ff)
- AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE8("sci2", h8_sci_device, scmr_r, scmr_w, 0xff00)
- AM_RANGE(0xffff90, 0xffff97) AM_DEVREAD8( "adc", h8_adc_device, addr8_r, 0xffff)
- AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcsr_r, adcsr_w, 0xff00)
- AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcr_r, adcr_w, 0x00ff)
- AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
- AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
- AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcsr_r, tcsr_w, 0x00ff)
- AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcor_r, tcor_w, 0xff00)
- AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
- AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
- AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
- AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
- AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
- AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
- AM_RANGE(0xffffd2, 0xffffd3) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
- AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
- AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
- AM_RANGE(0xffffd6, 0xffffd7) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tcnt_r, tcnt_w )
- AM_RANGE(0xffffd8, 0xffffdf) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tgr_r, tgr_w )
- AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
- AM_RANGE(0xffffe2, 0xffffe3) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
- AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
- AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
- AM_RANGE(0xffffe6, 0xffffe7) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tcnt_r, tcnt_w )
- AM_RANGE(0xffffe8, 0xffffeb) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tgr_r, tgr_w )
- AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
- AM_RANGE(0xfffff2, 0xfffff3) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
- AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
- AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
- AM_RANGE(0xfffff6, 0xfffff7) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tcnt_r, tcnt_w )
- AM_RANGE(0xfffff8, 0xfffffb) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tgr_r, tgr_w )
+ AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port1", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port2", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffeb2, 0xfffeb3) AM_DEVWRITE8( "port3", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port5", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffeb8, 0xfffeb9) AM_DEVWRITE8( "porta", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portb", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portc", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "portd", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "porte", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portf", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portg", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffec0, 0xfffec1) AM_DEVREADWRITE8("intc", h8s_intc_device, icr_r, icr_w, 0xffff)
+ AM_RANGE(0xfffec2, 0xfffec3) AM_DEVREADWRITE8("intc", h8s_intc_device, icrc_r, icrc_w, 0xff00)
+ AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrh_r, iscrh_w, 0xff00)
+ AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrl_r, iscrl_w, 0x00ff)
+ AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, ier_r, ier_w, 0xff00)
+ AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, isr_r, isr_w, 0x00ff)
+ AM_RANGE(0xffff30, 0xffff35) AM_DEVREADWRITE8("dtc", h8_dtc_device, dtcer_r, dtcer_w, 0xffff)
+ AM_RANGE(0xffff36, 0xffff37) AM_DEVREADWRITE8("dtc", h8_dtc_device, dtvecr_r, dtvecr_w, 0x00ff)
+ AM_RANGE(0xffff38, 0xffff39) AM_READWRITE8( syscr_r, syscr_w, 0x00ff)
+ AM_RANGE(0xffff3c, 0xffff3d) AM_READWRITE( mstpcr_r, mstpcr_w )
+ AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port1", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port2", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port3", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port4", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port5", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff58, 0xffff59) AM_DEVREAD8( "porta", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portb", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portc", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "portd", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "porte", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portf", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portg", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port1", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port2", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff62, 0xffff63) AM_DEVREADWRITE8("port3", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port5", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff68, 0xffff69) AM_DEVREADWRITE8("porta", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portb", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portc", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("portd", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("porte", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portf", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portg", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("porta", h8_port_device, pcr_r, pcr_w, 0xff00)
+ AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("portb", h8_port_device, pcr_r, pcr_w, 0x00ff)
+ AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portc", h8_port_device, pcr_r, pcr_w, 0xff00)
+ AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portd", h8_port_device, pcr_r, pcr_w, 0x00ff)
+ AM_RANGE(0xffff74, 0xffff75) AM_DEVREADWRITE8("porte", h8_port_device, pcr_r, pcr_w, 0xff00)
+ AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("port3", h8_port_device, odr_r, odr_w, 0xff00)
+ AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("porta", h8_port_device, odr_r, odr_w, 0x00ff)
+ AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
+ AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
+ AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
+ AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, tdr_r, tdr_w, 0x00ff)
+ AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREADWRITE8("sci0", h8_sci_device, ssr_r, ssr_w, 0xff00)
+ AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREAD8( "sci0", h8_sci_device, rdr_r, 0x00ff)
+ AM_RANGE(0xffff7e, 0xffff7f) AM_DEVREADWRITE8("sci0", h8_sci_device, scmr_r, scmr_w, 0xff00)
+ AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, smr_r, smr_w, 0xff00)
+ AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, brr_r, brr_w, 0x00ff)
+ AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, scr_r, scr_w, 0xff00)
+ AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, tdr_r, tdr_w, 0x00ff)
+ AM_RANGE(0xffff84, 0xffff85) AM_DEVREADWRITE8("sci1", h8_sci_device, ssr_r, ssr_w, 0xff00)
+ AM_RANGE(0xffff84, 0xffff85) AM_DEVREAD8( "sci1", h8_sci_device, rdr_r, 0x00ff)
+ AM_RANGE(0xffff86, 0xffff87) AM_DEVREADWRITE8("sci1", h8_sci_device, scmr_r, scmr_w, 0xff00)
+ AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, smr_r, smr_w, 0xff00)
+ AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, brr_r, brr_w, 0x00ff)
+ AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, scr_r, scr_w, 0xff00)
+ AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, tdr_r, tdr_w, 0x00ff)
+ AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE8("sci2", h8_sci_device, ssr_r, ssr_w, 0xff00)
+ AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREAD8( "sci2", h8_sci_device, rdr_r, 0x00ff)
+ AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE8("sci2", h8_sci_device, scmr_r, scmr_w, 0xff00)
+ AM_RANGE(0xffff90, 0xffff97) AM_DEVREAD8( "adc", h8_adc_device, addr8_r, 0xffff)
+ AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcsr_r, adcsr_w, 0xff00)
+ AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcr_r, adcr_w, 0x00ff)
+ AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
+ AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
+ AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcsr_r, tcsr_w, 0x00ff)
+ AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcor_r, tcor_w, 0xff00)
+ AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
+ AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
+ AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
+ AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
+ AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
+ AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
+ AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
+ AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
+ AM_RANGE(0xffffd2, 0xffffd3) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
+ AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
+ AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
+ AM_RANGE(0xffffd6, 0xffffd7) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tcnt_r, tcnt_w )
+ AM_RANGE(0xffffd8, 0xffffdf) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tgr_r, tgr_w )
+ AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
+ AM_RANGE(0xffffe2, 0xffffe3) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
+ AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
+ AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
+ AM_RANGE(0xffffe6, 0xffffe7) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tcnt_r, tcnt_w )
+ AM_RANGE(0xffffe8, 0xffffeb) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tgr_r, tgr_w )
+ AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
+ AM_RANGE(0xfffff2, 0xfffff3) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
+ AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
+ AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
+ AM_RANGE(0xfffff6, 0xfffff7) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tcnt_r, tcnt_w )
+ AM_RANGE(0xfffff8, 0xfffffb) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tgr_r, tgr_w )
ADDRESS_MAP_END
machine_config_constructor h8s2245_device::device_mconfig_additions() const
@@ -319,6 +332,7 @@ void h8s2245_device::internal_update(UINT64 current_time)
add_event(event_time, timer16_0->internal_update(current_time));
add_event(event_time, timer16_1->internal_update(current_time));
add_event(event_time, timer16_2->internal_update(current_time));
+ add_event(event_time, watchdog->internal_update(current_time));
recompute_bcount(event_time);
}
@@ -326,12 +340,14 @@ void h8s2245_device::internal_update(UINT64 current_time)
void h8s2245_device::device_start()
{
h8s2000_device::device_start();
+ dtc_device = dtc;
}
void h8s2245_device::device_reset()
{
h8s2000_device::device_reset();
syscr = 0x01;
+ mstpcr = 0x3fff;
}
READ8_MEMBER(h8s2245_device::syscr_r)
@@ -343,5 +359,30 @@ WRITE8_MEMBER(h8s2245_device::syscr_w)
{
syscr = data;
update_irq_filter();
- logerror("%s: syscr = %02x\n", tag(), data);
+ logerror("syscr = %02x\n", data);
+}
+
+READ16_MEMBER(h8s2245_device::mstpcr_r)
+{
+ return mstpcr;
+}
+
+WRITE16_MEMBER(h8s2245_device::mstpcr_w)
+{
+ UINT16 omstpcr = mstpcr;
+ COMBINE_DATA(&mstpcr);
+ if((omstpcr ^ mstpcr) & 0x72e0) {
+ char buf[4096];
+ char *p = buf;
+ p += sprintf(p, "Online modules:");
+ if(mstpcr & 0x0020) p += sprintf(p, " sci0");
+ if(mstpcr & 0x0040) p += sprintf(p, " sci1");
+ if(mstpcr & 0x0080) p += sprintf(p, " sci2");
+ if(mstpcr & 0x0200) p += sprintf(p, " adc");
+ if(mstpcr & 0x1000) p += sprintf(p, " timer8");
+ if(mstpcr & 0x2000) p += sprintf(p, " timer16");
+ if(mstpcr & 0x4000) p += sprintf(p, " dtc");
+ p += sprintf(p, "\n");
+ logerror(buf);
+ }
}
diff --git a/src/devices/cpu/h8/h8s2245.h b/src/devices/cpu/h8/h8s2245.h
index b4364f68501..a67fa9f9866 100644
--- a/src/devices/cpu/h8/h8s2245.h
+++ b/src/devices/cpu/h8/h8s2245.h
@@ -22,12 +22,14 @@
#define __H8S2245_H__
#include "h8s2000.h"
+#include "h8_intc.h"
#include "h8_adc.h"
+#include "h8_dtc.h"
#include "h8_port.h"
-#include "h8_intc.h"
-#include "h8_sci.h"
#include "h8_timer8.h"
#include "h8_timer16.h"
+#include "h8_sci.h"
+#include "h8_watchdog.h"
class h8s2245_device : public h8s2000_device {
public:
@@ -36,10 +38,13 @@ public:
DECLARE_READ8_MEMBER(syscr_r);
DECLARE_WRITE8_MEMBER(syscr_w);
+ DECLARE_READ16_MEMBER(mstpcr_r);
+ DECLARE_WRITE16_MEMBER(mstpcr_w);
protected:
required_device<h8s_intc_device> intc;
required_device<h8_adc_device> adc;
+ required_device<h8_dtc_device> dtc;
required_device<h8_port_device> port1;
required_device<h8_port_device> port2;
required_device<h8_port_device> port3;
@@ -61,8 +66,10 @@ protected:
required_device<h8_sci_device> sci0;
required_device<h8_sci_device> sci1;
required_device<h8_sci_device> sci2;
+ required_device<h8_watchdog_device> watchdog;
UINT32 ram_start;
+ UINT16 mstpcr;
UINT8 syscr;
virtual bool exr_in_stack() const override;
diff --git a/src/devices/cpu/h8/h8s2320.cpp b/src/devices/cpu/h8/h8s2320.cpp
index 352229079b5..5f0987c2f10 100644
--- a/src/devices/cpu/h8/h8s2320.cpp
+++ b/src/devices/cpu/h8/h8s2320.cpp
@@ -18,6 +18,10 @@ h8s2320_device::h8s2320_device(const machine_config &mconfig, device_type type,
h8s2000_device(mconfig, type, name, tag, owner, clock, shortname, source, address_map_delegate(FUNC(h8s2320_device::map), this)),
intc(*this, "intc"),
adc(*this, "adc"),
+ dma(*this, "dma"),
+ dma0(*this, "dma:0"),
+ dma1(*this, "dma:1"),
+ dtc(*this, "dtc"),
port1(*this, "port1"),
port2(*this, "port2"),
port3(*this, "port3"),
@@ -42,14 +46,21 @@ h8s2320_device::h8s2320_device(const machine_config &mconfig, device_type type,
timer16_5(*this, "timer16:5"),
sci0(*this, "sci0"),
sci1(*this, "sci1"),
- sci2(*this, "sci2"), ram_start(0), syscr(0)
+ sci2(*this, "sci2"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
+ ram_start = 0;
}
h8s2320_device::h8s2320_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
h8s2000_device(mconfig, H8S2320, "H8S/2320", tag, owner, clock, "h8s2320", __FILE__, address_map_delegate(FUNC(h8s2320_device::map), this)),
intc(*this, "intc"),
adc(*this, "adc"),
+ dma(*this, "dma"),
+ dma0(*this, "dma:0"),
+ dma1(*this, "dma:1"),
+ dtc(*this, "dtc"),
port1(*this, "port1"),
port2(*this, "port2"),
port3(*this, "port3"),
@@ -74,8 +85,10 @@ h8s2320_device::h8s2320_device(const machine_config &mconfig, const char *tag, d
timer16_5(*this, "timer16:5"),
sci0(*this, "sci0"),
sci1(*this, "sci1"),
- sci2(*this, "sci2")
+ sci2(*this, "sci2"),
+ watchdog(*this, "watchdog")
{
+ syscr = 0;
ram_start = 0xffec00;
}
@@ -127,9 +140,15 @@ h8s2329_device::h8s2329_device(const machine_config &mconfig, const char *tag, d
ram_start = 0xff7c00;
}
+// TODO: the 2321 doesn't have the dma subdevice
+
static MACHINE_CONFIG_FRAGMENT(h8s2320)
MCFG_H8S_INTC_ADD("intc")
MCFG_H8_ADC_2320_ADD("adc", "intc", 28)
+ MCFG_H8_DMA_ADD("dma")
+ MCFG_H8_DMA_CHANNEL_ADD("dma:0", "intc", 72, h8_dma_channel_device::NONE, 28, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, 82, 81, 86, 85, 32, 40, 44, 48, 56, 60, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE)
+ MCFG_H8_DMA_CHANNEL_ADD("dma:1", "intc", 74, h8_dma_channel_device::NONE, 28, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 82, 81, 86, 85, 32, 40, 44, 48, 56, 60, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE)
+ MCFG_H8_DTC_ADD("dtc", "intc", 24)
MCFG_H8_PORT_ADD("port1", h8_device::PORT_1, 0x00, 0x00)
MCFG_H8_PORT_ADD("port2", h8_device::PORT_2, 0x00, 0x00)
MCFG_H8_PORT_ADD("port3", h8_device::PORT_3, 0xc0, 0xc0)
@@ -205,144 +224,170 @@ static MACHINE_CONFIG_FRAGMENT(h8s2320)
MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
+ MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::H)
MACHINE_CONFIG_END
DEVICE_ADDRESS_MAP_START(map, 16, h8s2320_device)
AM_RANGE(ram_start, 0xfffbff) AM_RAM
- AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
- AM_RANGE(0xfffe82, 0xfffe83) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
- AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
- AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
- AM_RANGE(0xfffe86, 0xfffe87) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tcnt_r, tcnt_w )
- AM_RANGE(0xfffe88, 0xfffe8f) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tgr_r, tgr_w )
- AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
- AM_RANGE(0xfffe92, 0xfffe93) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
- AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
- AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
- AM_RANGE(0xfffe96, 0xfffe97) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tcnt_r, tcnt_w )
- AM_RANGE(0xfffe98, 0xfffe9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
- AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
- AM_RANGE(0xfffea2, 0xfffea3) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
- AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
- AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
- AM_RANGE(0xfffea6, 0xfffea7) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tcnt_r, tcnt_w )
- AM_RANGE(0xfffea8, 0xfffeab) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tgr_r, tgr_w )
- AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port1", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port2", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffeb2, 0xfffeb3) AM_DEVWRITE8( "port3", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port5", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port6", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffeb8, 0xfffeb9) AM_DEVWRITE8( "porta", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portb", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portc", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "portd", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "porte", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portf", h8_port_device, ddr_w, 0xff00)
- AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portg", h8_port_device, ddr_w, 0x00ff)
- AM_RANGE(0xfffec0, 0xfffec1) AM_DEVREADWRITE8("intc", h8s_intc_device, icr_r, icr_w, 0xffff)
- AM_RANGE(0xfffec2, 0xfffec3) AM_DEVREADWRITE8("intc", h8s_intc_device, icrc_r, icrc_w, 0xff00)
- AM_RANGE(0xfffec4, 0xfffecd) AM_DEVREADWRITE8("intc", h8s_intc_device, ipr_r, ipr_w, 0xffff)
- AM_RANGE(0xfffece, 0xfffecf) AM_DEVREADWRITE8("intc", h8s_intc_device, iprk_r, iprk_w, 0xff00)
- AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrh_r, iscrh_w, 0xff00)
- AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrl_r, iscrl_w, 0x00ff)
- AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, ier_r, ier_w, 0xff00)
- AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, isr_r, isr_w, 0x00ff)
- AM_RANGE(0xffff38, 0xffff39) AM_READWRITE8( syscr_r, syscr_w, 0x00ff)
-
- AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port1", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port2", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port3", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port4", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port5", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port6", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff58, 0xffff59) AM_DEVREAD8( "porta", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portb", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portc", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "portd", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "porte", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portf", h8_port_device, port_r, 0xff00)
- AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portg", h8_port_device, port_r, 0x00ff)
- AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port1", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port2", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff62, 0xffff63) AM_DEVREADWRITE8("port3", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port5", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port6", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff68, 0xffff69) AM_DEVREADWRITE8("porta", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portb", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portc", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("portd", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("porte", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portf", h8_port_device, dr_r, dr_w, 0xff00)
- AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portg", h8_port_device, dr_r, dr_w, 0x00ff)
- AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("porta", h8_port_device, pcr_r, pcr_w, 0xff00)
- AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("portb", h8_port_device, pcr_r, pcr_w, 0x00ff)
- AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portc", h8_port_device, pcr_r, pcr_w, 0xff00)
- AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portd", h8_port_device, pcr_r, pcr_w, 0x00ff)
- AM_RANGE(0xffff74, 0xffff75) AM_DEVREADWRITE8("porte", h8_port_device, pcr_r, pcr_w, 0xff00)
- AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("port3", h8_port_device, odr_r, odr_w, 0xff00)
- AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("porta", h8_port_device, odr_r, odr_w, 0x00ff)
- AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
- AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
- AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
- AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, tdr_r, tdr_w, 0x00ff)
- AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREADWRITE8("sci0", h8_sci_device, ssr_r, ssr_w, 0xff00)
- AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREAD8( "sci0", h8_sci_device, rdr_r, 0x00ff)
- AM_RANGE(0xffff7e, 0xffff7f) AM_DEVREADWRITE8("sci0", h8_sci_device, scmr_r, scmr_w, 0xff00)
- AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, smr_r, smr_w, 0xff00)
- AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, brr_r, brr_w, 0x00ff)
- AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, scr_r, scr_w, 0xff00)
- AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, tdr_r, tdr_w, 0x00ff)
- AM_RANGE(0xffff84, 0xffff85) AM_DEVREADWRITE8("sci1", h8_sci_device, ssr_r, ssr_w, 0xff00)
- AM_RANGE(0xffff84, 0xffff85) AM_DEVREAD8( "sci1", h8_sci_device, rdr_r, 0x00ff)
- AM_RANGE(0xffff86, 0xffff87) AM_DEVREADWRITE8("sci1", h8_sci_device, scmr_r, scmr_w, 0xff00)
- AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, smr_r, smr_w, 0xff00)
- AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, brr_r, brr_w, 0x00ff)
- AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, scr_r, scr_w, 0xff00)
- AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, tdr_r, tdr_w, 0x00ff)
- AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE8("sci2", h8_sci_device, ssr_r, ssr_w, 0xff00)
- AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREAD8( "sci2", h8_sci_device, rdr_r, 0x00ff)
- AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE8("sci2", h8_sci_device, scmr_r, scmr_w, 0xff00)
- AM_RANGE(0xffff90, 0xffff97) AM_DEVREAD8( "adc", h8_adc_device, addr8_r, 0xffff)
- AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcsr_r, adcsr_w, 0xff00)
- AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcr_r, adcr_w, 0x00ff)
-
- AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
- AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
- AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcsr_r, tcsr_w, 0x00ff)
- AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcor_r, tcor_w, 0xff00)
- AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
- AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
- AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
-
- AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
- AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
-
- AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
- AM_RANGE(0xffffd2, 0xffffd3) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
- AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
- AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
- AM_RANGE(0xffffd6, 0xffffd7) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tcnt_r, tcnt_w )
- AM_RANGE(0xffffd8, 0xffffdf) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tgr_r, tgr_w )
- AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
- AM_RANGE(0xffffe2, 0xffffe3) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
- AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
- AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
- AM_RANGE(0xffffe6, 0xffffe7) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tcnt_r, tcnt_w )
- AM_RANGE(0xffffe8, 0xffffeb) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tgr_r, tgr_w )
- AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
- AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
- AM_RANGE(0xfffff2, 0xfffff3) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
- AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
- AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
- AM_RANGE(0xfffff6, 0xfffff7) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tcnt_r, tcnt_w )
- AM_RANGE(0xfffff8, 0xfffffb) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tgr_r, tgr_w )
+ AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
+ AM_RANGE(0xfffe82, 0xfffe83) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
+ AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
+ AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
+ AM_RANGE(0xfffe86, 0xfffe87) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tcnt_r, tcnt_w )
+ AM_RANGE(0xfffe88, 0xfffe8f) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tgr_r, tgr_w )
+ AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
+ AM_RANGE(0xfffe92, 0xfffe93) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
+ AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
+ AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
+ AM_RANGE(0xfffe96, 0xfffe97) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tcnt_r, tcnt_w )
+ AM_RANGE(0xfffe98, 0xfffe9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
+ AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
+ AM_RANGE(0xfffea2, 0xfffea3) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
+ AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
+ AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
+ AM_RANGE(0xfffea6, 0xfffea7) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tcnt_r, tcnt_w )
+ AM_RANGE(0xfffea8, 0xfffeab) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tgr_r, tgr_w )
+ AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port1", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port2", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffeb2, 0xfffeb3) AM_DEVWRITE8( "port3", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port5", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port6", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffeb8, 0xfffeb9) AM_DEVWRITE8( "porta", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portb", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portc", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "portd", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "porte", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portf", h8_port_device, ddr_w, 0xff00)
+ AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portg", h8_port_device, ddr_w, 0x00ff)
+ AM_RANGE(0xfffec0, 0xfffec1) AM_DEVREADWRITE8("intc", h8s_intc_device, icr_r, icr_w, 0xffff)
+ AM_RANGE(0xfffec2, 0xfffec3) AM_DEVREADWRITE8("intc", h8s_intc_device, icrc_r, icrc_w, 0xff00)
+ AM_RANGE(0xfffec4, 0xfffecd) AM_DEVREADWRITE8("intc", h8s_intc_device, ipr_r, ipr_w, 0xffff)
+ AM_RANGE(0xfffece, 0xfffecf) AM_DEVREADWRITE8("intc", h8s_intc_device, iprk_r, iprk_w, 0xff00)
+
+ AM_RANGE(0xfffee0, 0xfffee1) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, marah_r, marah_w )
+ AM_RANGE(0xfffee2, 0xfffee3) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, maral_r, maral_w )
+ AM_RANGE(0xfffee4, 0xfffee5) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, ioara_r, ioara_w )
+ AM_RANGE(0xfffee6, 0xfffee7) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, etcra_r, etcra_w )
+ AM_RANGE(0xfffee8, 0xfffee9) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, marbh_r, marbh_w )
+ AM_RANGE(0xfffeea, 0xfffeeb) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, marbl_r, marbl_w )
+ AM_RANGE(0xfffeec, 0xfffeed) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, ioarb_r, ioarb_w )
+ AM_RANGE(0xfffeee, 0xfffeef) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, etcrb_r, etcrb_w )
+ AM_RANGE(0xfffef0, 0xfffef1) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, marah_r, marah_w )
+ AM_RANGE(0xfffef2, 0xfffef3) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, maral_r, maral_w )
+ AM_RANGE(0xfffef4, 0xfffef5) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, ioara_r, ioara_w )
+ AM_RANGE(0xfffef6, 0xfffef7) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, etcra_r, etcra_w )
+ AM_RANGE(0xfffef8, 0xfffef9) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, marbh_r, marbh_w )
+ AM_RANGE(0xfffefa, 0xfffefb) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, marbl_r, marbl_w )
+ AM_RANGE(0xfffefc, 0xfffefd) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, ioarb_r, ioarb_w )
+ AM_RANGE(0xfffefe, 0xfffeff) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, etcrb_r, etcrb_w )
+ AM_RANGE(0xffff00, 0xffff01) AM_DEVREADWRITE8("dma", h8_dma_device, dmawer_r, dmawer_w, 0xff00)
+ AM_RANGE(0xffff00, 0xffff01) AM_DEVREADWRITE8("dma", h8_dma_device, dmatcr_r, dmatcr_w, 0x00ff)
+ AM_RANGE(0xffff02, 0xffff03) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, dmacr_r, dmacr_w )
+ AM_RANGE(0xffff04, 0xffff05) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, dmacr_r, dmacr_w )
+ AM_RANGE(0xffff06, 0xffff07) AM_DEVREADWRITE( "dma", h8_dma_device, dmabcr_r, dmabcr_w )
+ AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrh_r, iscrh_w, 0xff00)
+ AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrl_r, iscrl_w, 0x00ff)
+ AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, ier_r, ier_w, 0xff00)
+ AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, isr_r, isr_w, 0x00ff)
+ AM_RANGE(0xffff30, 0xffff35) AM_DEVREADWRITE8("dtc", h8_dtc_device, dtcer_r, dtcer_w, 0xffff)
+ AM_RANGE(0xffff36, 0xffff37) AM_DEVREADWRITE8("dtc", h8_dtc_device, dtvecr_r, dtvecr_w, 0x00ff)
+ AM_RANGE(0xffff38, 0xffff39) AM_READWRITE8( syscr_r, syscr_w, 0x00ff)
+
+ AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port1", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port2", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port3", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port4", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port5", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port6", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff58, 0xffff59) AM_DEVREAD8( "porta", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portb", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portc", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "portd", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "porte", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portf", h8_port_device, port_r, 0xff00)
+ AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portg", h8_port_device, port_r, 0x00ff)
+ AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port1", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port2", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff62, 0xffff63) AM_DEVREADWRITE8("port3", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port5", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port6", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff68, 0xffff69) AM_DEVREADWRITE8("porta", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portb", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portc", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("portd", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("porte", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portf", h8_port_device, dr_r, dr_w, 0xff00)
+ AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portg", h8_port_device, dr_r, dr_w, 0x00ff)
+ AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("porta", h8_port_device, pcr_r, pcr_w, 0xff00)
+ AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("portb", h8_port_device, pcr_r, pcr_w, 0x00ff)
+ AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portc", h8_port_device, pcr_r, pcr_w, 0xff00)
+ AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portd", h8_port_device, pcr_r, pcr_w, 0x00ff)
+ AM_RANGE(0xffff74, 0xffff75) AM_DEVREADWRITE8("porte", h8_port_device, pcr_r, pcr_w, 0xff00)
+ AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("port3", h8_port_device, odr_r, odr_w, 0xff00)
+ AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("porta", h8_port_device, odr_r, odr_w, 0x00ff)
+ AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
+ AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
+ AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
+ AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, tdr_r, tdr_w, 0x00ff)
+ AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREADWRITE8("sci0", h8_sci_device, ssr_r, ssr_w, 0xff00)
+ AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREAD8( "sci0", h8_sci_device, rdr_r, 0x00ff)
+ AM_RANGE(0xffff7e, 0xffff7f) AM_DEVREADWRITE8("sci0", h8_sci_device, scmr_r, scmr_w, 0xff00)
+ AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, smr_r, smr_w, 0xff00)
+ AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, brr_r, brr_w, 0x00ff)
+ AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, scr_r, scr_w, 0xff00)
+ AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, tdr_r, tdr_w, 0x00ff)
+ AM_RANGE(0xffff84, 0xffff85) AM_DEVREADWRITE8("sci1", h8_sci_device, ssr_r, ssr_w, 0xff00)
+ AM_RANGE(0xffff84, 0xffff85) AM_DEVREAD8( "sci1", h8_sci_device, rdr_r, 0x00ff)
+ AM_RANGE(0xffff86, 0xffff87) AM_DEVREADWRITE8("sci1", h8_sci_device, scmr_r, scmr_w, 0xff00)
+ AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, smr_r, smr_w, 0xff00)
+ AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, brr_r, brr_w, 0x00ff)
+ AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, scr_r, scr_w, 0xff00)
+ AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, tdr_r, tdr_w, 0x00ff)
+ AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE8("sci2", h8_sci_device, ssr_r, ssr_w, 0xff00)
+ AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREAD8( "sci2", h8_sci_device, rdr_r, 0x00ff)
+ AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE8("sci2", h8_sci_device, scmr_r, scmr_w, 0xff00)
+ AM_RANGE(0xffff90, 0xffff97) AM_DEVREAD8( "adc", h8_adc_device, addr8_r, 0xffff)
+ AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcsr_r, adcsr_w, 0xff00)
+ AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcr_r, adcr_w, 0x00ff)
+
+ AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
+ AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
+ AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcsr_r, tcsr_w, 0x00ff)
+ AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcor_r, tcor_w, 0xff00)
+ AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
+ AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
+ AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
+ AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
+ AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
+ AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
+ AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
+
+ AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
+ AM_RANGE(0xffffd2, 0xffffd3) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
+ AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
+ AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
+ AM_RANGE(0xffffd6, 0xffffd7) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tcnt_r, tcnt_w )
+ AM_RANGE(0xffffd8, 0xffffdf) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tgr_r, tgr_w )
+ AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
+ AM_RANGE(0xffffe2, 0xffffe3) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
+ AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
+ AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
+ AM_RANGE(0xffffe6, 0xffffe7) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tcnt_r, tcnt_w )
+ AM_RANGE(0xffffe8, 0xffffeb) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tgr_r, tgr_w )
+ AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
+ AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
+ AM_RANGE(0xfffff2, 0xfffff3) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
+ AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
+ AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
+ AM_RANGE(0xfffff6, 0xfffff7) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tcnt_r, tcnt_w )
+ AM_RANGE(0xfffff8, 0xfffffb) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tgr_r, tgr_w )
ADDRESS_MAP_END
machine_config_constructor h8s2320_device::device_mconfig_additions() const
@@ -427,6 +472,7 @@ void h8s2320_device::internal_update(UINT64 current_time)
add_event(event_time, timer16_3->internal_update(current_time));
add_event(event_time, timer16_4->internal_update(current_time));
add_event(event_time, timer16_5->internal_update(current_time));
+ add_event(event_time, watchdog->internal_update(current_time));
recompute_bcount(event_time);
}
@@ -434,6 +480,8 @@ void h8s2320_device::internal_update(UINT64 current_time)
void h8s2320_device::device_start()
{
h8s2000_device::device_start();
+ dma_device = dma;
+ dtc_device = dtc;
}
void h8s2320_device::device_reset()
@@ -452,5 +500,5 @@ WRITE8_MEMBER(h8s2320_device::syscr_w)
syscr = data;
mac_saturating = syscr & 0x80;
update_irq_filter();
- logerror("%s: syscr = %02x\n", tag(), data);
+ logerror("syscr = %02x\n", data);
}
diff --git a/src/devices/cpu/h8/h8s2320.h b/src/devices/cpu/h8/h8s2320.h
index 2a5a6f8f225..68ef4f7ba66 100644
--- a/src/devices/cpu/h8/h8s2320.h
+++ b/src/devices/cpu/h8/h8s2320.h
@@ -27,12 +27,15 @@
#define __H8S2320_H__
#include "h8s2000.h"
+#include "h8_intc.h"
#include "h8_adc.h"
+#include "h8_dma.h"
+#include "h8_dtc.h"
#include "h8_port.h"
-#include "h8_intc.h"
-#include "h8_sci.h"
#include "h8_timer8.h"
#include "h8_timer16.h"
+#include "h8_sci.h"
+#include "h8_watchdog.h"
class h8s2320_device : public h8s2000_device {
public:
@@ -45,6 +48,10 @@ public:
protected:
required_device<h8s_intc_device> intc;
required_device<h8_adc_device> adc;
+ optional_device<h8_dma_device> dma;
+ optional_device<h8_dma_channel_device> dma0;
+ optional_device<h8_dma_channel_device> dma1;
+ required_device<h8_dtc_device> dtc;
required_device<h8_port_device> port1;
required_device<h8_port_device> port2;
required_device<h8_port_device> port3;
@@ -70,6 +77,7 @@ protected:
required_device<h8_sci_device> sci0;
required_device<h8_sci_device> sci1;
required_device<h8_sci_device> sci2;
+ required_device<h8_watchdog_device> watchdog;
UINT32 ram_start;
UINT8 syscr;
diff --git a/src/devices/cpu/h8/h8s2357.cpp b/src/devices/cpu/h8/h8s2357.cpp
index d9a1ecc7cfa..d80f48e1551 100644
--- a/src/devices/cpu/h8/h8s2357.cpp
+++ b/src/devices/cpu/h8/h8s2357.cpp
@@ -38,8 +38,11 @@ h8s2357_device::h8s2357_device(const machine_config &mconfig, device_type type,
timer16_5(*this, "timer16:5"),
sci0(*this, "sci0"),
sci1(*this, "sci1"),
- sci2(*this, "sci2"), ram_start(0), syscr(0)
+ sci2(*this, "sci2"),
+ watchdog(*this, "watchdog")
{
+ ram_start = 0;
+ syscr = 0;
}
h8s2357_device::h8s2357_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
@@ -70,8 +73,11 @@ h8s2357_device::h8s2357_device(const machine_config &mconfig, const char *tag, d
timer16_5(*this, "timer16:5"),
sci0(*this, "sci0"),
sci1(*this, "sci1"),
- sci2(*this, "sci2")
+ sci2(*this, "sci2"),
+ watchdog(*this, "watchdog")
{
+ ram_start = 0;
+ syscr = 0;
ram_start = 0xffdc00;
}
@@ -183,6 +189,7 @@ static MACHINE_CONFIG_FRAGMENT(h8s2357)
MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
+ MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
MACHINE_CONFIG_END
DEVICE_ADDRESS_MAP_START(map, 16, h8s2357_device)
@@ -292,6 +299,8 @@ DEVICE_ADDRESS_MAP_START(map, 16, h8s2357_device)
AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
+ AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
+ AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
@@ -399,6 +408,7 @@ void h8s2357_device::internal_update(UINT64 current_time)
add_event(event_time, timer16_3->internal_update(current_time));
add_event(event_time, timer16_4->internal_update(current_time));
add_event(event_time, timer16_5->internal_update(current_time));
+ add_event(event_time, watchdog->internal_update(current_time));
recompute_bcount(event_time);
}
@@ -423,5 +433,5 @@ WRITE8_MEMBER(h8s2357_device::syscr_w)
{
syscr = data;
update_irq_filter();
- logerror("%s: syscr = %02x\n", tag(), data);
+ logerror("syscr = %02x\n", data);
}
diff --git a/src/devices/cpu/h8/h8s2357.h b/src/devices/cpu/h8/h8s2357.h
index b13c0b9aab3..fc677b565c3 100644
--- a/src/devices/cpu/h8/h8s2357.h
+++ b/src/devices/cpu/h8/h8s2357.h
@@ -24,12 +24,13 @@
#define __H8S2357_H__
#include "h8s2000.h"
+#include "h8_intc.h"
#include "h8_adc.h"
#include "h8_port.h"
-#include "h8_intc.h"
-#include "h8_sci.h"
#include "h8_timer8.h"
#include "h8_timer16.h"
+#include "h8_sci.h"
+#include "h8_watchdog.h"
class h8s2357_device : public h8s2000_device {
public:
@@ -67,6 +68,7 @@ protected:
required_device<h8_sci_device> sci0;
required_device<h8_sci_device> sci1;
required_device<h8_sci_device> sci2;
+ required_device<h8_watchdog_device> watchdog;
UINT32 ram_start;
unsigned char syscr;
diff --git a/src/devices/cpu/h8/h8s2655.cpp b/src/devices/cpu/h8/h8s2655.cpp
index a8a02dd1bee..80558108b69 100644
--- a/src/devices/cpu/h8/h8s2655.cpp
+++ b/src/devices/cpu/h8/h8s2655.cpp
@@ -34,9 +34,11 @@ h8s2655_device::h8s2655_device(const machine_config &mconfig, device_type type,
timer16_5(*this, "timer16:5"),
sci0(*this, "sci0"),
sci1(*this, "sci1"),
- sci2(*this, "sci2"), syscr(0)
+ sci2(*this, "sci2"),
+ watchdog(*this, "watchdog")
{
has_trace = true;
+ syscr = 0;
}
h8s2655_device::h8s2655_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
@@ -67,10 +69,12 @@ h8s2655_device::h8s2655_device(const machine_config &mconfig, const char *tag, d
timer16_5(*this, "timer16:5"),
sci0(*this, "sci0"),
sci1(*this, "sci1"),
- sci2(*this, "sci2")
+ sci2(*this, "sci2"),
+ watchdog(*this, "watchdog")
{
has_trace = true;
+ syscr = 0;
}
h8s2653_device::h8s2653_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
@@ -156,6 +160,7 @@ static MACHINE_CONFIG_FRAGMENT(h8s2655)
MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
+ MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
MACHINE_CONFIG_END
DEVICE_ADDRESS_MAP_START(map, 16, h8s2655_device)
@@ -266,6 +271,8 @@ DEVICE_ADDRESS_MAP_START(map, 16, h8s2655_device)
AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
+ AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
+ AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
@@ -406,6 +413,7 @@ void h8s2655_device::internal_update(UINT64 current_time)
add_event(event_time, timer16_3->internal_update(current_time));
add_event(event_time, timer16_4->internal_update(current_time));
add_event(event_time, timer16_5->internal_update(current_time));
+ add_event(event_time, watchdog->internal_update(current_time));
recompute_bcount(event_time);
}
@@ -430,5 +438,5 @@ WRITE8_MEMBER(h8s2655_device::syscr_w)
{
syscr = data;
update_irq_filter();
- logerror("%s: syscr = %02x\n", tag(), data);
+ logerror("syscr = %02x\n", data);
}
diff --git a/src/devices/cpu/h8/h8s2655.h b/src/devices/cpu/h8/h8s2655.h
index 8211f457698..47fb7e57e23 100644
--- a/src/devices/cpu/h8/h8s2655.h
+++ b/src/devices/cpu/h8/h8s2655.h
@@ -16,12 +16,13 @@
#define __H8S2655_H__
#include "h8s2600.h"
+#include "h8_intc.h"
#include "h8_adc.h"
#include "h8_port.h"
-#include "h8_intc.h"
#include "h8_timer8.h"
#include "h8_timer16.h"
#include "h8_sci.h"
+#include "h8_watchdog.h"
class h8s2655_device : public h8s2600_device {
public:
@@ -59,6 +60,7 @@ protected:
required_device<h8_sci_device> sci0;
required_device<h8_sci_device> sci1;
required_device<h8_sci_device> sci2;
+ required_device<h8_watchdog_device> watchdog;
UINT8 syscr;