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Diffstat (limited to 'src/devices/cpu/dsp56k/dsp56mem.cpp')
-rw-r--r--src/devices/cpu/dsp56k/dsp56mem.cpp156
1 files changed, 78 insertions, 78 deletions
diff --git a/src/devices/cpu/dsp56k/dsp56mem.cpp b/src/devices/cpu/dsp56k/dsp56mem.cpp
index 5f8d4e405bd..ad8cfd6320e 100644
--- a/src/devices/cpu/dsp56k/dsp56mem.cpp
+++ b/src/devices/cpu/dsp56k/dsp56mem.cpp
@@ -9,21 +9,21 @@
namespace DSP56K
{
/* IPR Accessor Implementations */
-void IPR_set(dsp56k_core* cpustate, UINT16 value)
+void IPR_set(dsp56k_core* cpustate, uint16_t value)
{
/* TODO: Is there anything else? */
IPR = value;
}
-INT8 irqa_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0003) >> 0) - 1; }
-UINT8 irqa_trigger(dsp56k_core* cpustate){ return (IPR & 0x0004) >> 2; }
-INT8 irqb_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0018) >> 3) - 1; }
-UINT8 irqb_trigger(dsp56k_core* cpustate){ return (IPR & 0x0002) >> 5; }
-INT8 codec_ipl(dsp56k_core* cpustate) { return ((IPR & 0x00c0) >> 6) - 1; }
-INT8 host_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0300) >> 8) - 1; }
-INT8 ssi0_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0c00) >> 10) - 1; }
-INT8 ssi1_ipl(dsp56k_core* cpustate) { return ((IPR & 0x3000) >> 12) - 1; }
-INT8 tm_ipl(dsp56k_core* cpustate) { return ((IPR & 0xc000) >> 14) - 1; }
+int8_t irqa_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0003) >> 0) - 1; }
+uint8_t irqa_trigger(dsp56k_core* cpustate){ return (IPR & 0x0004) >> 2; }
+int8_t irqb_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0018) >> 3) - 1; }
+uint8_t irqb_trigger(dsp56k_core* cpustate){ return (IPR & 0x0002) >> 5; }
+int8_t codec_ipl(dsp56k_core* cpustate) { return ((IPR & 0x00c0) >> 6) - 1; }
+int8_t host_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0300) >> 8) - 1; }
+int8_t ssi0_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0c00) >> 10) - 1; }
+int8_t ssi1_ipl(dsp56k_core* cpustate) { return ((IPR & 0x3000) >> 12) - 1; }
+int8_t tm_ipl(dsp56k_core* cpustate) { return ((IPR & 0xc000) >> 14) - 1; }
void mem_reset(dsp56k_core* cpustate)
{
@@ -44,7 +44,7 @@ void mem_reset(dsp56k_core* cpustate)
/************************************/
/* Host Control Register (HCR) Bits */
/************************************/
-void HCR_set(dsp56k_core* cpustate, UINT16 value)
+void HCR_set(dsp56k_core* cpustate, uint16_t value)
{
HF3_bit_set (cpustate, (value & 0x0010) >> 4);
HF2_bit_set (cpustate, (value & 0x0008) >> 3);
@@ -52,13 +52,13 @@ void HCR_set(dsp56k_core* cpustate, UINT16 value)
HTIE_bit_set(cpustate, (value & 0x0002) >> 1);
HRIE_bit_set(cpustate, (value & 0x0001) >> 0);
}
-//UINT16 HF3_bit(dsp56k_core* cpustate) { return ((HCR & 0x0010) != 0); }
-//UINT16 HF2_bit(dsp56k_core* cpustate) { return ((HCR & 0x0008) != 0); }
-UINT16 HCIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0004) != 0); }
-UINT16 HTIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0002) != 0); }
-UINT16 HRIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0001) != 0); }
+//uint16_t HF3_bit(dsp56k_core* cpustate) { return ((HCR & 0x0010) != 0); }
+//uint16_t HF2_bit(dsp56k_core* cpustate) { return ((HCR & 0x0008) != 0); }
+uint16_t HCIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0004) != 0); }
+uint16_t HTIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0002) != 0); }
+uint16_t HRIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0001) != 0); }
-void HF3_bit_set(dsp56k_core* cpustate, UINT16 value)
+void HF3_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HCR &= ~(0x0010);
@@ -66,7 +66,7 @@ void HF3_bit_set(dsp56k_core* cpustate, UINT16 value)
HF3_bit_host_set(cpustate, value);
}
-void HF2_bit_set(dsp56k_core* cpustate, UINT16 value)
+void HF2_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HCR &= ~(0x0008);
@@ -74,19 +74,19 @@ void HF2_bit_set(dsp56k_core* cpustate, UINT16 value)
HF2_bit_host_set(cpustate, value);
}
-void HCIE_bit_set(dsp56k_core* cpustate, UINT16 value)
+void HCIE_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HCR &= ~(0x0004);
HCR |= (value << 2);
}
-void HTIE_bit_set(dsp56k_core* cpustate, UINT16 value)
+void HTIE_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HCR &= ~(0x0002);
HCR |= (value << 1);
}
-void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value)
+void HRIE_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HCR &= ~(0x0001);
@@ -96,33 +96,33 @@ void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value)
/***********************************/
/* Host Status Register (HSR) Bits */
/***********************************/
-//UINT16 DMA_bit(dsp56k_core* cpustate) { return ((HSR & 0x0080) != 0); }
-//UINT16 HF1_bit(dsp56k_core* cpustate) { return ((HSR & 0x0010) != 0); }
-//UINT16 HF0_bit(dsp56k_core* cpustate) { return ((HSR & 0x0008) != 0); }
-//UINT16 HCP_bit(dsp56k_core* cpustate) { return ((HSR & 0x0004) != 0); }
-UINT16 HTDE_bit(dsp56k_core* cpustate) { return ((HSR & 0x0002) != 0); }
-UINT16 HRDF_bit(dsp56k_core* cpustate) { return ((HSR & 0x0001) != 0); }
+//uint16_t DMA_bit(dsp56k_core* cpustate) { return ((HSR & 0x0080) != 0); }
+//uint16_t HF1_bit(dsp56k_core* cpustate) { return ((HSR & 0x0010) != 0); }
+//uint16_t HF0_bit(dsp56k_core* cpustate) { return ((HSR & 0x0008) != 0); }
+//uint16_t HCP_bit(dsp56k_core* cpustate) { return ((HSR & 0x0004) != 0); }
+uint16_t HTDE_bit(dsp56k_core* cpustate) { return ((HSR & 0x0002) != 0); }
+uint16_t HRDF_bit(dsp56k_core* cpustate) { return ((HSR & 0x0001) != 0); }
-void DMA_bit_set(dsp56k_core* cpustate, UINT16 value)
+void DMA_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0080);
HSR |= (value << 7);
// TODO: 5-12 When the DMA bit is set, the DMA mode is enabled by the Host Mode bits HM0 & HM1
}
-void HF1_bit_set(dsp56k_core* cpustate, UINT16 value)
+void HF1_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0010);
HSR |= (value << 4);
}
-void HF0_bit_set(dsp56k_core* cpustate, UINT16 value)
+void HF0_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0008);
HSR |= (value << 3);
}
-void HCP_bit_set(dsp56k_core* cpustate, UINT16 value)
+void HCP_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0004);
@@ -131,7 +131,7 @@ void HCP_bit_set(dsp56k_core* cpustate, UINT16 value)
if (value && HCIE_bit(cpustate))
dsp56k_add_pending_interrupt(cpustate, "Host Command");
}
-void HTDE_bit_set(dsp56k_core* cpustate, UINT16 value)
+void HTDE_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0002);
@@ -145,7 +145,7 @@ void HTDE_bit_set(dsp56k_core* cpustate, UINT16 value)
if (!value && !RXDF_bit(cpustate))
dsp56k_host_interface_HTX_to_host(cpustate);
}
-void HRDF_bit_set(dsp56k_core* cpustate, UINT16 value)
+void HRDF_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0001);
@@ -168,7 +168,7 @@ void HRDF_bit_set(dsp56k_core* cpustate, UINT16 value)
/*****************************************/
/* Interrupt Control Register (ICR) Bits */
/*****************************************/
-void ICR_set(dsp56k_core* cpustate, UINT8 value)
+void ICR_set(dsp56k_core* cpustate, uint8_t value)
{
HF1_bit_host_set(cpustate, (value & 0x10) >> 4);
HF0_bit_host_set(cpustate, (value & 0x08) >> 3);
@@ -176,18 +176,18 @@ void ICR_set(dsp56k_core* cpustate, UINT8 value)
RREQ_bit_set(cpustate, (value & 0x01) >> 0);
}
-//UINT8 INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0)
-//UINT8 HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0)
-//UINT8 HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0)
-//UINT8 HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0)
-//UINT8 HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0)
-//UINT8 TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0)
-//UINT8 RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0)
+//uint8_t INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0)
+//uint8_t HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0)
+//uint8_t HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0)
+//uint8_t HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0)
+//uint8_t HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0)
+//uint8_t TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0)
+//uint8_t RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0)
-//void INIT_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080))
-//void HM1_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040))
-//void HM0_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020))
-void HF1_bit_host_set(dsp56k_core* cpustate, UINT8 value)
+//void INIT_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080))
+//void HM1_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040))
+//void HM0_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020))
+void HF1_bit_host_set(dsp56k_core* cpustate, uint8_t value)
{
value = value & 0x01;
ICR &= ~(0x10);
@@ -195,7 +195,7 @@ void HF1_bit_host_set(dsp56k_core* cpustate, UINT8 value)
HF1_bit_set(cpustate, value); // 5-14
}
-void HF0_bit_host_set(dsp56k_core* cpustate, UINT8 value)
+void HF0_bit_host_set(dsp56k_core* cpustate, uint8_t value)
{
value = value & 0x01;
ICR &= ~(0x08);
@@ -203,13 +203,13 @@ void HF0_bit_host_set(dsp56k_core* cpustate, UINT8 value)
HF0_bit_set(cpustate, value); // 5-13
}
-void TREQ_bit_set(dsp56k_core* cpustate, UINT8 value)
+void TREQ_bit_set(dsp56k_core* cpustate, uint8_t value)
{
value = value & 0x01;
ICR &= ~(0x02);
ICR |= (value << 1);
}
-void RREQ_bit_set(dsp56k_core* cpustate, UINT8 value)
+void RREQ_bit_set(dsp56k_core* cpustate, uint8_t value)
{
value = value & 0x01;
ICR &= ~(0x01);
@@ -227,16 +227,16 @@ void RREQ_bit_set(dsp56k_core* cpustate, UINT8 value)
/**************************************/
/* Command Vector Register (CVR) Bits */
/**************************************/
-UINT8 HV_bits(dsp56k_core* cpustate) { return (CVR & 0x1f); }
+uint8_t HV_bits(dsp56k_core* cpustate) { return (CVR & 0x1f); }
-void CVR_set(dsp56k_core* cpustate, UINT8 value)
+void CVR_set(dsp56k_core* cpustate, uint8_t value)
{
/* A single, unified place to run all callbacks for each of the bits */
HC_bit_set(cpustate, (value & 0x80) >> 7);
HV_bits_set(cpustate, (value & 0x1f));
}
-void HC_bit_set(dsp56k_core* cpustate, UINT8 value)
+void HC_bit_set(dsp56k_core* cpustate, uint8_t value)
{
value = value & 0x01;
CVR &= ~(0x80);
@@ -244,7 +244,7 @@ void HC_bit_set(dsp56k_core* cpustate, UINT8 value)
HCP_bit_set(cpustate, value); // 5-9 & 5-11
}
-void HV_bits_set(dsp56k_core* cpustate, UINT8 value)
+void HV_bits_set(dsp56k_core* cpustate, uint8_t value)
{
value = value & 0x1f;
CVR &= ~(0x1f);
@@ -255,23 +255,23 @@ void HV_bits_set(dsp56k_core* cpustate, UINT8 value)
/****************************************/
/* Interrupt Status Register (ISR) Bits */
/****************************************/
-UINT8 TXDE_bit(dsp56k_core* cpustate) { return ((ISR & 0x0002) != 0); }
-UINT8 RXDF_bit(dsp56k_core* cpustate) { return ((ISR & 0x0001) != 0); }
+uint8_t TXDE_bit(dsp56k_core* cpustate) { return ((ISR & 0x0002) != 0); }
+uint8_t RXDF_bit(dsp56k_core* cpustate) { return ((ISR & 0x0001) != 0); }
-void HF3_bit_host_set(dsp56k_core* cpustate, UINT8 value)
+void HF3_bit_host_set(dsp56k_core* cpustate, uint8_t value)
{
value = value & 0x01;
ISR &= ~(0x0010);
ISR |= (value << 4);
}
-void HF2_bit_host_set(dsp56k_core* cpustate, UINT8 value)
+void HF2_bit_host_set(dsp56k_core* cpustate, uint8_t value)
{
value = value & 0x01;
ISR &= ~(0x0008);
ISR |= (value << 3);
}
-void TXDE_bit_set(dsp56k_core* cpustate, UINT8 value)
+void TXDE_bit_set(dsp56k_core* cpustate, uint8_t value)
{
value = value & 0x01;
ISR &= ~(0x0002);
@@ -282,7 +282,7 @@ void TXDE_bit_set(dsp56k_core* cpustate, UINT8 value)
dsp56k_host_interface_host_to_HTX(cpustate);
}
-void RXDF_bit_set(dsp56k_core* cpustate, UINT8 value)
+void RXDF_bit_set(dsp56k_core* cpustate, uint8_t value)
{
value = value & 0x01;
ISR &= ~(0x0001);
@@ -347,7 +347,7 @@ void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate)
I/O INTERFACE
***************************************************************************/
/* BCR */
-void BCR_set(dsp56k_core* cpustate, UINT16 value)
+void BCR_set(dsp56k_core* cpustate, uint16_t value)
{
RH_bit_set(cpustate, (value & 0x8000) >> 15);
BS_bit_set(cpustate, (value & 0x4000) >> 14);
@@ -355,12 +355,12 @@ void BCR_set(dsp56k_core* cpustate, UINT16 value)
external_p_wait_states_set(cpustate, (value & 0x001f) >> 0);
}
-//UINT16 RH_bit(dsp56k_core* cpustate);
-//UINT16 BS_bit(dsp56k_core* cpustate);
-//UINT16 external_x_wait_states(dsp56k_core* cpustate);
-//UINT16 external_p_wait_states(dsp56k_core* cpustate);
+//uint16_t RH_bit(dsp56k_core* cpustate);
+//uint16_t BS_bit(dsp56k_core* cpustate);
+//uint16_t external_x_wait_states(dsp56k_core* cpustate);
+//uint16_t external_p_wait_states(dsp56k_core* cpustate);
-void RH_bit_set(dsp56k_core* cpustate, UINT16 value)
+void RH_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x0001;
BCR &= ~(0x8000);
@@ -368,7 +368,7 @@ void RH_bit_set(dsp56k_core* cpustate, UINT16 value)
// TODO: 4-6 Assert BR pin?
}
-void BS_bit_set(dsp56k_core* cpustate, UINT16 value)
+void BS_bit_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x0001;
BCR &= ~(0x4000);
@@ -376,13 +376,13 @@ void BS_bit_set(dsp56k_core* cpustate, UINT16 value)
// TODO: 4-6 Respond to BR pin?
}
-void external_x_wait_states_set(dsp56k_core* cpustate, UINT16 value)
+void external_x_wait_states_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x001f;
BCR &= ~(0x03e0);
BCR |= (value << 5);
}
-void external_p_wait_states_set(dsp56k_core* cpustate, UINT16 value)
+void external_p_wait_states_set(dsp56k_core* cpustate, uint16_t value)
{
value = value & 0x001f;
BCR &= ~(0x001f);
@@ -391,7 +391,7 @@ void external_p_wait_states_set(dsp56k_core* cpustate, UINT16 value)
/* Port B Control Register PBC */
-void PBC_set(dsp56k_core* cpustate, UINT16 value)
+void PBC_set(dsp56k_core* cpustate, uint16_t value)
{
if (value & 0xfffe)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PBC. Ignoring.\n");
@@ -410,7 +410,7 @@ int host_interface_active(dsp56k_core* cpustate)
#endif
/* Port B Data Direction Register (PBDDR) */
-void PBDDR_set(dsp56k_core* cpustate, UINT16 value)
+void PBDDR_set(dsp56k_core* cpustate, uint16_t value)
{
if (value & 0x8000)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PBDDR. Ignoring.\n");
@@ -423,7 +423,7 @@ void PBDDR_set(dsp56k_core* cpustate, UINT16 value)
}
/* Port B Data Register (PBD) */
-void PBD_set(dsp56k_core* cpustate, UINT16 value)
+void PBD_set(dsp56k_core* cpustate, uint16_t value)
{
if (value & 0x8000)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PBD. Ignoring.\n");
@@ -436,7 +436,7 @@ void PBD_set(dsp56k_core* cpustate, UINT16 value)
}
/* Port C Control Register (PCC) */
-void PCC_set(dsp56k_core* cpustate, UINT16 value)
+void PCC_set(dsp56k_core* cpustate, uint16_t value)
{
if (value & 0xf000)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCC. Ignoring.\n");
@@ -449,7 +449,7 @@ void PCC_set(dsp56k_core* cpustate, UINT16 value)
}
/* Port C Data Direction Register (PCDDR) */
-void PCDDR_set(dsp56k_core* cpustate, UINT16 value)
+void PCDDR_set(dsp56k_core* cpustate, uint16_t value)
{
if (value & 0xf000)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCDDR. Ignoring.\n");
@@ -462,7 +462,7 @@ void PCDDR_set(dsp56k_core* cpustate, UINT16 value)
}
/* Port C Data Register (PCD) */
-void PCD_set(dsp56k_core* cpustate, UINT16 value)
+void PCD_set(dsp56k_core* cpustate, uint16_t value)
{
if (value & 0xf000)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCD. Ignoring.\n");
@@ -557,7 +557,7 @@ READ16_MEMBER( dsp56k_device::peripheral_register_r )
return 0xbeef;
else
{
- UINT16 value = HRX; // TODO: Maybe not exactly right? Just being safe.
+ uint16_t value = HRX; // TODO: Maybe not exactly right? Just being safe.
DSP56K::HRDF_bit_set(cpustate, 0);
return value;
}
@@ -780,7 +780,7 @@ WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
/* These two functions are exposed to the outside world */
/* They represent the host side of the dsp56k's host interface */
-void dsp56k_device::host_interface_write(UINT8 offset, UINT8 data)
+void dsp56k_device::host_interface_write(uint8_t offset, uint8_t data)
{
dsp56k_core* cpustate = &m_dsp56k_core;
@@ -876,7 +876,7 @@ void dsp56k_device::host_interface_write(UINT8 offset, UINT8 data)
}
}
-UINT8 dsp56k_device::host_interface_read(UINT8 offset)
+uint8_t dsp56k_device::host_interface_read(uint8_t offset)
{
dsp56k_core* cpustate = &m_dsp56k_core;
@@ -928,7 +928,7 @@ UINT8 dsp56k_device::host_interface_read(UINT8 offset)
return 0xbf;
else
{
- UINT8 value = RXL; // TODO: Maybe not exactly right? I'm just being safe.
+ uint8_t value = RXL; // TODO: Maybe not exactly right? I'm just being safe.
DSP56K::RXDF_bit_set(cpustate, 0);
return value;
}
@@ -941,7 +941,7 @@ UINT8 dsp56k_device::host_interface_read(UINT8 offset)
}
/* MISC*/
-UINT16 dsp56k_device::get_peripheral_memory(UINT16 addr)
+uint16_t dsp56k_device::get_peripheral_memory(uint16_t addr)
{
dsp56k_core* cpustate = &m_dsp56k_core;
return cpustate->peripheral_ram[A2O(addr)];