summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/arm7
diff options
context:
space:
mode:
Diffstat (limited to 'src/devices/cpu/arm7')
-rw-r--r--src/devices/cpu/arm7/arm7.cpp38
-rw-r--r--src/devices/cpu/arm7/arm7.h18
-rw-r--r--src/devices/cpu/arm7/arm7core.h5
-rw-r--r--src/devices/cpu/arm7/arm7help.h5
-rw-r--r--src/devices/cpu/arm7/arm7thmb.cpp5
5 files changed, 37 insertions, 34 deletions
diff --git a/src/devices/cpu/arm7/arm7.cpp b/src/devices/cpu/arm7/arm7.cpp
index 19530ed9e66..7a3a7ba30db 100644
--- a/src/devices/cpu/arm7/arm7.cpp
+++ b/src/devices/cpu/arm7/arm7.cpp
@@ -148,16 +148,14 @@ arm920t_cpu_device::arm920t_cpu_device(const machine_config &mconfig, const char
}
-
-
-arm946es_cpu_device::arm946es_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
- : arm9_cpu_device(mconfig, type, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E, ENDIANNESS_LITTLE),
+arm946es_cpu_device::arm946es_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : arm9_cpu_device(mconfig, ARM946ES, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E, ENDIANNESS_LITTLE),
cp15_control(0x78)
{
m_copro_id = ARM9_COPRO_ID_MFR_ARM
- | ARM9_COPRO_ID_ARCH_V5TE
- | ARM9_COPRO_ID_PART_ARM946
- | ARM9_COPRO_ID_STEP_ARM946_A0;
+ | ARM9_COPRO_ID_ARCH_V5TE
+ | ARM9_COPRO_ID_PART_ARM946
+ | ARM9_COPRO_ID_STEP_ARM946_A0;
memset(ITCM, 0, 0x8000);
memset(DTCM, 0, 0x4000);
@@ -171,17 +169,6 @@ arm946es_cpu_device::arm946es_cpu_device(const machine_config &mconfig, device_t
cp15_itcm_reg = cp15_dtcm_reg = 0;
}
-arm946es_cpu_device::arm946es_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : arm946es_cpu_device(mconfig, ARM946ES, tag, owner, clock)
-{
-}
-
-// unknown configuration, but uses MPU not MMU, so closer to ARM946ES
-igs036_cpu_device::igs036_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : arm946es_cpu_device(mconfig, IGS036, tag, owner, clock)
-{
-}
-
pxa255_cpu_device::pxa255_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm7_cpu_device(mconfig, PXA255, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E | ARCHFLAG_XSCALE, ENDIANNESS_LITTLE)
{
@@ -202,6 +189,13 @@ sa1110_cpu_device::sa1110_cpu_device(const machine_config &mconfig, const char *
| ARM9_COPRO_ID_STEP_SA1110_A0;
}
+// unknown configuration
+igs036_cpu_device::igs036_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : arm9_cpu_device(mconfig, IGS036, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E, ENDIANNESS_LITTLE)
+{
+}
+
+
device_memory_interface::space_config_vector arm7_cpu_device::memory_space_config() const
{
return space_config_vector {
@@ -1465,6 +1459,14 @@ uint8_t arm946es_cpu_device::arm7_cpu_read8(uint32_t addr)
return m_program->read_byte(addr);
}
+WRITE32_MEMBER(igs036_cpu_device::arm7_rt_w_callback)
+{
+ arm7_cpu_device::arm7_rt_w_callback(space, offset, data, mem_mask);
+ /* disable the MMU for now, it doesn't seem to set up valid mappings
+ so could be entirely different here */
+ COPRO_CTRL &= ~COPRO_CTRL_MMU_EN;
+}
+
void arm7_cpu_device::arm7_dt_r_callback(uint32_t insn, uint32_t *prn)
{
uint8_t cpn = (insn >> 8) & 0xF;
diff --git a/src/devices/cpu/arm7/arm7.h b/src/devices/cpu/arm7/arm7.h
index 23df9469073..f6eecc4e4e1 100644
--- a/src/devices/cpu/arm7/arm7.h
+++ b/src/devices/cpu/arm7/arm7.h
@@ -626,9 +626,6 @@ public:
virtual uint32_t arm7_cpu_read16(uint32_t addr) override;
virtual uint8_t arm7_cpu_read8(uint32_t addr) override;
-protected:
- arm946es_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
-
private:
uint32_t cp15_control, cp15_itcm_base, cp15_dtcm_base, cp15_itcm_size, cp15_dtcm_size;
uint32_t cp15_itcm_end, cp15_dtcm_end, cp15_itcm_reg, cp15_dtcm_reg;
@@ -638,12 +635,6 @@ private:
void RefreshDTCM();
};
-class igs036_cpu_device : public arm946es_cpu_device
-{
-public:
- // construction/destruction
- igs036_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-};
class pxa255_cpu_device : public arm7_cpu_device
{
@@ -660,6 +651,15 @@ public:
sa1110_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
+class igs036_cpu_device : public arm9_cpu_device
+{
+public:
+ // construction/destruction
+ igs036_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ virtual DECLARE_WRITE32_MEMBER( arm7_rt_w_callback ) override;
+};
+
+
DECLARE_DEVICE_TYPE(ARM7, arm7_cpu_device)
DECLARE_DEVICE_TYPE(ARM7_BE, arm7_be_cpu_device)
DECLARE_DEVICE_TYPE(ARM7500, arm7500_cpu_device)
diff --git a/src/devices/cpu/arm7/arm7core.h b/src/devices/cpu/arm7/arm7core.h
index c33bdee9dd2..9ae499ae109 100644
--- a/src/devices/cpu/arm7/arm7core.h
+++ b/src/devices/cpu/arm7/arm7core.h
@@ -470,6 +470,11 @@ enum
COND_NV /* 0 never */
};
+#define LSL(v, s) ((v) << (s))
+#define LSR(v, s) ((v) >> (s))
+#define ROL(v, s) (LSL((v), (s)) | (LSR((v), 32u - (s))))
+#define ROR(v, s) (LSR((v), (s)) | (LSL((v), 32u - (s))))
+
/* Convenience Macros */
#define R15 m_r[eR15]
#define SPSR 17 // SPSR is always the 18th register in our 0 based array sRegisterTable[][18]
diff --git a/src/devices/cpu/arm7/arm7help.h b/src/devices/cpu/arm7/arm7help.h
index c006bfbf1af..4b0b4f21c8a 100644
--- a/src/devices/cpu/arm7/arm7help.h
+++ b/src/devices/cpu/arm7/arm7help.h
@@ -166,8 +166,3 @@
#define WRITE32(addr,data) arm7_cpu_write32(addr,data)
#define PTR_READ32 &arm7_cpu_read32
#define PTR_WRITE32 &arm7_cpu_write32
-
-#define LSL(v, s) ((v) << (s))
-#define LSR(v, s) ((v) >> (s))
-#define ROL(v, s) (LSL((v), (s)) | (LSR((v), 32u - (s))))
-#define ROR(v, s) (LSR((v), (s)) | (LSL((v), 32u - (s))))
diff --git a/src/devices/cpu/arm7/arm7thmb.cpp b/src/devices/cpu/arm7/arm7thmb.cpp
index a6fe0400721..0d25d62fcf3 100644
--- a/src/devices/cpu/arm7/arm7thmb.cpp
+++ b/src/devices/cpu/arm7/arm7thmb.cpp
@@ -1307,7 +1307,8 @@ void arm7_cpu_device::tg0b_f(uint32_t pc, uint32_t op)
// "The address should normally be a word aligned quantity and non-word aligned addresses do not affect the instruction."
// "However, the bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system."
-// Endrift says LDMIA/STMIA ignore the low 2 bits and GBA Test Suite assumes it.
+// GBA "BB Ball" performs an unaligned read with A[1:0] = 2 and expects A[1] not to be ignored [BP 800B90A,(R4&3)!=0]
+// GBA "Gadget Racers" performs an unaligned read with A[1:0] = 1 and expects A[0] to be ignored [BP B72,(R0&3)!=0]
void arm7_cpu_device::tg0c_0(uint32_t pc, uint32_t op) /* Store */
{
@@ -1334,7 +1335,7 @@ void arm7_cpu_device::tg0c_1(uint32_t pc, uint32_t op) /* Load */
{
if (op & (1 << offs))
{
- SetRegister(offs, READ32(ld_st_address & ~3));
+ SetRegister(offs, READ32(ld_st_address & ~1));
ld_st_address += 4;
}
}