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Diffstat (limited to 'src/devices/cpu/arm7/arm7tdrc.hxx')
-rw-r--r--src/devices/cpu/arm7/arm7tdrc.hxx592
1 files changed, 296 insertions, 296 deletions
diff --git a/src/devices/cpu/arm7/arm7tdrc.hxx b/src/devices/cpu/arm7/arm7tdrc.hxx
index ee0573a32e7..fac7a70f7fa 100644
--- a/src/devices/cpu/arm7/arm7tdrc.hxx
+++ b/src/devices/cpu/arm7/arm7tdrc.hxx
@@ -7,7 +7,7 @@
const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[0x40*0x10] =
{
-// #define THUMB_SHIFT_R ((UINT16)0x0800)
+// #define THUMB_SHIFT_R ((uint16_t)0x0800)
&arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
&arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
&arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
@@ -16,7 +16,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
&arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
&arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
-// #define THUMB_INSN_ADDSUB ((UINT16)0x0800) // #define THUMB_ADDSUB_TYPE ((UINT16)0x0600)
+// #define THUMB_INSN_ADDSUB ((uint16_t)0x0800) // #define THUMB_ADDSUB_TYPE ((uint16_t)0x0600)
&arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
&arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
&arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
@@ -25,7 +25,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11,
&arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12,
&arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13,
-// #define THUMB_INSN_CMP ((UINT16)0x0800)
+// #define THUMB_INSN_CMP ((uint16_t)0x0800)
&arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
&arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
&arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
@@ -34,7 +34,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
&arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
&arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
-// #define THUMB_INSN_SUB ((UINT16)0x0800)
+// #define THUMB_INSN_SUB ((uint16_t)0x0800)
&arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
&arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
&arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
@@ -43,7 +43,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
&arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
&arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
-//#define THUMB_GROUP4_TYPE ((UINT16)0x0c00) //#define THUMB_ALUOP_TYPE ((UINT16)0x03c0) // #define THUMB_HIREG_OP ((UINT16)0x0300) // #define THUMB_HIREG_H ((UINT16)0x00c0)
+//#define THUMB_GROUP4_TYPE ((uint16_t)0x0c00) //#define THUMB_ALUOP_TYPE ((uint16_t)0x03c0) // #define THUMB_HIREG_OP ((uint16_t)0x0300) // #define THUMB_HIREG_H ((uint16_t)0x00c0)
&arm7_cpu_device::drctg04_00_00, &arm7_cpu_device::drctg04_00_01, &arm7_cpu_device::drctg04_00_02, &arm7_cpu_device::drctg04_00_03, &arm7_cpu_device::drctg04_00_04, &arm7_cpu_device::drctg04_00_05, &arm7_cpu_device::drctg04_00_06, &arm7_cpu_device::drctg04_00_07,
&arm7_cpu_device::drctg04_00_08, &arm7_cpu_device::drctg04_00_09, &arm7_cpu_device::drctg04_00_0a, &arm7_cpu_device::drctg04_00_0b, &arm7_cpu_device::drctg04_00_0c, &arm7_cpu_device::drctg04_00_0d, &arm7_cpu_device::drctg04_00_0e, &arm7_cpu_device::drctg04_00_0f,
&arm7_cpu_device::drctg04_01_00, &arm7_cpu_device::drctg04_01_01, &arm7_cpu_device::drctg04_01_02, &arm7_cpu_device::drctg04_01_03, &arm7_cpu_device::drctg04_01_10, &arm7_cpu_device::drctg04_01_11, &arm7_cpu_device::drctg04_01_12, &arm7_cpu_device::drctg04_01_13,
@@ -52,7 +52,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
&arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
&arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
-//#define THUMB_GROUP5_TYPE ((UINT16)0x0e00)
+//#define THUMB_GROUP5_TYPE ((uint16_t)0x0e00)
&arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0,
&arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1,
&arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2,
@@ -61,7 +61,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5,
&arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6,
&arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7,
-//#define THUMB_LSOP_L ((UINT16)0x0800)
+//#define THUMB_LSOP_L ((uint16_t)0x0800)
&arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
&arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
&arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
@@ -70,7 +70,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
&arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
&arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
-//#define THUMB_LSOP_L ((UINT16)0x0800)
+//#define THUMB_LSOP_L ((uint16_t)0x0800)
&arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
&arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
&arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
@@ -79,7 +79,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
&arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
&arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
-// #define THUMB_HALFOP_L ((UINT16)0x0800)
+// #define THUMB_HALFOP_L ((uint16_t)0x0800)
&arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
&arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
&arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
@@ -88,7 +88,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
&arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
&arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
-// #define THUMB_STACKOP_L ((UINT16)0x0800)
+// #define THUMB_STACKOP_L ((uint16_t)0x0800)
&arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
&arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
&arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
@@ -97,7 +97,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
&arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
&arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
-// #define THUMB_RELADDR_SP ((UINT16)0x0800)
+// #define THUMB_RELADDR_SP ((uint16_t)0x0800)
&arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
&arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
&arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
@@ -106,7 +106,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
&arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
&arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
-// #define THUMB_STACKOP_TYPE ((UINT16)0x0f00)
+// #define THUMB_STACKOP_TYPE ((uint16_t)0x0f00)
&arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_1, &arm7_cpu_device::drctg0b_1, &arm7_cpu_device::drctg0b_1, &arm7_cpu_device::drctg0b_1,
&arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_3, &arm7_cpu_device::drctg0b_3, &arm7_cpu_device::drctg0b_3, &arm7_cpu_device::drctg0b_3,
&arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_5, &arm7_cpu_device::drctg0b_5, &arm7_cpu_device::drctg0b_5, &arm7_cpu_device::drctg0b_5,
@@ -115,7 +115,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_b, &arm7_cpu_device::drctg0b_b, &arm7_cpu_device::drctg0b_b, &arm7_cpu_device::drctg0b_b,
&arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_d, &arm7_cpu_device::drctg0b_d, &arm7_cpu_device::drctg0b_d, &arm7_cpu_device::drctg0b_d,
&arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_f, &arm7_cpu_device::drctg0b_f, &arm7_cpu_device::drctg0b_f, &arm7_cpu_device::drctg0b_f,
-// #define THUMB_MULTLS ((UINT16)0x0800)
+// #define THUMB_MULTLS ((uint16_t)0x0800)
&arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
&arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
&arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
@@ -124,7 +124,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
&arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
&arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
-// #define THUMB_COND_TYPE ((UINT16)0x0f00)
+// #define THUMB_COND_TYPE ((uint16_t)0x0f00)
&arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_1, &arm7_cpu_device::drctg0d_1, &arm7_cpu_device::drctg0d_1, &arm7_cpu_device::drctg0d_1,
&arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_3, &arm7_cpu_device::drctg0d_3, &arm7_cpu_device::drctg0d_3, &arm7_cpu_device::drctg0d_3,
&arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_5, &arm7_cpu_device::drctg0d_5, &arm7_cpu_device::drctg0d_5, &arm7_cpu_device::drctg0d_5,
@@ -133,7 +133,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_b, &arm7_cpu_device::drctg0d_b, &arm7_cpu_device::drctg0d_b, &arm7_cpu_device::drctg0d_b,
&arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_d, &arm7_cpu_device::drctg0d_d, &arm7_cpu_device::drctg0d_d, &arm7_cpu_device::drctg0d_d,
&arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_f, &arm7_cpu_device::drctg0d_f, &arm7_cpu_device::drctg0d_f, &arm7_cpu_device::drctg0d_f,
-// #define THUMB_BLOP_LO ((UINT16)0x0800)
+// #define THUMB_BLOP_LO ((uint16_t)0x0800)
&arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
&arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
&arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
@@ -142,7 +142,7 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
&arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
&arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
&arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
-// #define THUMB_BLOP_LO ((UINT16)0x0800)
+// #define THUMB_BLOP_LO ((uint16_t)0x0800)
&arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
&arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
&arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
@@ -157,10 +157,10 @@ const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[
void arm7_cpu_device::drctg00_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Shift left */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- INT32 offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ int32_t offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
UML_MOV(block, uml::I0, DRC_RS); // rrs
if (offs != 0)
@@ -184,10 +184,10 @@ void arm7_cpu_device::drctg00_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg00_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Shift right */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- INT32 offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ int32_t offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
UML_MOV(block, uml::I0, DRC_RS); // rrs
if (offs != 0)
@@ -218,10 +218,10 @@ void arm7_cpu_device::drctg00_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg01_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- INT32 offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ int32_t offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
/* ASR.. */
UML_MOV(block, uml::I0, DRC_RS);
@@ -262,40 +262,40 @@ void arm7_cpu_device::drctg01_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg01_10(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rn = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rn = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_ADD(block, DRC_REG(rd), DRC_REG(rs), DRC_REG(rn));
DRCHandleThumbALUAddFlags(DRC_REG(rd), DRC_REG(rs), DRC_REG(rn));
}
void arm7_cpu_device::drctg01_11(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* SUB Rd, Rs, Rn */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rn = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rn = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_SUB(block, DRC_REG(rd), DRC_REG(rs), DRC_REG(rn));
DRCHandleThumbALUSubFlags(DRC_REG(rd), DRC_REG(rs), DRC_REG(rn));
}
void arm7_cpu_device::drctg01_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ADD Rd, Rs, #imm */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_ADD(block, DRC_REG(rd), DRC_REG(rs), imm);
DRCHandleThumbALUAddFlags(DRC_REG(rd), DRC_REG(rs), imm);
}
void arm7_cpu_device::drctg01_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* SUB Rd, Rs, #imm */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_SUB(block, DRC_REG(rd), DRC_REG(rs), imm);
DRCHandleThumbALUSubFlags(DRC_REG(rd), DRC_REG(rs), imm);
}
@@ -304,9 +304,9 @@ void arm7_cpu_device::drctg01_13(drcuml_block *block, compiler_state *compiler,
void arm7_cpu_device::drctg02_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
- UINT32 op2 = (op & THUMB_INSN_IMM);
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
+ uint32_t op2 = (op & THUMB_INSN_IMM);
UML_MOV(block, DRC_REG(rd), op2);
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
DRCHandleALUNZFlags(DRC_REG(rd));
@@ -316,9 +316,9 @@ void arm7_cpu_device::drctg02_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg02_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
- UINT32 op2 = op & THUMB_INSN_IMM;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
+ uint32_t op2 = op & THUMB_INSN_IMM;
UML_SUB(block, uml::I3, DRC_REG(rn), op2);
DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rn), op2);
@@ -328,20 +328,20 @@ void arm7_cpu_device::drctg02_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg03_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ADD Rd, #Offset8 */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
- UINT32 op2 = op & THUMB_INSN_IMM;
- UINT32 rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
+ uint32_t op2 = op & THUMB_INSN_IMM;
+ uint32_t rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
UML_ADD(block, DRC_REG(rd), DRC_REG(rn), op2);
DRCHandleThumbALUAddFlags(DRC_REG(rd), DRC_REG(rn), op2);
}
void arm7_cpu_device::drctg03_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* SUB Rd, #Offset8 */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
- UINT32 op2 = op & THUMB_INSN_IMM;
- UINT32 rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
+ uint32_t op2 = op & THUMB_INSN_IMM;
+ uint32_t rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
UML_SUB(block, DRC_REG(rd), DRC_REG(rn), op2);
DRCHandleThumbALUSubFlags(DRC_REG(rd), DRC_REG(rn), op2);
}
@@ -350,9 +350,9 @@ void arm7_cpu_device::drctg03_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg04_00_00(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* AND Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_AND(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs));
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
DRCHandleALUNZFlags(DRC_REG(rd));
@@ -362,9 +362,9 @@ void arm7_cpu_device::drctg04_00_00(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_01(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* EOR Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_XOR(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs));
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
DRCHandleALUNZFlags(DRC_REG(rd));
@@ -374,9 +374,9 @@ void arm7_cpu_device::drctg04_00_01(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_02(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* LSL Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
uml::code_label skip;
uml::code_label offsg32;
uml::code_label offs32;
@@ -421,9 +421,9 @@ void arm7_cpu_device::drctg04_00_02(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_03(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* LSR Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
uml::code_label skip;
uml::code_label offsg32;
uml::code_label offs32;
@@ -466,9 +466,9 @@ void arm7_cpu_device::drctg04_00_03(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_04(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ASR Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
uml::code_label skip;
uml::code_label offsg32;
uml::code_label offs32;
@@ -514,9 +514,9 @@ void arm7_cpu_device::drctg04_00_04(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_05(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ADC Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_TEST(block, DRC_CPSR, C_MASK);
UML_MOVc(block, uml::COND_NZ, uml::I3, 1);
UML_MOVc(block, uml::COND_Z, uml::I3, 0);
@@ -528,9 +528,9 @@ void arm7_cpu_device::drctg04_00_05(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_06(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* SBC Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_TEST(block, DRC_CPSR, C_MASK);
UML_MOVc(block, uml::COND_NZ, uml::I3, 0);
UML_MOVc(block, uml::COND_Z, uml::I3, 1);
@@ -542,9 +542,9 @@ void arm7_cpu_device::drctg04_00_06(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_07(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ROR Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_MOV(block, uml::I0, DRC_REG(rd));
UML_AND(block, uml::I1, DRC_REG(rs), 0x1f);
UML_SHR(block, DRC_REG(rd), uml::I0, uml::I1);
@@ -564,9 +564,9 @@ void arm7_cpu_device::drctg04_00_07(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_08(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* TST Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
UML_AND(block, uml::I2, DRC_REG(rd), DRC_REG(rs));
DRCHandleALUNZFlags(uml::I2);
@@ -576,9 +576,9 @@ void arm7_cpu_device::drctg04_00_08(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_09(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* NEG Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_MOV(block, uml::I3, DRC_REG(rs));
UML_SUB(block, DRC_REG(rd), 0, uml::I3);
DRCHandleThumbALUSubFlags(DRC_REG(rd), 0, uml::I3);
@@ -586,27 +586,27 @@ void arm7_cpu_device::drctg04_00_09(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_0a(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* CMP Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_SUB(block, uml::I3, DRC_REG(rd), DRC_REG(rs));
DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
}
void arm7_cpu_device::drctg04_00_0b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* CMN Rd, Rs - check flags, add dasm */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_ADD(block, uml::I3, DRC_REG(rd), DRC_REG(rs));
DRCHandleThumbALUAddFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
}
void arm7_cpu_device::drctg04_00_0c(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ORR Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_OR(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs));
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
DRCHandleALUNZFlags(DRC_REG(rd));
@@ -616,9 +616,9 @@ void arm7_cpu_device::drctg04_00_0c(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_0d(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* MUL Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
UML_MULU(block, DRC_REG(rd), uml::I1, DRC_REG(rd), DRC_REG(rs));
DRCHandleALUNZFlags(DRC_REG(rd));
@@ -628,9 +628,9 @@ void arm7_cpu_device::drctg04_00_0d(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_0e(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* BIC Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
UML_XOR(block, uml::I0, DRC_REG(rs), ~0);
UML_AND(block, DRC_REG(rd), DRC_REG(rd), uml::I0);
@@ -641,9 +641,9 @@ void arm7_cpu_device::drctg04_00_0e(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_00_0f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* MVN Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_XOR(block, uml::I0, DRC_REG(rs), ~0);
UML_MOV(block, DRC_REG(rd), uml::I0);
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
@@ -656,16 +656,16 @@ void arm7_cpu_device::drctg04_00_0f(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_01_00(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: G4-1-0 Undefined Thumb instruction: %04x %x\n", pc, op, (op & THUMB_HIREG_H) >> THUMB_HIREG_H_SHIFT);
}
void arm7_cpu_device::drctg04_01_01(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ADD Rd, HRs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_ADD(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs+8));
if (rs == 7)
{
@@ -676,9 +676,9 @@ void arm7_cpu_device::drctg04_01_01(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_01_02(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ADD HRd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_ADD(block, DRC_REG(rd+8), DRC_REG(rd+8), DRC_REG(rs));
if (rd == 7)
{
@@ -689,9 +689,9 @@ void arm7_cpu_device::drctg04_01_02(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_01_03(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Add HRd, HRs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_ADD(block, DRC_REG(rd+8), DRC_REG(rd+8), DRC_REG(rs+8));
// emulate the effects of pre-fetch
if (rs == 7)
@@ -707,36 +707,36 @@ void arm7_cpu_device::drctg04_01_03(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_01_10(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* CMP Rd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_SUB(block, uml::I3, DRC_REG(rd), DRC_REG(rs));
DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
}
void arm7_cpu_device::drctg04_01_11(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* CMP Rd, Hs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_SUB(block, uml::I3, DRC_REG(rd), DRC_REG(rs+8));
DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs+8));
}
void arm7_cpu_device::drctg04_01_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* CMP Hd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_SUB(block, uml::I3, DRC_REG(rd+8), DRC_REG(rs));
DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd+8), DRC_REG(rs));
}
void arm7_cpu_device::drctg04_01_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* CMP Hd, Hs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_SUB(block, uml::I3, DRC_REG(rd+8), DRC_REG(rs+8));
DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd+8), DRC_REG(rs+8));
}
@@ -745,18 +745,18 @@ void arm7_cpu_device::drctg04_01_13(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_01_20(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* MOV Rd, Rs (undefined) */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_MOV(block, DRC_REG(rd), DRC_REG(rs));
UML_ADD(block, DRC_PC, DRC_PC, 2);
}
void arm7_cpu_device::drctg04_01_21(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* MOV Rd, Hs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_MOV(block, DRC_REG(rd), DRC_REG(rs+8));
if (rs == 7)
{
@@ -767,9 +767,9 @@ void arm7_cpu_device::drctg04_01_21(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_01_22(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* MOV Hd, Rs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_MOV(block, DRC_REG(rd+8), DRC_REG(rs));
// CHECKME
if (rd != 7)
@@ -784,9 +784,9 @@ void arm7_cpu_device::drctg04_01_22(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_01_23(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* MOV Hd, Hs */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 rd = op & THUMB_HIREG_RD;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rd = op & THUMB_HIREG_RD;
UML_MOV(block, DRC_REG(rd+8), DRC_REG(rs+8));
if (rs == 7)
{
@@ -805,10 +805,10 @@ void arm7_cpu_device::drctg04_01_23(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_01_30(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
+ uint32_t op = desc->opptr.l[0];
uml::code_label switch_state;
uml::code_label done;
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
UML_MOV(block, uml::I0, DRC_REG(rs));
UML_TEST(block, uml::I0, 1);
UML_JMPc(block, uml::COND_Z, switch_state = compiler->labelnum++);
@@ -828,10 +828,10 @@ void arm7_cpu_device::drctg04_01_30(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_01_31(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
+ uint32_t op = desc->opptr.l[0];
uml::code_label switch_state;
uml::code_label done;
- UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
+ uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
UML_MOV(block, uml::I0, DRC_REG(rs+8));
if(rs == 7)
{
@@ -855,23 +855,23 @@ void arm7_cpu_device::drctg04_01_31(drcuml_block *block, compiler_state *compile
void arm7_cpu_device::drctg04_01_32(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg04_01_33(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg04_0203(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
- UINT32 imm = 4 + ((op & THUMB_INSN_IMM) << 2);
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
+ uint32_t imm = 4 + ((op & THUMB_INSN_IMM) << 2);
UML_AND(block, uml::I0, DRC_PC, ~2);
UML_ADD(block, uml::I0, uml::I0, imm);
UML_CALLH(block, *m_impstate.read32);
@@ -883,10 +883,10 @@ void arm7_cpu_device::drctg04_0203(drcuml_block *block, compiler_state *compiler
void arm7_cpu_device::drctg05_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* STR Rd, [Rn, Rm] */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
- UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
- UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
+ uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
+ uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
UML_MOV(block, uml::I1, DRC_REG(rd));
UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
UML_CALLH(block, *m_impstate.write32);
@@ -895,10 +895,10 @@ void arm7_cpu_device::drctg05_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg05_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* STRH Rd, [Rn, Rm] */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
- UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
- UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
+ uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
+ uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
UML_MOV(block, uml::I1, DRC_REG(rd));
UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
UML_CALLH(block, *m_impstate.write16);
@@ -907,10 +907,10 @@ void arm7_cpu_device::drctg05_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg05_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* STRB Rd, [Rn, Rm] */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
- UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
- UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
+ uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
+ uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
UML_MOV(block, uml::I1, DRC_REG(rd));
UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
UML_CALLH(block, *m_impstate.write16);
@@ -919,10 +919,10 @@ void arm7_cpu_device::drctg05_2(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg05_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* LDSB Rd, [Rn, Rm] todo, add dasm */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
- UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
- UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
+ uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
+ uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
UML_CALLH(block, *m_impstate.read8);
UML_SEXT(block, DRC_REG(rd), uml::I0, uml::SIZE_BYTE);
@@ -931,10 +931,10 @@ void arm7_cpu_device::drctg05_3(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg05_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* LDR Rd, [Rn, Rm] */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
- UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
- UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
+ uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
+ uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
UML_CALLH(block, *m_impstate.read32);
UML_MOV(block, DRC_REG(rd), uml::I0);
@@ -943,10 +943,10 @@ void arm7_cpu_device::drctg05_4(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg05_5(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* LDRH Rd, [Rn, Rm] */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
- UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
- UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
+ uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
+ uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
UML_CALLH(block, *m_impstate.read16);
UML_MOV(block, DRC_REG(rd), uml::I0);
@@ -955,10 +955,10 @@ void arm7_cpu_device::drctg05_5(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg05_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* LDRB Rd, [Rn, Rm] */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
- UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
- UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
+ uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
+ uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
UML_CALLH(block, *m_impstate.read8);
UML_MOV(block, DRC_REG(rd), uml::I0);
@@ -967,10 +967,10 @@ void arm7_cpu_device::drctg05_6(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg05_7(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* LDSH Rd, [Rn, Rm] */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
- UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
- UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
+ uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
+ uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
UML_CALLH(block, *m_impstate.read16);
UML_SEXT(block, DRC_REG(rd), uml::I0, uml::SIZE_WORD);
@@ -981,10 +981,10 @@ void arm7_cpu_device::drctg05_7(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg06_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Store */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = op & THUMB_ADDSUB_RD;
- INT32 offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = op & THUMB_ADDSUB_RD;
+ int32_t offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
UML_ADD(block, uml::I0, DRC_REG(rn), offs);
UML_MOV(block, uml::I1, DRC_REG(rd));
UML_CALLH(block, *m_impstate.write32);
@@ -993,10 +993,10 @@ void arm7_cpu_device::drctg06_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg06_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Load */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = op & THUMB_ADDSUB_RD;
- INT32 offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = op & THUMB_ADDSUB_RD;
+ int32_t offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
UML_ADD(block, uml::I0, DRC_REG(rn), offs);
UML_CALLH(block, *m_impstate.read32);
UML_MOV(block, DRC_REG(rd), uml::I0);
@@ -1007,10 +1007,10 @@ void arm7_cpu_device::drctg06_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg07_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Store */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = op & THUMB_ADDSUB_RD;
- INT32 offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = op & THUMB_ADDSUB_RD;
+ int32_t offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
UML_ADD(block, uml::I0, DRC_REG(rn), offs);
UML_MOV(block, uml::I1, DRC_REG(rd));
UML_CALLH(block, *m_impstate.write8);
@@ -1019,10 +1019,10 @@ void arm7_cpu_device::drctg07_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg07_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Load */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = op & THUMB_ADDSUB_RD;
- INT32 offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = op & THUMB_ADDSUB_RD;
+ int32_t offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
UML_ADD(block, uml::I0, DRC_REG(rn), offs);
UML_CALLH(block, *m_impstate.read8);
UML_MOV(block, DRC_REG(rd), uml::I0);
@@ -1033,10 +1033,10 @@ void arm7_cpu_device::drctg07_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg08_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Store */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 offs = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
- UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t offs = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
+ uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_ADD(block, uml::I0, DRC_REG(rn), offs << 1);
UML_MOV(block, uml::I1, DRC_REG(rd));
UML_CALLH(block, *m_impstate.write16);
@@ -1045,10 +1045,10 @@ void arm7_cpu_device::drctg08_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg08_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Load */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 offs = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
- UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
- UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t offs = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
+ uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
+ uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UML_ADD(block, uml::I0, DRC_REG(rn), offs << 1);
UML_CALLH(block, *m_impstate.read16);
UML_MOV(block, DRC_REG(rd), uml::I0);
@@ -1059,9 +1059,9 @@ void arm7_cpu_device::drctg08_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg09_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Store */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
- INT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
+ int32_t offs = (uint8_t)(op & THUMB_INSN_IMM) << 2;
UML_ADD(block, uml::I0, DRC_REG(13), offs);
UML_MOV(block, uml::I1, DRC_REG(rd));
UML_CALLH(block, *m_impstate.write32);
@@ -1070,9 +1070,9 @@ void arm7_cpu_device::drctg09_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg09_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Load */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
- UINT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
+ uint32_t offs = (uint8_t)(op & THUMB_INSN_IMM) << 2;
UML_ADD(block, uml::I0, DRC_REG(13), offs);
UML_CALLH(block, *m_impstate.read32);
UML_MOV(block, DRC_REG(rd), uml::I0);
@@ -1083,9 +1083,9 @@ void arm7_cpu_device::drctg09_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0a_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ADD Rd, PC, #nn */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
- INT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
+ int32_t offs = (uint8_t)(op & THUMB_INSN_IMM) << 2;
UML_ADD(block, uml::I0, DRC_PC, 4);
UML_AND(block, uml::I0, uml::I0, ~2);
UML_ADD(block, DRC_REG(rd), uml::I0, offs);
@@ -1094,9 +1094,9 @@ void arm7_cpu_device::drctg0a_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0a_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ADD Rd, SP, #nn */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
- INT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
+ int32_t offs = (uint8_t)(op & THUMB_INSN_IMM) << 2;
UML_ADD(block, DRC_REG(rd), DRC_REG(13), offs);
UML_ADD(block, DRC_PC, DRC_PC, 2);
}
@@ -1105,8 +1105,8 @@ void arm7_cpu_device::drctg0a_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0b_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* ADD SP, #imm */
{
- UINT32 op = desc->opptr.l[0];
- INT32 addr = (op & THUMB_INSN_IMM);
+ uint32_t op = desc->opptr.l[0];
+ int32_t addr = (op & THUMB_INSN_IMM);
addr &= ~THUMB_INSN_IMM_S;
addr = ((op & THUMB_INSN_IMM_S) ? -(addr << 2) : (addr << 2));
UML_ADD(block, DRC_REG(13), DRC_REG(13), addr);
@@ -1115,29 +1115,29 @@ void arm7_cpu_device::drctg0b_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0b_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg0b_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg0b_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg0b_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* PUSH {Rlist} */
{
- UINT32 op = desc->opptr.l[0];
- for (INT32 offs = 7; offs >= 0; offs--)
+ uint32_t op = desc->opptr.l[0];
+ for (int32_t offs = 7; offs >= 0; offs--)
{
if (op & (1 << offs))
{
@@ -1152,12 +1152,12 @@ void arm7_cpu_device::drctg0b_4(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0b_5(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* PUSH {Rlist}{LR} */
{
- UINT32 op = desc->opptr.l[0];
+ uint32_t op = desc->opptr.l[0];
UML_SUB(block, DRC_REG(13), DRC_REG(13), 4);
UML_MOV(block, uml::I0, DRC_REG(13));
UML_MOV(block, uml::I1, DRC_REG(14));
UML_CALLH(block, *m_impstate.write32);
- for (INT32 offs = 7; offs >= 0; offs--)
+ for (int32_t offs = 7; offs >= 0; offs--)
{
if (op & (1 << offs))
{
@@ -1172,50 +1172,50 @@ void arm7_cpu_device::drctg0b_5(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0b_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg0b_7(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg0b_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg0b_9(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg0b_a(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg0b_b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg0b_c(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* POP {Rlist} */
{
- UINT32 op = desc->opptr.l[0];
- for (INT32 offs = 0; offs < 8; offs++)
+ uint32_t op = desc->opptr.l[0];
+ for (int32_t offs = 0; offs < 8; offs++)
{
if (op & (1 << offs))
{
@@ -1230,11 +1230,11 @@ void arm7_cpu_device::drctg0b_c(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0b_d(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* POP {Rlist}{PC} */
{
- UINT32 op = desc->opptr.l[0];
+ uint32_t op = desc->opptr.l[0];
uml::code_label arch5up;
uml::code_label done;
uml::code_label switch_mode;
- for (INT32 offs = 0; offs < 8; offs++)
+ for (int32_t offs = 0; offs < 8; offs++)
{
if (op & (1 << offs))
{
@@ -1273,15 +1273,15 @@ void arm7_cpu_device::drctg0b_d(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0b_e(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
void arm7_cpu_device::drctg0b_f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
}
@@ -1295,10 +1295,10 @@ void arm7_cpu_device::drctg0b_f(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0c_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Store */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
UML_MOV(block, uml::I2, DRC_REG(rd));
- for (INT32 offs = 0; offs < 8; offs++)
+ for (int32_t offs = 0; offs < 8; offs++)
{
if (op & (1 << offs))
{
@@ -1314,11 +1314,11 @@ void arm7_cpu_device::drctg0c_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0c_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* Load */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
int rd_in_list = op & (1 << rd);
UML_MOV(block, uml::I2, DRC_REG(rd));
- for (INT32 offs = 0; offs < 8; offs++)
+ for (int32_t offs = 0; offs < 8; offs++)
{
if (op & (1 << offs))
{
@@ -1338,8 +1338,8 @@ void arm7_cpu_device::drctg0c_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_EQ:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, Z_MASK);
UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
UML_MOVc(block, uml::COND_Z, uml::I0, 2);
@@ -1348,8 +1348,8 @@ void arm7_cpu_device::drctg0d_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_NE:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, Z_MASK);
UML_MOVc(block, uml::COND_Z, uml::I0, offs);
UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
@@ -1358,8 +1358,8 @@ void arm7_cpu_device::drctg0d_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_CS:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, C_MASK);
UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
UML_MOVc(block, uml::COND_Z, uml::I0, 2);
@@ -1368,8 +1368,8 @@ void arm7_cpu_device::drctg0d_2(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_CC:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, C_MASK);
UML_MOVc(block, uml::COND_Z, uml::I0, offs);
UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
@@ -1378,8 +1378,8 @@ void arm7_cpu_device::drctg0d_3(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_MI:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, N_MASK);
UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
UML_MOVc(block, uml::COND_Z, uml::I0, 2);
@@ -1388,8 +1388,8 @@ void arm7_cpu_device::drctg0d_4(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_5(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_PL:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, N_MASK);
UML_MOVc(block, uml::COND_Z, uml::I0, offs);
UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
@@ -1398,8 +1398,8 @@ void arm7_cpu_device::drctg0d_5(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_VS:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, V_MASK);
UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
UML_MOVc(block, uml::COND_Z, uml::I0, 2);
@@ -1408,8 +1408,8 @@ void arm7_cpu_device::drctg0d_6(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_7(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_VC:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, V_MASK);
UML_MOVc(block, uml::COND_Z, uml::I0, offs);
UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
@@ -1418,8 +1418,8 @@ void arm7_cpu_device::drctg0d_7(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_HI:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, C_MASK);
UML_MOVc(block, uml::COND_NZ, uml::I0, 1);
UML_MOVc(block, uml::COND_Z, uml::I0, 0);
@@ -1435,8 +1435,8 @@ void arm7_cpu_device::drctg0d_8(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_9(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_LS:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, C_MASK);
UML_MOVc(block, uml::COND_Z, uml::I0, 1);
UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
@@ -1452,8 +1452,8 @@ void arm7_cpu_device::drctg0d_9(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_a(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_GE:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, N_MASK);
UML_MOVc(block, uml::COND_Z, uml::I0, 1);
UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
@@ -1468,8 +1468,8 @@ void arm7_cpu_device::drctg0d_a(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_LT:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, N_MASK);
UML_MOVc(block, uml::COND_Z, uml::I0, 1);
UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
@@ -1484,8 +1484,8 @@ void arm7_cpu_device::drctg0d_b(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_c(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_GT:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, N_MASK);
UML_MOVc(block, uml::COND_Z, uml::I0, 1);
UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
@@ -1507,8 +1507,8 @@ void arm7_cpu_device::drctg0d_c(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_d(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_LE:
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = ((INT8)(op & THUMB_INSN_IMM) << 1) + 4;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
UML_TEST(block, DRC_CPSR, N_MASK);
UML_MOVc(block, uml::COND_Z, uml::I0, 1);
UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
@@ -1530,8 +1530,8 @@ void arm7_cpu_device::drctg0d_d(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0d_e(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) // COND_AL:
{
- UINT32 op = desc->opptr.l[0];
- UINT32 pc = desc->pc;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t pc = desc->pc;
fatalerror("%08x: Undefined Thumb instruction: %04x (ARM9 reserved)\n", pc, op);
}
@@ -1545,8 +1545,8 @@ void arm7_cpu_device::drctg0d_f(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0e_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- INT32 offs = (op & THUMB_BRANCH_OFFS) << 1;
+ uint32_t op = desc->opptr.l[0];
+ int32_t offs = (op & THUMB_BRANCH_OFFS) << 1;
if (offs & 0x00000800)
{
offs |= 0xfffff800;
@@ -1556,8 +1556,8 @@ void arm7_cpu_device::drctg0e_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0e_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 offs = (op & THUMB_BLOP_OFFS) << 1;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t offs = (op & THUMB_BLOP_OFFS) << 1;
UML_MOV(block, uml::I0, DRC_REG(14));
UML_ADD(block, uml::I0, uml::I0, offs);
UML_AND(block, uml::I0, uml::I0, ~3);
@@ -1570,8 +1570,8 @@ void arm7_cpu_device::drctg0e_1(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0f_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
- UINT32 op = desc->opptr.l[0];
- UINT32 addr = (op & THUMB_BLOP_OFFS) << 12;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t addr = (op & THUMB_BLOP_OFFS) << 12;
if (addr & (1 << 22))
{
addr |= 0xff800000;
@@ -1583,8 +1583,8 @@ void arm7_cpu_device::drctg0f_0(drcuml_block *block, compiler_state *compiler, c
void arm7_cpu_device::drctg0f_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) /* BL */
{
- UINT32 op = desc->opptr.l[0];
- UINT32 addr = (op & THUMB_BLOP_OFFS) << 1;
+ uint32_t op = desc->opptr.l[0];
+ uint32_t addr = (op & THUMB_BLOP_OFFS) << 1;
UML_AND(block, uml::I0, DRC_REG(14), ~1);
UML_ADD(block, uml::I0, uml::I0, addr);
UML_ADD(block, DRC_REG(14), DRC_PC, 2);