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Diffstat (limited to 'src/devices/cpu/arm/arm.cpp')
-rw-r--r--src/devices/cpu/arm/arm.cpp192
1 files changed, 96 insertions, 96 deletions
diff --git a/src/devices/cpu/arm/arm.cpp b/src/devices/cpu/arm/arm.cpp
index 31bcfa527dd..b4870ce9f54 100644
--- a/src/devices/cpu/arm/arm.cpp
+++ b/src/devices/cpu/arm/arm.cpp
@@ -96,12 +96,12 @@ static const int sRegisterTable[kNumModes][16] =
#define I_BIT 27
#define F_BIT 26
-#define N_MASK ((UINT32)(1<<N_BIT)) /* Negative flag */
-#define Z_MASK ((UINT32)(1<<Z_BIT)) /* Zero flag */
-#define C_MASK ((UINT32)(1<<C_BIT)) /* Carry flag */
-#define V_MASK ((UINT32)(1<<V_BIT)) /* oVerflow flag */
-#define I_MASK ((UINT32)(1<<I_BIT)) /* Interrupt request disable */
-#define F_MASK ((UINT32)(1<<F_BIT)) /* Fast interrupt request disable */
+#define N_MASK ((uint32_t)(1<<N_BIT)) /* Negative flag */
+#define Z_MASK ((uint32_t)(1<<Z_BIT)) /* Zero flag */
+#define C_MASK ((uint32_t)(1<<C_BIT)) /* Carry flag */
+#define V_MASK ((uint32_t)(1<<V_BIT)) /* oVerflow flag */
+#define I_MASK ((uint32_t)(1<<I_BIT)) /* Interrupt request disable */
+#define F_MASK ((uint32_t)(1<<F_BIT)) /* Fast interrupt request disable */
#define N_IS_SET(pc) ((pc) & N_MASK)
#define Z_IS_SET(pc) ((pc) & Z_MASK)
@@ -117,50 +117,50 @@ static const int sRegisterTable[kNumModes][16] =
#define I_IS_CLEAR(pc) (!I_IS_SET(pc))
#define F_IS_CLEAR(pc) (!F_IS_SET(pc))
-#define PSR_MASK ((UINT32) 0xf0000000u)
-#define IRQ_MASK ((UINT32) 0x0c000000u)
-#define ADDRESS_MASK ((UINT32) 0x03fffffcu)
-#define MODE_MASK ((UINT32) 0x00000003u)
+#define PSR_MASK ((uint32_t) 0xf0000000u)
+#define IRQ_MASK ((uint32_t) 0x0c000000u)
+#define ADDRESS_MASK ((uint32_t) 0x03fffffcu)
+#define MODE_MASK ((uint32_t) 0x00000003u)
#define R15 m_sArmRegister[eR15]
#define MODE (R15&0x03)
-#define SIGN_BIT ((UINT32)(1<<31))
+#define SIGN_BIT ((uint32_t)(1<<31))
#define SIGN_BITS_DIFFER(a,b) (((a)^(b)) >> 31)
/* Deconstructing an instruction */
-#define INSN_COND ((UINT32) 0xf0000000u)
-#define INSN_SDT_L ((UINT32) 0x00100000u)
-#define INSN_SDT_W ((UINT32) 0x00200000u)
-#define INSN_SDT_B ((UINT32) 0x00400000u)
-#define INSN_SDT_U ((UINT32) 0x00800000u)
-#define INSN_SDT_P ((UINT32) 0x01000000u)
-#define INSN_BDT_L ((UINT32) 0x00100000u)
-#define INSN_BDT_W ((UINT32) 0x00200000u)
-#define INSN_BDT_S ((UINT32) 0x00400000u)
-#define INSN_BDT_U ((UINT32) 0x00800000u)
-#define INSN_BDT_P ((UINT32) 0x01000000u)
-#define INSN_BDT_REGS ((UINT32) 0x0000ffffu)
-#define INSN_SDT_IMM ((UINT32) 0x00000fffu)
-#define INSN_MUL_A ((UINT32) 0x00200000u)
-#define INSN_MUL_RM ((UINT32) 0x0000000fu)
-#define INSN_MUL_RS ((UINT32) 0x00000f00u)
-#define INSN_MUL_RN ((UINT32) 0x0000f000u)
-#define INSN_MUL_RD ((UINT32) 0x000f0000u)
-#define INSN_I ((UINT32) 0x02000000u)
-#define INSN_OPCODE ((UINT32) 0x01e00000u)
-#define INSN_S ((UINT32) 0x00100000u)
-#define INSN_BL ((UINT32) 0x01000000u)
-#define INSN_BRANCH ((UINT32) 0x00ffffffu)
-#define INSN_SWI ((UINT32) 0x00ffffffu)
-#define INSN_RN ((UINT32) 0x000f0000u)
-#define INSN_RD ((UINT32) 0x0000f000u)
-#define INSN_OP2 ((UINT32) 0x00000fffu)
-#define INSN_OP2_SHIFT ((UINT32) 0x00000f80u)
-#define INSN_OP2_SHIFT_TYPE ((UINT32) 0x00000070u)
-#define INSN_OP2_RM ((UINT32) 0x0000000fu)
-#define INSN_OP2_ROTATE ((UINT32) 0x00000f00u)
-#define INSN_OP2_IMM ((UINT32) 0x000000ffu)
+#define INSN_COND ((uint32_t) 0xf0000000u)
+#define INSN_SDT_L ((uint32_t) 0x00100000u)
+#define INSN_SDT_W ((uint32_t) 0x00200000u)
+#define INSN_SDT_B ((uint32_t) 0x00400000u)
+#define INSN_SDT_U ((uint32_t) 0x00800000u)
+#define INSN_SDT_P ((uint32_t) 0x01000000u)
+#define INSN_BDT_L ((uint32_t) 0x00100000u)
+#define INSN_BDT_W ((uint32_t) 0x00200000u)
+#define INSN_BDT_S ((uint32_t) 0x00400000u)
+#define INSN_BDT_U ((uint32_t) 0x00800000u)
+#define INSN_BDT_P ((uint32_t) 0x01000000u)
+#define INSN_BDT_REGS ((uint32_t) 0x0000ffffu)
+#define INSN_SDT_IMM ((uint32_t) 0x00000fffu)
+#define INSN_MUL_A ((uint32_t) 0x00200000u)
+#define INSN_MUL_RM ((uint32_t) 0x0000000fu)
+#define INSN_MUL_RS ((uint32_t) 0x00000f00u)
+#define INSN_MUL_RN ((uint32_t) 0x0000f000u)
+#define INSN_MUL_RD ((uint32_t) 0x000f0000u)
+#define INSN_I ((uint32_t) 0x02000000u)
+#define INSN_OPCODE ((uint32_t) 0x01e00000u)
+#define INSN_S ((uint32_t) 0x00100000u)
+#define INSN_BL ((uint32_t) 0x01000000u)
+#define INSN_BRANCH ((uint32_t) 0x00ffffffu)
+#define INSN_SWI ((uint32_t) 0x00ffffffu)
+#define INSN_RN ((uint32_t) 0x000f0000u)
+#define INSN_RD ((uint32_t) 0x0000f000u)
+#define INSN_OP2 ((uint32_t) 0x00000fffu)
+#define INSN_OP2_SHIFT ((uint32_t) 0x00000f80u)
+#define INSN_OP2_SHIFT_TYPE ((uint32_t) 0x00000070u)
+#define INSN_OP2_RM ((uint32_t) 0x0000000fu)
+#define INSN_OP2_ROTATE ((uint32_t) 0x00000f00u)
+#define INSN_OP2_IMM ((uint32_t) 0x000000ffu)
#define INSN_OP2_SHIFT_TYPE_SHIFT 4
#define INSN_OP2_SHIFT_SHIFT 7
#define INSN_OP2_ROTATE_SHIFT 8
@@ -228,7 +228,7 @@ const device_type ARM = &device_creator<arm_cpu_device>;
const device_type ARM_BE = &device_creator<arm_be_cpu_device>;
-arm_cpu_device::arm_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+arm_cpu_device::arm_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: cpu_device(mconfig, ARM, "ARM", tag, owner, clock, "arm", __FILE__)
, m_program_config("program", ENDIANNESS_LITTLE, 32, 26, 0)
, m_endian(ENDIANNESS_LITTLE)
@@ -238,7 +238,7 @@ arm_cpu_device::arm_cpu_device(const machine_config &mconfig, const char *tag, d
}
-arm_cpu_device::arm_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, endianness_t endianness)
+arm_cpu_device::arm_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source, endianness_t endianness)
: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
, m_program_config("program", endianness, 32, 26, 0)
, m_endian(endianness)
@@ -248,28 +248,28 @@ arm_cpu_device::arm_cpu_device(const machine_config &mconfig, device_type type,
}
-arm_be_cpu_device::arm_be_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+arm_be_cpu_device::arm_be_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm_cpu_device(mconfig, ARM_BE, "ARM (big endian)", tag, owner, clock, "arm be", __FILE__, ENDIANNESS_BIG)
{
}
-void arm_cpu_device::cpu_write32( int addr, UINT32 data )
+void arm_cpu_device::cpu_write32( int addr, uint32_t data )
{
/* Unaligned writes are treated as normal writes */
m_program->write_dword(addr&ADDRESS_MASK,data);
if (ARM_DEBUG_CORE && !DWORD_ALIGNED(addr)) logerror("%08x: Unaligned write %08x\n",R15,addr);
}
-void arm_cpu_device::cpu_write8( int addr, UINT8 data )
+void arm_cpu_device::cpu_write8( int addr, uint8_t data )
{
m_program->write_byte(addr,data);
}
-UINT32 arm_cpu_device::cpu_read32( int addr )
+uint32_t arm_cpu_device::cpu_read32( int addr )
{
- UINT32 result = m_program->read_dword(addr&ADDRESS_MASK);
+ uint32_t result = m_program->read_dword(addr&ADDRESS_MASK);
/* Unaligned reads rotate the word, they never combine words */
if (!DWORD_ALIGNED(addr))
@@ -288,27 +288,27 @@ UINT32 arm_cpu_device::cpu_read32( int addr )
return result;
}
-UINT8 arm_cpu_device::cpu_read8( int addr )
+uint8_t arm_cpu_device::cpu_read8( int addr )
{
return m_program->read_byte(addr);
}
-UINT32 arm_cpu_device::GetRegister( int rIndex )
+uint32_t arm_cpu_device::GetRegister( int rIndex )
{
return m_sArmRegister[sRegisterTable[MODE][rIndex]];
}
-void arm_cpu_device::SetRegister( int rIndex, UINT32 value )
+void arm_cpu_device::SetRegister( int rIndex, uint32_t value )
{
m_sArmRegister[sRegisterTable[MODE][rIndex]] = value;
}
-UINT32 arm_cpu_device::GetModeRegister( int mode, int rIndex )
+uint32_t arm_cpu_device::GetModeRegister( int mode, int rIndex )
{
return m_sArmRegister[sRegisterTable[mode][rIndex]];
}
-void arm_cpu_device::SetModeRegister( int mode, int rIndex, UINT32 value )
+void arm_cpu_device::SetModeRegister( int mode, int rIndex, uint32_t value )
{
m_sArmRegister[sRegisterTable[mode][rIndex]] = value;
}
@@ -336,8 +336,8 @@ void arm_cpu_device::device_reset()
void arm_cpu_device::execute_run()
{
- UINT32 pc;
- UINT32 insn;
+ uint32_t pc;
+ uint32_t insn;
do
{
@@ -451,7 +451,7 @@ void arm_cpu_device::execute_run()
void arm_cpu_device::arm_check_irq_state()
{
- UINT32 pc = R15+4; /* save old pc (already incremented in pipeline) */;
+ uint32_t pc = R15+4; /* save old pc (already incremented in pipeline) */;
/* Exception priorities (from ARM6, not specifically ARM2/3):
@@ -575,9 +575,9 @@ void arm_cpu_device::state_string_export(const device_state_entry &entry, std::s
/***************************************************************************/
-void arm_cpu_device::HandleBranch( UINT32 insn )
+void arm_cpu_device::HandleBranch( uint32_t insn )
{
- UINT32 off = (insn & INSN_BRANCH) << 2;
+ uint32_t off = (insn & INSN_BRANCH) << 2;
/* Save PC into LR if this is a branch with link */
if (insn & INSN_BL)
@@ -598,9 +598,9 @@ void arm_cpu_device::HandleBranch( UINT32 insn )
}
-void arm_cpu_device::HandleMemSingle( UINT32 insn )
+void arm_cpu_device::HandleMemSingle( uint32_t insn )
{
- UINT32 rn, rnv, off, rd;
+ uint32_t rn, rnv, off, rd;
/* Fetch the offset */
if (insn & INSN_I)
@@ -669,7 +669,7 @@ void arm_cpu_device::HandleMemSingle( UINT32 insn )
{
if (ARM_DEBUG_CORE && rd == eR15)
logerror("read byte R15 %08x\n", R15);
- SetRegister(rd,(UINT32) cpu_read8(rnv) );
+ SetRegister(rd,(uint32_t) cpu_read8(rnv) );
}
else
{
@@ -705,7 +705,7 @@ void arm_cpu_device::HandleMemSingle( UINT32 insn )
if (ARM_DEBUG_CORE && rd==eR15)
logerror("Wrote R15 in byte mode\n");
- cpu_write8(rnv, (UINT8) GetRegister(rd) & 0xffu);
+ cpu_write8(rnv, (uint8_t) GetRegister(rd) & 0xffu);
}
else
{
@@ -793,10 +793,10 @@ void arm_cpu_device::HandleMemSingle( UINT32 insn )
| (((sc) != 0) << C_BIT)) + 4; \
else R15 += 4;
-void arm_cpu_device::HandleALU( UINT32 insn )
+void arm_cpu_device::HandleALU( uint32_t insn )
{
- UINT32 op2, sc=0, rd, rn, opcode;
- UINT32 by, rdn;
+ uint32_t op2, sc=0, rd, rn, opcode;
+ uint32_t by, rdn;
opcode = (insn & INSN_OPCODE) >> INSN_OPCODE_SHIFT;
m_icount -= S_CYCLE;
@@ -958,9 +958,9 @@ void arm_cpu_device::HandleALU( UINT32 insn )
}
}
-void arm_cpu_device::HandleMul( UINT32 insn)
+void arm_cpu_device::HandleMul( uint32_t insn)
{
- UINT32 r;
+ uint32_t r;
m_icount -= S_CYCLE + I_CYCLE;
/* should be:
@@ -1011,7 +1011,7 @@ void arm_cpu_device::HandleMul( UINT32 insn)
}
-int arm_cpu_device::loadInc(UINT32 pat, UINT32 rbv, UINT32 s)
+int arm_cpu_device::loadInc(uint32_t pat, uint32_t rbv, uint32_t s)
{
int i,result;
@@ -1037,7 +1037,7 @@ int arm_cpu_device::loadInc(UINT32 pat, UINT32 rbv, UINT32 s)
}
-int arm_cpu_device::loadDec(UINT32 pat, UINT32 rbv, UINT32 s, UINT32* deferredR15, int* defer)
+int arm_cpu_device::loadDec(uint32_t pat, uint32_t rbv, uint32_t s, uint32_t* deferredR15, int* defer)
{
int i,result;
@@ -1063,7 +1063,7 @@ int arm_cpu_device::loadDec(UINT32 pat, UINT32 rbv, UINT32 s, UINT32* deferredR1
}
-int arm_cpu_device::storeInc(UINT32 pat, UINT32 rbv)
+int arm_cpu_device::storeInc(uint32_t pat, uint32_t rbv)
{
int i,result;
@@ -1083,7 +1083,7 @@ int arm_cpu_device::storeInc(UINT32 pat, UINT32 rbv)
} /* storeInc */
-int arm_cpu_device::storeDec(UINT32 pat, UINT32 rbv)
+int arm_cpu_device::storeDec(uint32_t pat, uint32_t rbv)
{
int i,result;
@@ -1103,10 +1103,10 @@ int arm_cpu_device::storeDec(UINT32 pat, UINT32 rbv)
} /* storeDec */
-void arm_cpu_device::HandleMemBlock( UINT32 insn )
+void arm_cpu_device::HandleMemBlock( uint32_t insn )
{
- UINT32 rb = (insn & INSN_RN) >> INSN_RN_SHIFT;
- UINT32 rbp = GetRegister(rb);
+ uint32_t rb = (insn & INSN_RN) >> INSN_RN_SHIFT;
+ uint32_t rbp = GetRegister(rb);
int result;
if (ARM_DEBUG_CORE && insn & INSN_BDT_S)
@@ -1154,7 +1154,7 @@ void arm_cpu_device::HandleMemBlock( UINT32 insn )
}
else
{
- UINT32 deferredR15=0;
+ uint32_t deferredR15=0;
int defer=0;
/* Decrementing */
@@ -1242,11 +1242,11 @@ void arm_cpu_device::HandleMemBlock( UINT32 insn )
* shifter carry output will manifest itself as @*carry == 0@ for carry clear
* and @*carry != 0@ for carry set.
*/
-UINT32 arm_cpu_device::decodeShift(UINT32 insn, UINT32 *pCarry)
+uint32_t arm_cpu_device::decodeShift(uint32_t insn, uint32_t *pCarry)
{
- UINT32 k = (insn & INSN_OP2_SHIFT) >> INSN_OP2_SHIFT_SHIFT;
- UINT32 rm = GetRegister( insn & INSN_OP2_RM );
- UINT32 t = (insn & INSN_OP2_SHIFT_TYPE) >> INSN_OP2_SHIFT_TYPE_SHIFT;
+ uint32_t k = (insn & INSN_OP2_SHIFT) >> INSN_OP2_SHIFT_SHIFT;
+ uint32_t rm = GetRegister( insn & INSN_OP2_RM );
+ uint32_t t = (insn & INSN_OP2_SHIFT_TYPE) >> INSN_OP2_SHIFT_TYPE_SHIFT;
if ((insn & INSN_OP2_RM)==0xf)
{
@@ -1332,10 +1332,10 @@ UINT32 arm_cpu_device::decodeShift(UINT32 insn, UINT32 *pCarry)
} /* decodeShift */
-UINT32 arm_cpu_device::BCDToDecimal(UINT32 value)
+uint32_t arm_cpu_device::BCDToDecimal(uint32_t value)
{
- UINT32 accumulator = 0;
- UINT32 multiplier = 1;
+ uint32_t accumulator = 0;
+ uint32_t multiplier = 1;
int i;
for(i = 0; i < 8; i++)
@@ -1350,15 +1350,15 @@ UINT32 arm_cpu_device::BCDToDecimal(UINT32 value)
}
-UINT32 arm_cpu_device::DecimalToBCD(UINT32 value)
+uint32_t arm_cpu_device::DecimalToBCD(uint32_t value)
{
- UINT32 accumulator = 0;
- UINT32 divisor = 10;
+ uint32_t accumulator = 0;
+ uint32_t divisor = 10;
int i;
for(i = 0; i < 8; i++)
{
- UINT32 temp;
+ uint32_t temp;
temp = value % divisor;
value -= temp;
@@ -1372,10 +1372,10 @@ UINT32 arm_cpu_device::DecimalToBCD(UINT32 value)
return accumulator;
}
-void arm_cpu_device::HandleCoProVL86C020( UINT32 insn )
+void arm_cpu_device::HandleCoProVL86C020( uint32_t insn )
{
- UINT32 rn=(insn>>12)&0xf;
- UINT32 crn=(insn>>16)&0xf;
+ uint32_t rn=(insn>>12)&0xf;
+ uint32_t crn=(insn>>16)&0xf;
m_icount -= S_CYCLE;
@@ -1412,10 +1412,10 @@ void arm_cpu_device::HandleCoProVL86C020( UINT32 insn )
}
}
-void arm_cpu_device::HandleCoPro( UINT32 insn )
+void arm_cpu_device::HandleCoPro( uint32_t insn )
{
- UINT32 rn=(insn>>12)&0xf;
- UINT32 crn=(insn>>16)&0xf;
+ uint32_t rn=(insn>>12)&0xf;
+ uint32_t crn=(insn>>16)&0xf;
m_icount -= S_CYCLE;
@@ -1506,14 +1506,14 @@ void arm_cpu_device::HandleCoPro( UINT32 insn )
}
-offs_t arm_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
+offs_t arm_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
{
extern CPU_DISASSEMBLE( arm );
return CPU_DISASSEMBLE_NAME(arm)(this, buffer, pc, oprom, opram, options);
}
-offs_t arm_be_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
+offs_t arm_be_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
{
extern CPU_DISASSEMBLE( arm_be );
return CPU_DISASSEMBLE_NAME(arm_be)(this, buffer, pc, oprom, opram, options);