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path: root/src/devices/bus/snes/sa1.cpp
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Diffstat (limited to 'src/devices/bus/snes/sa1.cpp')
-rw-r--r--src/devices/bus/snes/sa1.cpp87
1 files changed, 43 insertions, 44 deletions
diff --git a/src/devices/bus/snes/sa1.cpp b/src/devices/bus/snes/sa1.cpp
index 487f176fd86..aaf7024ce5f 100644
--- a/src/devices/bus/snes/sa1.cpp
+++ b/src/devices/bus/snes/sa1.cpp
@@ -204,7 +204,7 @@ void sns_sa1_device::recalc_irqs()
// handle this separately to avoid accessing recursively the regs?
-uint8_t sns_sa1_device::var_length_read(uint32_t offset)
+uint8_t sns_sa1_device::var_length_read(address_space &space, uint32_t offset)
{
// handle 0xffea/0xffeb/0xffee/0xffef
if ((offset & 0xffffe0) == 0x00ffe0)
@@ -216,13 +216,13 @@ uint8_t sns_sa1_device::var_length_read(uint32_t offset)
}
if ((offset & 0xc08000) == 0x008000) //$00-3f:8000-ffff
- return read_l(offset & 0x7fffff);
+ return read_l(space, (offset & 0x7fffff));
if ((offset & 0xc08000) == 0x808000) //$80-bf:8000-ffff
- return read_h(offset & 0x7fffff);
+ return read_h(space, (offset & 0x7fffff));
if ((offset & 0xc00000) == 0xc00000) //$c0-ff:0000-ffff
- return read_h(offset & 0x7fffff);
+ return read_h(space, (offset & 0x7fffff));
if ((offset & 0x40e000) == 0x006000) //$00-3f|80-bf:6000-7fff
return read_bwram((m_bwram_snes * 0x2000) + (offset & 0x1fff));
@@ -239,7 +239,7 @@ uint8_t sns_sa1_device::var_length_read(uint32_t offset)
return 0;
}
-void sns_sa1_device::dma_transfer()
+void sns_sa1_device::dma_transfer(address_space &space)
{
// printf("DMA src %08x (%d), dst %08x (%d) cnt %d\n", m_src_addr, m_dma_ctrl & 3, m_dst_addr, m_dma_ctrl & 4, m_dma_cnt);
@@ -260,15 +260,15 @@ void sns_sa1_device::dma_transfer()
case 0: // ROM
if ((dma_src & 0x408000) == 0x008000 && (dma_src & 0x800000) == 0x000000)
{
- data = read_l(dma_src & 0x7fffff);
+ data = read_l(space, (dma_src & 0x7fffff));
}
if ((dma_src & 0x408000) == 0x008000 && (dma_src & 0x800000) == 0x800000)
{
- data = read_h(dma_src & 0x7fffff);
+ data = read_h(space, (dma_src & 0x7fffff));
}
if ((dma_src & 0xc00000) == 0xc00000)
{
- data = read_h(dma_src & 0x7fffff);
+ data = read_h(space, (dma_src & 0x7fffff));
}
break;
@@ -311,17 +311,17 @@ void sns_sa1_device::dma_transfer()
recalc_irqs();
}
-void sns_sa1_device::dma_cctype1_transfer()
+void sns_sa1_device::dma_cctype1_transfer(address_space &space)
{
m_scpu_flags |= SCPU_IRQ_CHARCONV;
recalc_irqs();
}
-void sns_sa1_device::dma_cctype2_transfer()
+void sns_sa1_device::dma_cctype2_transfer(address_space &space)
{
}
-uint8_t sns_sa1_device::read_regs(uint32_t offset)
+uint8_t sns_sa1_device::read_regs(address_space &space, uint32_t offset)
{
uint8_t value = 0xff;
offset &= 0x1ff; // $2200 + offset gives the reg value to compare with docs
@@ -383,8 +383,8 @@ uint8_t sns_sa1_device::read_regs(uint32_t offset)
case 0x10c:
// Var-Length Read Port Low
{
- uint32_t data = (var_length_read(m_vda + 0) << 0) | (var_length_read(m_vda + 1) << 8)
- | (var_length_read(m_vda + 2) << 16);
+ uint32_t data = (var_length_read(space, m_vda + 0) << 0) | (var_length_read(space, m_vda + 1) << 8)
+ | (var_length_read(space, m_vda + 2) << 16);
data >>= m_vbit;
value = (data >> 0) & 0xff;
}
@@ -392,8 +392,8 @@ uint8_t sns_sa1_device::read_regs(uint32_t offset)
case 0x10d:
// Var-Length Read Port High
{
- uint32_t data = (var_length_read(m_vda + 0) << 0) | (var_length_read(m_vda + 1) << 8)
- | (var_length_read(m_vda + 2) << 16);
+ uint32_t data = (var_length_read(space, m_vda + 0) << 0) | (var_length_read(space, m_vda + 1) << 8)
+ | (var_length_read(space, m_vda + 2) << 16);
data >>= m_vbit;
if (m_drm == 1)
@@ -417,7 +417,7 @@ uint8_t sns_sa1_device::read_regs(uint32_t offset)
return value;
}
-void sns_sa1_device::write_regs(uint32_t offset, uint8_t data)
+void sns_sa1_device::write_regs(address_space &space, uint32_t offset, uint8_t data)
{
offset &= 0x1ff; // $2200 + offset gives the reg value to compare with docs
@@ -669,14 +669,14 @@ void sns_sa1_device::write_regs(uint32_t offset, uint8_t data)
{
if (!(m_dma_ctrl & 0x20) && !(m_dma_ctrl & 0x04)) // Normal DMA to IRAM
{
- dma_transfer();
+ dma_transfer(space);
// printf("SA-1: normal DMA to IRAM\n");
}
if (m_dma_ctrl & 0x20 && m_dma_ctrl & 0x10) // CC DMA Type 1
{
// printf("SA-1: CC DMA type 1\n");
- dma_cctype1_transfer();
+ dma_cctype1_transfer(space);
}
}
break;
@@ -688,7 +688,7 @@ void sns_sa1_device::write_regs(uint32_t offset, uint8_t data)
if (!(m_dma_ctrl & 0x20) && m_dma_ctrl & 0x04) // Normal DMA to BWRAM
{
// printf("SA-1: normal DMA to BWRAM\n");
- dma_transfer();
+ dma_transfer(space);
}
}
break;
@@ -729,7 +729,7 @@ void sns_sa1_device::write_regs(uint32_t offset, uint8_t data)
if (m_dma_ctrl & 0x20 && !(m_dma_ctrl & 0x10)) // CC DMA Type 2
{
// printf("SA-1: CC DMA type 2\n");
- dma_cctype2_transfer();
+ dma_cctype2_transfer(space);
}
}
break;
@@ -901,7 +901,7 @@ void sns_sa1_device::write_bwram(uint32_t offset, uint8_t data)
-------------------------------------------------*/
-uint8_t sns_sa1_device::read_l(offs_t offset)
+READ8_MEMBER(sns_sa1_device::read_l)
{
int bank;
@@ -936,7 +936,7 @@ uint8_t sns_sa1_device::read_l(offs_t offset)
return 0; // this should not happen (the driver should only call read_l in the above case)
}
-uint8_t sns_sa1_device::read_h(offs_t offset)
+READ8_MEMBER(sns_sa1_device::read_h)
{
int bank;
@@ -972,20 +972,20 @@ uint8_t sns_sa1_device::read_h(offs_t offset)
return m_rom[rom_bank_map[(m_bank_f_rom * 0x20) + ((offset - 0x700000) / 0x8000)] * 0x8000 + (offset & 0x7fff)];
}
-void sns_sa1_device::write_l(offs_t offset, uint8_t data)
+WRITE8_MEMBER(sns_sa1_device::write_l)
{
}
-void sns_sa1_device::write_h(offs_t offset, uint8_t data)
+WRITE8_MEMBER(sns_sa1_device::write_h)
{
}
-uint8_t sns_sa1_device::chip_read(offs_t offset)
+READ8_MEMBER( sns_sa1_device::chip_read )
{
uint16_t address = offset & 0xffff;
if (offset < 0x400000 && address >= 0x2200 && address < 0x2400)
- return read_regs(address & 0x1ff); // SA-1 Regs
+ return read_regs(space, address & 0x1ff); // SA-1 Regs
if (offset < 0x400000 && address >= 0x3000 && address < 0x3800)
return read_iram(address & 0x7ff); // Internal SA-1 RAM (2K)
@@ -1000,12 +1000,12 @@ uint8_t sns_sa1_device::chip_read(offs_t offset)
}
-void sns_sa1_device::chip_write(offs_t offset, uint8_t data)
+WRITE8_MEMBER( sns_sa1_device::chip_write )
{
uint16_t address = offset & 0xffff;
if (offset < 0x400000 && address >= 0x2200 && address < 0x2400)
- write_regs(address & 0x1ff, data); // SA-1 Regs
+ write_regs(space, address & 0x1ff, data); // SA-1 Regs
if (offset < 0x400000 && address >= 0x3000 && address < 0x3800)
write_iram(address & 0x7ff, data); // Internal SA-1 RAM (2K)
@@ -1026,7 +1026,7 @@ void sns_sa1_device::chip_write(offs_t offset, uint8_t data)
// I/O regs or WRAM, and there are a few additional accesses to IRAM (in [00-3f][0000-07ff])
// and to BWRAM (in [60-6f][0000-ffff], so-called bitmap mode)
-uint8_t sns_sa1_device::sa1_hi_r(offs_t offset)
+READ8_MEMBER( sns_sa1_device::sa1_hi_r )
{
uint16_t address = offset & 0xffff;
@@ -1037,22 +1037,22 @@ uint8_t sns_sa1_device::sa1_hi_r(offs_t offset)
if (address < 0x0800)
return read_iram(offset); // Internal SA-1 RAM (2K)
else if (address >= 0x2200 && address < 0x2400)
- return read_regs(offset & 0x1ff); // SA-1 Regs
+ return read_regs(space, offset & 0x1ff); // SA-1 Regs
else if (address >= 0x3000 && address < 0x3800)
return read_iram(offset); // Internal SA-1 RAM (2K)
}
else if (address < 0x8000)
return read_bwram((m_bwram_sa1 * 0x2000) + (offset & 0x1fff) + (m_bwram_sa1_source * 0x100000)); // SA-1 BWRAM
else
- return read_h(offset); // ROM
+ return read_h(space, offset); // ROM
return 0xff; // maybe open bus? same as the main system one or diff? (currently not accessible from carts anyway...)
}
else
- return read_h(offset); // ROM
+ return read_h(space, offset); // ROM
}
-uint8_t sns_sa1_device::sa1_lo_r(offs_t offset)
+READ8_MEMBER( sns_sa1_device::sa1_lo_r )
{
uint16_t address = offset & 0xffff;
@@ -1063,7 +1063,7 @@ uint8_t sns_sa1_device::sa1_lo_r(offs_t offset)
if (address < 0x0800)
return read_iram(offset); // Internal SA-1 RAM (2K)
else if (address >= 0x2200 && address < 0x2400)
- return read_regs(offset & 0x1ff); // SA-1 Regs
+ return read_regs(space, offset & 0x1ff); // SA-1 Regs
else if (address >= 0x3000 && address < 0x3800)
return read_iram(offset); // Internal SA-1 RAM (2K)
}
@@ -1094,7 +1094,7 @@ uint8_t sns_sa1_device::sa1_lo_r(offs_t offset)
return m_sa1_reset>>8;
}
else
- return read_l(offset); // ROM
+ return read_l(space, offset); // ROM
return 0xff; // maybe open bus? same as the main system one or diff? (currently not accessible from carts anyway...)
}
@@ -1106,7 +1106,7 @@ uint8_t sns_sa1_device::sa1_lo_r(offs_t offset)
return 0xff; // nothing should be mapped here, so maybe open bus?
}
-void sns_sa1_device::sa1_hi_w(offs_t offset, uint8_t data)
+WRITE8_MEMBER( sns_sa1_device::sa1_hi_w )
{
uint16_t address = offset & 0xffff;
if (offset < 0x400000)
@@ -1116,7 +1116,7 @@ void sns_sa1_device::sa1_hi_w(offs_t offset, uint8_t data)
if (address < 0x0800)
write_iram(offset, data); // Internal SA-1 RAM (2K)
else if (address >= 0x2200 && address < 0x2400)
- write_regs(offset & 0x1ff, data); // SA-1 Regs
+ write_regs(space, offset & 0x1ff, data); // SA-1 Regs
else if (address >= 0x3000 && address < 0x3800)
write_iram(offset, data); // Internal SA-1 RAM (2K)
}
@@ -1125,14 +1125,14 @@ void sns_sa1_device::sa1_hi_w(offs_t offset, uint8_t data)
}
}
-void sns_sa1_device::sa1_lo_w(offs_t offset, uint8_t data)
+WRITE8_MEMBER( sns_sa1_device::sa1_lo_w )
{
if (offset >= 0x400000 && offset < 0x500000)
write_bwram(offset & 0xfffff, data); // SA-1 BWRAM (not mirrored above!)
else if (offset >= 0x600000 && offset < 0x700000)
write_bwram((offset & 0xfffff) + 0x100000, data); // SA-1 BWRAM Bitmap mode
else
- sa1_hi_w(offset, data);
+ sa1_hi_w(space, offset, data);
}
void sns_sa1_device::sa1_map(address_map &map)
@@ -1143,8 +1143,7 @@ void sns_sa1_device::sa1_map(address_map &map)
}
-void sns_sa1_device::device_add_mconfig(machine_config &config)
-{
- G65816(config, m_sa1, 10000000);
- m_sa1->set_addrmap(AS_PROGRAM, &sns_sa1_device::sa1_map);
-}
+MACHINE_CONFIG_START(sns_sa1_device::device_add_mconfig)
+ MCFG_DEVICE_ADD("sa1cpu", G65816, 10000000)
+ MCFG_DEVICE_PROGRAM_MAP(sa1_map)
+MACHINE_CONFIG_END