diff options
Diffstat (limited to 'src/devices/bus/megadrive/eeprom.cpp')
-rw-r--r-- | src/devices/bus/megadrive/eeprom.cpp | 37 |
1 files changed, 18 insertions, 19 deletions
diff --git a/src/devices/bus/megadrive/eeprom.cpp b/src/devices/bus/megadrive/eeprom.cpp index e790d7cace8..016a17507eb 100644 --- a/src/devices/bus/megadrive/eeprom.cpp +++ b/src/devices/bus/megadrive/eeprom.cpp @@ -399,11 +399,11 @@ void md_eeprom_nbajam_device_alt::eeprom_i2c_init() m_eeprom_word_address = 0; m_eeprom_devsel = 0; m_eeprom_byte = 0; - + m_eeprom_sda = m_eeprom_prev_sda = 1; m_eeprom_scl = m_eeprom_prev_scl = 1; m_eeprom_cur_state = STATE_I2C_IDLE; - + m_eeprom_mask = 0xff; m_eeprom_pagewrite_mask = 0x03; } @@ -438,17 +438,17 @@ void md_eeprom_nbajam_device_alt::eeprom_i2c_update(void) case STATE_I2C_IDLE: idle_devsel_check(); break; - + case STATE_I2C_WAIT_STOP: if (!m_eeprom_prev_sda && m_eeprom_sda && m_eeprom_scl) m_eeprom_cur_state = STATE_I2C_IDLE; break; - + // device select: there can be up to 8 EEPROM in series, so that we start with writing 3 bits // to identify which device has to be accessed, followed by a Read/Write bit to specify the action case STATE_I2C_DEVSEL: idle_devsel_check(); - + // LOW to HIGH transition of SCL = prepare to transmit, by moving to cnt = 1 if (!m_eeprom_prev_scl && m_eeprom_scl) { @@ -480,11 +480,11 @@ void md_eeprom_nbajam_device_alt::eeprom_i2c_update(void) } } break; - + // read operation = count 8 operations and at 9th check whether ACK has been issued case STATE_I2C_READ_DATA: idle_devsel_check(); - + // HIGH to LOW transition of SCL if (m_eeprom_prev_scl && !m_eeprom_scl) { @@ -493,7 +493,7 @@ void md_eeprom_nbajam_device_alt::eeprom_i2c_update(void) else m_eeprom_cnt = 1; } - + // LOW to HIGH transition of SCL if (!m_eeprom_prev_scl && m_eeprom_scl) { @@ -506,12 +506,12 @@ void md_eeprom_nbajam_device_alt::eeprom_i2c_update(void) } break; - + // For a write operation, the x24c02 requires a second address field. This address field is the // word address, comprised of eight bits, providing access to any one of the 256 words of memory. case STATE_I2C_GET_WORD_ADDR: idle_devsel_check(); - + // HIGH to LOW transition of SCL if (m_eeprom_prev_scl && !m_eeprom_scl) { @@ -526,7 +526,7 @@ void md_eeprom_nbajam_device_alt::eeprom_i2c_update(void) m_eeprom_word_address &= m_eeprom_mask; } } - + // LOW to HIGH transition of SCL if (!m_eeprom_prev_scl && m_eeprom_scl) { @@ -534,11 +534,11 @@ void md_eeprom_nbajam_device_alt::eeprom_i2c_update(void) m_eeprom_word_address = ((m_eeprom_word_address << 1) | m_eeprom_sda) & 0xff; } break; - + // write operation case STATE_I2C_WRITE_DATA: idle_devsel_check(); - + // HIGH to LOW transition of SCL if (m_eeprom_prev_scl && !m_eeprom_scl) { @@ -547,7 +547,7 @@ void md_eeprom_nbajam_device_alt::eeprom_i2c_update(void) else m_eeprom_cnt = 1; } - + // LOW to HIGH transition of SCL if (!m_eeprom_prev_scl && m_eeprom_scl) { @@ -568,7 +568,7 @@ void md_eeprom_nbajam_device_alt::eeprom_i2c_update(void) } break; } - + m_eeprom_prev_scl = m_eeprom_scl; m_eeprom_prev_sda = m_eeprom_sda; //printf("Write line : status %d SDA %x SCL %x (count %d)\n", m_eeprom_cur_state, m_eeprom_sda, m_eeprom_scl, m_eeprom_cnt); @@ -588,7 +588,7 @@ UINT8 md_eeprom_nbajam_device_alt::eeprom_i2c_out() sram_address &= 0xffff; res = (nvram[sram_address] >> (8 - m_eeprom_cnt)) & 1; - + if (m_eeprom_cnt == 8) { //printf("Read EEPROM : status %d addr %x data %x (count 8)\n", m_eeprom_cur_state, sram_address, nvram[sram_address]); @@ -604,11 +604,11 @@ UINT8 md_eeprom_nbajam_device_alt::eeprom_i2c_out() if (m_eeprom_cnt == 9) res = 0; break; - + default: break; } - + //printf("Read line : status %d data %x (count %d)\n", m_eeprom_cur_state, res, m_eeprom_cnt); return res; } @@ -635,4 +635,3 @@ WRITE16_MEMBER(md_eeprom_nbajam_device_alt::write) eeprom_i2c_update(); } } - |