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Diffstat (limited to 'src/devices/bus/isa/3c505.cpp')
-rw-r--r--src/devices/bus/isa/3c505.cpp26
1 files changed, 13 insertions, 13 deletions
diff --git a/src/devices/bus/isa/3c505.cpp b/src/devices/bus/isa/3c505.cpp
index 6dd695165c2..8efc0471ff4 100644
--- a/src/devices/bus/isa/3c505.cpp
+++ b/src/devices/bus/isa/3c505.cpp
@@ -327,19 +327,19 @@ void isa16_3c505_device::map_io(address_map &map)
* A read or write to I/O location 00H will cause an active transition on
* the CA input.
*/
- map(0x0000, 0x0000).lrw8("ca",
- [this]()
- {
- m_net->ca(1);
- m_net->ca(0);
-
- return 0;
- },
- [this](u8 data)
- {
- m_net->ca(1);
- m_net->ca(0);
- });
+ map(0x0000, 0x0000).lrw8(
+ NAME([this]()
+ {
+ m_net->ca(1);
+ m_net->ca(0);
+
+ return 0;
+ }),
+ NAME([this](u8 data)
+ {
+ m_net->ca(1);
+ m_net->ca(0);
+ }));
/*
* A read or write to I/O location 80H will produce a CAS before RAS cycle