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Diffstat (limited to 'src/devices/bus/a2bus/a2eramworks3.cpp')
-rw-r--r--src/devices/bus/a2bus/a2eramworks3.cpp52
1 files changed, 46 insertions, 6 deletions
diff --git a/src/devices/bus/a2bus/a2eramworks3.cpp b/src/devices/bus/a2bus/a2eramworks3.cpp
index fa47c749e61..11dcf3cae68 100644
--- a/src/devices/bus/a2bus/a2eramworks3.cpp
+++ b/src/devices/bus/a2bus/a2eramworks3.cpp
@@ -2,7 +2,7 @@
// copyright-holders:R. Belmont
/*********************************************************************
- a2eramworks3.c
+ a2eramworks3.cpp
Applied Engineering RamWorks III
@@ -23,6 +23,8 @@
//**************************************************************************
DEFINE_DEVICE_TYPE(A2EAUX_RAMWORKS3, a2eaux_ramworks3_device, "a2erwks3", "Applied Engineering RamWorks III")
+DEFINE_DEVICE_TYPE(A2EAUX_FRANKLIN384, a2eaux_franklin384_device, "a2ef384", "Franklin ACE 500 expansion RAM")
+DEFINE_DEVICE_TYPE(A2EAUX_FRANKLIN512, a2eaux_franklin512_device, "a2ef512", "Franklin ACE 2x00 expansion RAM")
//**************************************************************************
// LIVE DEVICE
@@ -40,6 +42,16 @@ a2eaux_ramworks3_device::a2eaux_ramworks3_device(const machine_config &mconfig,
{
}
+a2eaux_franklin384_device::a2eaux_franklin384_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+ a2eaux_ramworks3_device(mconfig, A2EAUX_FRANKLIN384, tag, owner, clock)
+{
+}
+
+a2eaux_franklin512_device::a2eaux_franklin512_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+ a2eaux_ramworks3_device(mconfig, A2EAUX_FRANKLIN512, tag, owner, clock)
+{
+}
+
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
@@ -55,26 +67,31 @@ void a2eaux_ramworks3_device::device_reset()
m_bank = 0;
}
-uint8_t a2eaux_ramworks3_device::read_auxram(uint16_t offset)
+u8 a2eaux_ramworks3_device::read_auxram(uint16_t offset)
{
return m_ram[offset+m_bank];
}
-void a2eaux_ramworks3_device::write_auxram(uint16_t offset, uint8_t data)
+void a2eaux_ramworks3_device::write_auxram(uint16_t offset, u8 data)
{
m_ram[offset+m_bank] = data;
}
-uint8_t *a2eaux_ramworks3_device::get_vram_ptr()
+u8 *a2eaux_ramworks3_device::get_vram_ptr()
{
return &m_ram[0];
}
-uint8_t *a2eaux_ramworks3_device::get_auxbank_ptr()
+u8 *a2eaux_ramworks3_device::get_auxbank_ptr()
{
return &m_ram[m_bank];
}
+u16 a2eaux_ramworks3_device::get_auxbank_mask()
+{
+ return 0xffff;
+}
+
/*
These cards are split into 64k logical banks.
@@ -88,7 +105,7 @@ uint8_t *a2eaux_ramworks3_device::get_auxbank_ptr()
However, the software will recognize and correctly use a configuration in which
all of banks 00-7F are populated for a total of 8 megabytes. So that's what we do.
*/
-void a2eaux_ramworks3_device::write_c07x(uint8_t offset, uint8_t data)
+void a2eaux_ramworks3_device::write_c07x(u8 offset, u8 data)
{
// write to C071/3/5/7?
if ((offset & 0x9) == 1)
@@ -96,3 +113,26 @@ void a2eaux_ramworks3_device::write_c07x(uint8_t offset, uint8_t data)
m_bank = 0x10000 * (data & 0x7f);
}
}
+
+void a2eaux_franklin384_device::write_c07x(u8 offset, u8 data)
+{
+ if ((offset & 0x9) == 1)
+ {
+ // RamWorks/Z-RAM bank order is 0 3 4 7 8 11 12 15
+ // so cut off access above bank 11 to limit to 384K.
+ if (data > 11)
+ {
+ data = 0;
+ }
+ m_bank = 0x10000 * (data & 0xf);
+ }
+}
+
+void a2eaux_franklin512_device::write_c07x(u8 offset, u8 data)
+{
+ if ((offset & 0x9) == 1)
+ {
+ m_bank = 0x10000 * (data & 0x0f);
+ }
+}
+