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Diffstat (limited to 'regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_simple_mode.pld')
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diff --git a/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_simple_mode.pld b/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_simple_mode.pld
new file mode 100644
index 00000000000..acdf5f9e17a
--- /dev/null
+++ b/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_simple_mode.pld
@@ -0,0 +1,81 @@
+Name GAL16V8 Simple Mode Test ;
+PartNo 00 ;
+Date 4/22/2020 ;
+Revision 01 ;
+Designer MAME ;
+Company MAME ;
+Assembly None ;
+Location ;
+Device G16V8A ;
+
+/* Simple Mode Test */
+
+/*
+ NOTE:
+
+ According to the datasheet when in Simple Mode pins 12, 13, 14, 17, 18, 19
+ can be configured as combinatorial output with feedback, but WinCUPL
+ will not allow these pins to be fed back into a different product term.
+
+ I'm assuming WinCUPL is wrong and not the datasheet because the GAL20V8
+ device supports this configuration and WinCUPL will allow it.
+*/
+
+/* Input Pins */
+PIN 1 = [I1] ;
+PIN 2 = [I2] ;
+PIN 3 = [I3] ;
+PIN 4 = [I4] ;
+PIN 5 = [I5] ;
+PIN 6 = [I6] ;
+PIN 7 = [I7] ;
+PIN 8 = [I8] ;
+PIN 9 = [I9] ;
+PIN 11 = [I11] ;
+PIN 13 = [I13] ;
+PIN 14 = [I14] ;
+PIN 17 = [I17] ;
+PIN 19 = [I19] ;
+
+/* Output Pins */
+PINNODE 12 = [O12] ;
+PINNODE 15 = [O15] ;
+PINNODE 16 = [O16] ;
+PINNODE 18 = [O18] ;
+
+/* Logic Equations */
+
+!O12 = I1 & I3 & I5 #
+ I7 & I9 & I11 #
+ I13 & I17 #
+ !I17 #
+ !I8 #
+ !I1 & !I2 & !I3 & !I4 & !I5 & !I7 #
+ I2 & I4 & I6 #
+ I8 & I14 ;
+
+!O15 = !I1 & !I3 & !I5 #
+ !I7 & !I9 & !I11 #
+ !I13 & !I17 #
+ !I2 & !I4 #
+ I4 #
+ !I2 & !I4 & !I6 #
+ !I8 & !I14 #
+ I13 & I17 ;
+
+O16 = !I11 & !I13 & !I14 & I17 #
+ I6 & I7 & I8 & I9 #
+ !I1 & !I2 & !I3 & !I4 & !I5 #
+ !I17 #
+ I11 & I13 & I14 #
+ !I6 & !I7 & !I8 & !I9 #
+ I1 & I2 & I3 & I4 & I5 ;
+
+!O18 = !I1 & !I3 #
+ !I5 & !I7 #
+ !I9 & !I11 #
+ !I13 & I19 #
+ I17 #
+ I2 & I4 & I6 #
+ I8 & I9 #
+ I14;