diff options
Diffstat (limited to 'regtests/jedutil/eqns/PALASM/palce16v8/pal16r6-as-palce16v8.pds')
-rw-r--r-- | regtests/jedutil/eqns/PALASM/palce16v8/pal16r6-as-palce16v8.pds | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal16r6-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal16r6-as-palce16v8.pds new file mode 100644 index 00000000000..0454eba3e30 --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal16r6-as-palce16v8.pds @@ -0,0 +1,119 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL16R6 Test 1 +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL16R6Test1 PALCE16V8 + +SIGNATURE #b0000000000000000000000000000000000000000000000000000000000000000 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 O12 COMBINATORIAL ; +PIN 13 RF13 REGISTERED ; +PIN 14 RF14 REGISTERED ; +PIN 15 RF15 REGISTERED ; +PIN 16 RF16 REGISTERED ; +PIN 17 RF17 REGISTERED ; +PIN 18 RF18 REGISTERED ; +PIN 19 O19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +/O12 = RF13 * RF14 * RF15 * RF16 * RF17 * RF18 + + I2 + + I3 + + I4 + + /O19 + + I6 * O19 + + I7 * /I8 * I9 +O12.TRST = /I5 + +/RF13 = /I6 * RF13 + + O12 * O19 + + /I9 * /RF13 + + /I2 * /I5 + + I2 * /O12 + + /I7 * /I9 + + /I2 * /I8 + + /I3 * I8 * I9 + +/RF14 := I2 + + /RF14 + + I3 + + I7 * /I8 * /RF13 + + /I9 * RF14 + + I6 * I9 * RF13 + + I2 * I4 * /I9 + + /I5 * /I8 + +/RF15 := /I3 + + I4 + + I5 * RF14 * RF16 + + /I7 * I9 + + I3 * /RF14 + + /I4 * /I5 + + I6 * /I9 + + /I8 * /RF16 + +/RF16 := I8 * RF17 + + I3 * I9 + + /I4 * /I9 * /RF15 + + I7 * I8 + + I2 * I3 * I9 * /RF17 + + I2 * I5 + + I3 * /I4 * /I5 * RF15 + + /I6 * /I7 * I9 + +/RF17 := I2 * I9 + + /I2 * I3 * /I8 + + /I4 * /I8 + + /I5 * I6 * /I8 * /RF16 + + RF16 * /RF18 + + I3 * /I8 + + /I4 * /I8 * RF16 + + RF18 + +/RF18 := RF18 + + I8 * I9 + + /I5 * I8 + + I3 * I4 * /RF18 + + I2 * /I3 + + /I5 * /I7 * /O19 + + /I2 * I3 * /I7 + + /I2 * O19 + +/O19 = I4 * /O12 + + I5 * /I6 + + /I5 * I6 + + I8 * I9 * /RF18 + + I2 * /I9 * RF18 + + I3 * I9 + + /I4 * /I7 * /I8 +O19.TRST = O12 * /RF18 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- |