diff options
-rw-r--r-- | src/emu/cpu/i8085/i8085.c | 1739 | ||||
-rw-r--r-- | src/emu/cpu/i8085/i8085.h | 19 | ||||
-rw-r--r-- | src/emu/cpu/i8085/i8085cpu.h | 158 | ||||
-rw-r--r-- | src/mame/audio/redalert.c | 8 | ||||
-rw-r--r-- | src/mame/drivers/dwarfd.c | 6 | ||||
-rw-r--r-- | src/mame/drivers/phoenix.c | 2 | ||||
-rw-r--r-- | src/mame/includes/phoenix.h | 2 | ||||
-rw-r--r-- | src/mame/video/phoenix.c | 2 |
8 files changed, 973 insertions, 963 deletions
diff --git a/src/emu/cpu/i8085/i8085.c b/src/emu/cpu/i8085/i8085.c index 78866843da0..453e59fd46f 100644 --- a/src/emu/cpu/i8085/i8085.c +++ b/src/emu/cpu/i8085/i8085.c @@ -135,7 +135,9 @@ #define I8085_INTR 0xff -typedef struct { +typedef struct _i8085_state i8085_state; +struct _i8085_state +{ int cputype; /* 0 8080, 1 8085A */ PAIR PC,SP,AF,BC,DE,HL,XX; UINT8 HALT; @@ -151,1180 +153,1180 @@ typedef struct { const device_config *device; const address_space *program; const address_space *io; - void (*sod_callback)(int state); - int (*sid_callback)(void); -} i8085_Regs; - -static int i8085_ICount = 0; + i8085_sod_func sod_callback; + i8085_sid_func sid_callback; + int icount; + UINT8 rim_ien; +}; -static i8085_Regs I; static UINT8 ZS[256]; static UINT8 ZSP[256]; -static UINT8 RIM_IEN = 0; //AT: IEN status latch used by the RIM instruction -static UINT8 ROP(void) + +static UINT8 ROP(i8085_state *cpustate) { - I.STATUS = 0xa2; // instruction fetch - return memory_decrypted_read_byte(I.program, I.PC.w.l++); + cpustate->STATUS = 0xa2; // instruction fetch + return memory_decrypted_read_byte(cpustate->program, cpustate->PC.w.l++); } -static UINT8 ARG(void) +static UINT8 ARG(i8085_state *cpustate) { - return memory_raw_read_byte(I.program, I.PC.w.l++); + return memory_raw_read_byte(cpustate->program, cpustate->PC.w.l++); } -static UINT16 ARG16(void) +static UINT16 ARG16(i8085_state *cpustate) { UINT16 w; - w = memory_raw_read_byte(I.program, I.PC.d); - I.PC.w.l++; - w += memory_raw_read_byte(I.program, I.PC.d) << 8; - I.PC.w.l++; + w = memory_raw_read_byte(cpustate->program, cpustate->PC.d); + cpustate->PC.w.l++; + w += memory_raw_read_byte(cpustate->program, cpustate->PC.d) << 8; + cpustate->PC.w.l++; return w; } -static UINT8 RM(UINT32 a) +static UINT8 RM(i8085_state *cpustate, UINT32 a) { - I.STATUS = 0x82; // memory read - return memory_read_byte_8le(I.program, a); + cpustate->STATUS = 0x82; // memory read + return memory_read_byte_8le(cpustate->program, a); } -static void WM(UINT32 a, UINT8 v) +static void WM(i8085_state *cpustate, UINT32 a, UINT8 v) { - I.STATUS = 0x00; // memory write - memory_write_byte_8le(I.program, a, v); + cpustate->STATUS = 0x00; // memory write + memory_write_byte_8le(cpustate->program, a, v); } -INLINE void execute_one(int opcode) +INLINE void execute_one(i8085_state *cpustate, int opcode) { switch (opcode) { - case 0x00: i8085_ICount -= 4; /* NOP */ + case 0x00: cpustate->icount -= 4; /* NOP */ /* no op */ break; - case 0x01: i8085_ICount -= 10; /* LXI B,nnnn */ - I.BC.w.l = ARG16(); + case 0x01: cpustate->icount -= 10; /* LXI B,nnnn */ + cpustate->BC.w.l = ARG16(cpustate); break; - case 0x02: i8085_ICount -= 7; /* STAX B */ - WM(I.BC.d, I.AF.b.h); + case 0x02: cpustate->icount -= 7; /* STAX B */ + WM(cpustate, cpustate->BC.d, cpustate->AF.b.h); break; - case 0x03: i8085_ICount -= (I.cputype) ? 6 : 5; /* INX B */ - I.BC.w.l++; - if( I.cputype ) + case 0x03: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* INX B */ + cpustate->BC.w.l++; + if( cpustate->cputype ) { - if (I.BC.b.l == 0x00) I.AF.b.l |= XF; else I.AF.b.l &= ~XF; + if (cpustate->BC.b.l == 0x00) cpustate->AF.b.l |= XF; else cpustate->AF.b.l &= ~XF; } break; - case 0x04: i8085_ICount -= (I.cputype) ? 4 : 5; /* INR B */ - M_INR(I.BC.b.h); + case 0x04: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* INR B */ + M_INR(cpustate->BC.b.h); break; - case 0x05: i8085_ICount -= (I.cputype) ? 4 : 5; /* DCR B */ - M_DCR(I.BC.b.h); + case 0x05: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* DCR B */ + M_DCR(cpustate->BC.b.h); break; - case 0x06: i8085_ICount -= 7; /* MVI B,nn */ - M_MVI(I.BC.b.h); + case 0x06: cpustate->icount -= 7; /* MVI B,nn */ + M_MVI(cpustate->BC.b.h); break; - case 0x07: i8085_ICount -= 4; /* RLC */ + case 0x07: cpustate->icount -= 4; /* RLC */ M_RLC; break; case 0x08: - if( I.cputype ) { - i8085_ICount -= 10; /* DSUB */ - M_DSUB(); + if( cpustate->cputype ) { + cpustate->icount -= 10; /* DSUB */ + M_DSUB(cpustate); } else { - i8085_ICount -= 4; /* NOP undocumented */ + cpustate->icount -= 4; /* NOP undocumented */ } break; - case 0x09: i8085_ICount -= 10; /* DAD B */ + case 0x09: cpustate->icount -= 10; /* DAD B */ M_DAD(BC); break; - case 0x0a: i8085_ICount -= 7; /* LDAX B */ - I.AF.b.h = RM(I.BC.d); + case 0x0a: cpustate->icount -= 7; /* LDAX B */ + cpustate->AF.b.h = RM(cpustate, cpustate->BC.d); break; - case 0x0b: i8085_ICount -= (I.cputype) ? 6 : 5; /* DCX B */ - I.BC.w.l--; - if( I.cputype ) + case 0x0b: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* DCX B */ + cpustate->BC.w.l--; + if( cpustate->cputype ) { - if (I.BC.b.l == 0xff) I.AF.b.l |= XF; else I.AF.b.l &= ~XF; + if (cpustate->BC.b.l == 0xff) cpustate->AF.b.l |= XF; else cpustate->AF.b.l &= ~XF; } break; - case 0x0c: i8085_ICount -= (I.cputype) ? 4 : 5; /* INR C */ - M_INR(I.BC.b.l); + case 0x0c: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* INR C */ + M_INR(cpustate->BC.b.l); break; - case 0x0d: i8085_ICount -= (I.cputype) ? 4 : 5; /* DCR C */ - M_DCR(I.BC.b.l); + case 0x0d: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* DCR C */ + M_DCR(cpustate->BC.b.l); break; - case 0x0e: i8085_ICount -= 7; /* MVI C,nn */ - M_MVI(I.BC.b.l); + case 0x0e: cpustate->icount -= 7; /* MVI C,nn */ + M_MVI(cpustate->BC.b.l); break; - case 0x0f: i8085_ICount -= 4; /* RRC */ + case 0x0f: cpustate->icount -= 4; /* RRC */ M_RRC; break; case 0x10: - if( I.cputype ) { - i8085_ICount -= 7; /* ASRH */ - I.AF.b.l = (I.AF.b.l & ~CF) | (I.HL.b.l & CF); - I.HL.w.l = (I.HL.w.l >> 1); + if( cpustate->cputype ) { + cpustate->icount -= 7; /* ASRH */ + cpustate->AF.b.l = (cpustate->AF.b.l & ~CF) | (cpustate->HL.b.l & CF); + cpustate->HL.w.l = (cpustate->HL.w.l >> 1); } else { - i8085_ICount -= 4; /* NOP undocumented */ + cpustate->icount -= 4; /* NOP undocumented */ } break; - case 0x11: i8085_ICount -= 10; /* LXI D,nnnn */ - I.DE.w.l = ARG16(); + case 0x11: cpustate->icount -= 10; /* LXI D,nnnn */ + cpustate->DE.w.l = ARG16(cpustate); break; - case 0x12: i8085_ICount -= 7; /* STAX D */ - WM(I.DE.d, I.AF.b.h); + case 0x12: cpustate->icount -= 7; /* STAX D */ + WM(cpustate, cpustate->DE.d, cpustate->AF.b.h); break; - case 0x13: i8085_ICount -= (I.cputype) ? 6 : 5; /* INX D */ - I.DE.w.l++; - if( I.cputype ) + case 0x13: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* INX D */ + cpustate->DE.w.l++; + if( cpustate->cputype ) { - if (I.DE.b.l == 0x00) I.AF.b.l |= XF; else I.AF.b.l &= ~XF; + if (cpustate->DE.b.l == 0x00) cpustate->AF.b.l |= XF; else cpustate->AF.b.l &= ~XF; } break; - case 0x14: i8085_ICount -= (I.cputype) ? 4 : 5; /* INR D */ - M_INR(I.DE.b.h); + case 0x14: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* INR D */ + M_INR(cpustate->DE.b.h); break; - case 0x15: i8085_ICount -= (I.cputype) ? 4 : 5; /* DCR D */ - M_DCR(I.DE.b.h); + case 0x15: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* DCR D */ + M_DCR(cpustate->DE.b.h); break; - case 0x16: i8085_ICount -= 7; /* MVI D,nn */ - M_MVI(I.DE.b.h); + case 0x16: cpustate->icount -= 7; /* MVI D,nn */ + M_MVI(cpustate->DE.b.h); break; - case 0x17: i8085_ICount -= 4; /* RAL */ + case 0x17: cpustate->icount -= 4; /* RAL */ M_RAL; break; case 0x18: - if( I.cputype ) { - i8085_ICount -= 10; /* RLDE */ - I.AF.b.l = (I.AF.b.l & ~(CF | VF)) | (I.DE.b.h >> 7); - I.DE.w.l = (I.DE.w.l << 1) | (I.DE.w.l >> 15); - if (0 != (((I.DE.w.l >> 15) ^ I.AF.b.l) & CF)) - I.AF.b.l |= VF; + if( cpustate->cputype ) { + cpustate->icount -= 10; /* RLDE */ + cpustate->AF.b.l = (cpustate->AF.b.l & ~(CF | VF)) | (cpustate->DE.b.h >> 7); + cpustate->DE.w.l = (cpustate->DE.w.l << 1) | (cpustate->DE.w.l >> 15); + if (0 != (((cpustate->DE.w.l >> 15) ^ cpustate->AF.b.l) & CF)) + cpustate->AF.b.l |= VF; } else { - i8085_ICount -= 4; /* NOP undocumented */ + cpustate->icount -= 4; /* NOP undocumented */ } break; - case 0x19: i8085_ICount -= 10; /* DAD D */ + case 0x19: cpustate->icount -= 10; /* DAD D */ M_DAD(DE); break; - case 0x1a: i8085_ICount -= 7; /* LDAX D */ - I.AF.b.h = RM(I.DE.d); + case 0x1a: cpustate->icount -= 7; /* LDAX D */ + cpustate->AF.b.h = RM(cpustate, cpustate->DE.d); break; - case 0x1b: i8085_ICount -= (I.cputype) ? 6 : 5; /* DCX D */ - I.DE.w.l--; - if( I.cputype ) + case 0x1b: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* DCX D */ + cpustate->DE.w.l--; + if( cpustate->cputype ) { - if (I.DE.b.l == 0xff) I.AF.b.l |= XF; else I.AF.b.l &= ~XF; + if (cpustate->DE.b.l == 0xff) cpustate->AF.b.l |= XF; else cpustate->AF.b.l &= ~XF; } break; - case 0x1c: i8085_ICount -= (I.cputype) ? 4 : 5; /* INR E */ - M_INR(I.DE.b.l); + case 0x1c: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* INR E */ + M_INR(cpustate->DE.b.l); break; - case 0x1d: i8085_ICount -= (I.cputype) ? 4 : 5; /* DCR E */ - M_DCR(I.DE.b.l); + case 0x1d: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* DCR E */ + M_DCR(cpustate->DE.b.l); break; - case 0x1e: i8085_ICount -= 7; /* MVI E,nn */ - M_MVI(I.DE.b.l); + case 0x1e: cpustate->icount -= 7; /* MVI E,nn */ + M_MVI(cpustate->DE.b.l); break; - case 0x1f: i8085_ICount -= 4; /* RAR */ + case 0x1f: cpustate->icount -= 4; /* RAR */ M_RAR; break; case 0x20: - if( I.cputype ) { - i8085_ICount -= 7; /* RIM */ - I.AF.b.h = I.IM; - if (I.sid_callback) - I.AF.b.h = (I.AF.b.h & 0x7f) | ((*I.sid_callback)() ? 0x80 : 0); - I.AF.b.h |= RIM_IEN; RIM_IEN = 0; //AT: read and clear IEN status latch + if( cpustate->cputype ) { + cpustate->icount -= 7; /* RIM */ + cpustate->AF.b.h = cpustate->IM; + if (cpustate->sid_callback) + cpustate->AF.b.h = (cpustate->AF.b.h & 0x7f) | ((*cpustate->sid_callback)(cpustate->device) ? 0x80 : 0); + cpustate->AF.b.h |= cpustate->rim_ien; cpustate->rim_ien = 0; //AT: read and clear IEN status latch } else { - i8085_ICount -= 4; /* NOP undocumented */ + cpustate->icount -= 4; /* NOP undocumented */ } break; - case 0x21: i8085_ICount -= 10; /* LXI H,nnnn */ - I.HL.w.l = ARG16(); + case 0x21: cpustate->icount -= 10; /* LXI H,nnnn */ + cpustate->HL.w.l = ARG16(cpustate); break; - case 0x22: i8085_ICount -= 16; /* SHLD nnnn */ - I.XX.w.l = ARG16(); - WM(I.XX.d, I.HL.b.l); - I.XX.w.l++; - WM(I.XX.d, I.HL.b.h); + case 0x22: cpustate->icount -= 16; /* SHLD nnnn */ + cpustate->XX.w.l = ARG16(cpustate); + WM(cpustate, cpustate->XX.d, cpustate->HL.b.l); + cpustate->XX.w.l++; + WM(cpustate, cpustate->XX.d, cpustate->HL.b.h); break; - case 0x23: i8085_ICount -= (I.cputype) ? 6 : 5; /* INX H */ - I.HL.w.l++; - if( I.cputype ) + case 0x23: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* INX H */ + cpustate->HL.w.l++; + if( cpustate->cputype ) { - if (I.HL.b.l == 0x00) I.AF.b.l |= XF; else I.AF.b.l &= ~XF; + if (cpustate->HL.b.l == 0x00) cpustate->AF.b.l |= XF; else cpustate->AF.b.l &= ~XF; } break; - case 0x24: i8085_ICount -= (I.cputype) ? 4 : 5; /* INR H */ - M_INR(I.HL.b.h); + case 0x24: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* INR H */ + M_INR(cpustate->HL.b.h); break; - case 0x25: i8085_ICount -= (I.cputype) ? 4 : 5; /* DCR H */ - M_DCR(I.HL.b.h); + case 0x25: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* DCR H */ + M_DCR(cpustate->HL.b.h); break; - case 0x26: i8085_ICount -= 7; /* MVI H,nn */ - M_MVI(I.HL.b.h); + case 0x26: cpustate->icount -= 7; /* MVI H,nn */ + M_MVI(cpustate->HL.b.h); break; - case 0x27: i8085_ICount -= 4; /* DAA */ - I.XX.d = I.AF.b.h; - if (I.AF.b.l & CF) I.XX.d |= 0x100; - if (I.AF.b.l & HF) I.XX.d |= 0x200; - if (I.AF.b.l & NF) I.XX.d |= 0x400; - I.AF.w.l = DAA[I.XX.d]; - if( I.cputype==0 ) + case 0x27: cpustate->icount -= 4; /* DAA */ + cpustate->XX.d = cpustate->AF.b.h; + if (cpustate->AF.b.l & CF) cpustate->XX.d |= 0x100; + if (cpustate->AF.b.l & HF) cpustate->XX.d |= 0x200; + if (cpustate->AF.b.l & NF) cpustate->XX.d |= 0x400; + cpustate->AF.w.l = DAA[cpustate->XX.d]; + if( cpustate->cputype==0 ) { - I.AF.b.l &= 0xd5; // Ignore not used flags + cpustate->AF.b.l &= 0xd5; // Ignore not used flags } break; case 0x28: - if( I.cputype ) { - i8085_ICount -= 10; /* LDEH nn */ - I.XX.d = ARG(); - I.DE.d = (I.HL.d + I.XX.d) & 0xffff; + if( cpustate->cputype ) { + cpustate->icount -= 10; /* LDEH nn */ + cpustate->XX.d = ARG(cpustate); + cpustate->DE.d = (cpustate->HL.d + cpustate->XX.d) & 0xffff; } else { - i8085_ICount -= 4; /* NOP undocumented */ + cpustate->icount -= 4; /* NOP undocumented */ } break; - case 0x29: i8085_ICount -= 10; /* DAD H */ + case 0x29: cpustate->icount -= 10; /* DAD H */ M_DAD(HL); break; - case 0x2a: i8085_ICount -= 16; /* LHLD nnnn */ - I.XX.d = ARG16(); - I.HL.b.l = RM(I.XX.d); - I.XX.w.l++; - I.HL.b.h = RM(I.XX.d); + case 0x2a: cpustate->icount -= 16; /* LHLD nnnn */ + cpustate->XX.d = ARG16(cpustate); + cpustate->HL.b.l = RM(cpustate, cpustate->XX.d); + cpustate->XX.w.l++; + cpustate->HL.b.h = RM(cpustate, cpustate->XX.d); break; - case 0x2b: i8085_ICount -= (I.cputype) ? 6 : 5; /* DCX H */ - I.HL.w.l--; - if( I.cputype ) + case 0x2b: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* DCX H */ + cpustate->HL.w.l--; + if( cpustate->cputype ) { - if (I.HL.b.l == 0xff) I.AF.b.l |= XF; else I.AF.b.l &= ~XF; + if (cpustate->HL.b.l == 0xff) cpustate->AF.b.l |= XF; else cpustate->AF.b.l &= ~XF; } break; - case 0x2c: i8085_ICount -= (I.cputype) ? 4 : 5; /* INR L */ - M_INR(I.HL.b.l); + case 0x2c: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* INR L */ + M_INR(cpustate->HL.b.l); break; - case 0x2d: i8085_ICount -= (I.cputype) ? 4 : 5; /* DCR L */ - M_DCR(I.HL.b.l); + case 0x2d: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* DCR L */ + M_DCR(cpustate->HL.b.l); break; - case 0x2e: i8085_ICount -= 7; /* MVI L,nn */ - M_MVI(I.HL.b.l); + case 0x2e: cpustate->icount -= 7; /* MVI L,nn */ + M_MVI(cpustate->HL.b.l); break; - case 0x2f: i8085_ICount -= 4; /* CMA */ - if( I.cputype ) + case 0x2f: cpustate->icount -= 4; /* CMA */ + if( cpustate->cputype ) { - I.AF.b.h ^= 0xff; - I.AF.b.l |= HF + NF; + cpustate->AF.b.h ^= 0xff; + cpustate->AF.b.l |= HF + NF; } else { - I.AF.b.h ^= 0xff; /* 8080 */ + cpustate->AF.b.h ^= 0xff; /* 8080 */ } break; case 0x30: - if( I.cputype ) + if( cpustate->cputype ) { - i8085_ICount -= 7; /* SIM */ + cpustate->icount -= 7; /* SIM */ - if (I.AF.b.h & 0x40) //SOE - only when bit 0x40 is set! + if (cpustate->AF.b.h & 0x40) //SOE - only when bit 0x40 is set! { - I.IM &=~IM_SOD; - if (I.AF.b.h & 0x80) I.IM |= IM_SOD; //is it needed ? - if (I.sod_callback) (*I.sod_callback)(I.AF.b.h >> 7); //SOD - data = bit 0x80 + cpustate->IM &=~IM_SOD; + if (cpustate->AF.b.h & 0x80) cpustate->IM |= IM_SOD; //is it needed ? + if (cpustate->sod_callback) (*cpustate->sod_callback)(cpustate->device, cpustate->AF.b.h >> 7); //SOD - data = bit 0x80 } //AT - //I.IM &= (IM_SID + IM_IEN + IM_TRAP); - //I.IM |= (I.AF.b.h & ~(IM_SID + IM_SOD + IM_IEN + IM_TRAP)); + //cpustate->IM &= (IM_SID + IM_IEN + IM_TRAP); + //cpustate->IM |= (cpustate->AF.b.h & ~(IM_SID + IM_SOD + IM_IEN + IM_TRAP)); // overwrite RST5.5-7.5 interrupt masks only when bit 0x08 of the accumulator is set - if (I.AF.b.h & 0x08) - I.IM = (I.IM & ~(IM_RST55+IM_RST65+IM_RST75)) | (I.AF.b.h & (IM_RST55+IM_RST65+IM_RST75)); + if (cpustate->AF.b.h & 0x08) + cpustate->IM = (cpustate->IM & ~(IM_RST55+IM_RST65+IM_RST75)) | (cpustate->AF.b.h & (IM_RST55+IM_RST65+IM_RST75)); } else { - i8085_ICount -= 4; /* NOP undocumented */ + cpustate->icount -= 4; /* NOP undocumented */ } break; - case 0x31: i8085_ICount -= 10; /* LXI SP,nnnn */ - I.SP.w.l = ARG16(); + case 0x31: cpustate->icount -= 10; /* LXI SP,nnnn */ + cpustate->SP.w.l = ARG16(cpustate); break; - case 0x32: i8085_ICount -= 13; /* STAX nnnn */ - I.XX.d = ARG16(); - WM(I.XX.d, I.AF.b.h); + case 0x32: cpustate->icount -= 13; /* STAX nnnn */ + cpustate->XX.d = ARG16(cpustate); + WM(cpustate, cpustate->XX.d, cpustate->AF.b.h); break; - case 0x33: i8085_ICount -= (I.cputype) ? 6 : 5; /* INX SP */ - I.SP.w.l++; - if( I.cputype ) + case 0x33: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* INX SP */ + cpustate->SP.w.l++; + if( cpustate->cputype ) { - if (I.SP.b.l == 0x00) I.AF.b.l |= XF; else I.AF.b.l &= ~XF; + if (cpustate->SP.b.l == 0x00) cpustate->AF.b.l |= XF; else cpustate->AF.b.l &= ~XF; } break; - case 0x34: i8085_ICount -= 10; /* INR M */ - I.XX.b.l = RM(I.HL.d); - M_INR(I.XX.b.l); - WM(I.HL.d, I.XX.b.l); + case 0x34: cpustate->icount -= 10; /* INR M */ + cpustate->XX.b.l = RM(cpustate, cpustate->HL.d); + M_INR(cpustate->XX.b.l); + WM(cpustate, cpustate->HL.d, cpustate->XX.b.l); break; - case 0x35: i8085_ICount -= 10; /* DCR M */ - I.XX.b.l = RM(I.HL.d); - M_DCR(I.XX.b.l); - WM(I.HL.d, I.XX.b.l); + case 0x35: cpustate->icount -= 10; /* DCR M */ + cpustate->XX.b.l = RM(cpustate, cpustate->HL.d); + M_DCR(cpustate->XX.b.l); + WM(cpustate, cpustate->HL.d, cpustate->XX.b.l); break; - case 0x36: i8085_ICount -= 10; /* MVI M,nn */ - I.XX.b.l = ARG(); - WM(I.HL.d, I.XX.b.l); + case 0x36: cpustate->icount -= 10; /* MVI M,nn */ + cpustate->XX.b.l = ARG(cpustate); + WM(cpustate, cpustate->HL.d, cpustate->XX.b.l); break; - case 0x37: i8085_ICount -= 4; /* STC */ - I.AF.b.l = (I.AF.b.l & 0xfe) | CF; + case 0x37: cpustate->icount -= 4; /* STC */ + cpustate->AF.b.l = (cpustate->AF.b.l & 0xfe) | CF; break; case 0x38: - if( I.cputype ) { - i8085_ICount -= 10; /* LDES nn */ - I.XX.d = ARG(); - I.DE.d = (I.SP.d + I.XX.d) & 0xffff; + if( cpustate->cputype ) { + cpustate->icount -= 10; /* LDES nn */ + cpustate->XX.d = ARG(cpustate); + cpustate->DE.d = (cpustate->SP.d + cpustate->XX.d) & 0xffff; } else { - i8085_ICount -= 4; /* NOP undocumented */ + cpustate->icount -= 4; /* NOP undocumented */ } break; - case 0x39: i8085_ICount -= 10; /* DAD SP */ + case 0x39: cpustate->icount -= 10; /* DAD SP */ M_DAD(SP); break; - case 0x3a: i8085_ICount -= 13; /* LDAX nnnn */ - I.XX.d = ARG16(); - I.AF.b.h = RM(I.XX.d); + case 0x3a: cpustate->icount -= 13; /* LDAX nnnn */ + cpustate->XX.d = ARG16(cpustate); + cpustate->AF.b.h = RM(cpustate, cpustate->XX.d); break; - case 0x3b: i8085_ICount -= (I.cputype) ? 6 : 5; /* DCX SP */ - I.SP.w.l--; - if( I.cputype ) + case 0x3b: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* DCX SP */ + cpustate->SP.w.l--; + if( cpustate->cputype ) { - if (I.SP.b.l == 0xff) I.AF.b.l |= XF; else I.AF.b.l &= ~XF; + if (cpustate->SP.b.l == 0xff) cpustate->AF.b.l |= XF; else cpustate->AF.b.l &= ~XF; } break; - case 0x3c: i8085_ICount -= (I.cputype) ? 4 : 5; /* INR A */ - M_INR(I.AF.b.h); + case 0x3c: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* INR A */ + M_INR(cpustate->AF.b.h); break; - case 0x3d: i8085_ICount -= (I.cputype) ? 4 : 5; /* DCR A */ - M_DCR(I.AF.b.h); + case 0x3d: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* DCR A */ + M_DCR(cpustate->AF.b.h); break; - case 0x3e: i8085_ICount -= 7; /* MVI A,nn */ - M_MVI(I.AF.b.h); + case 0x3e: cpustate->icount -= 7; /* MVI A,nn */ + M_MVI(cpustate->AF.b.h); break; - case 0x3f: i8085_ICount -= 4; /* CMC */ - I.AF.b.l = (I.AF.b.l & 0xfe) | ((I.AF.b.l & CF)==1 ? 0 : 1); + case 0x3f: cpustate->icount -= 4; /* CMC */ + cpustate->AF.b.l = (cpustate->AF.b.l & 0xfe) | ((cpustate->AF.b.l & CF)==1 ? 0 : 1); break; - case 0x40: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV B,B */ + case 0x40: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV B,B */ /* no op */ break; - case 0x41: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV B,C */ - I.BC.b.h = I.BC.b.l; + case 0x41: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV B,C */ + cpustate->BC.b.h = cpustate->BC.b.l; break; - case 0x42: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV B,D */ - I.BC.b.h = I.DE.b.h; + case 0x42: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV B,D */ + cpustate->BC.b.h = cpustate->DE.b.h; break; - case 0x43: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV B,E */ - I.BC.b.h = I.DE.b.l; + case 0x43: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV B,E */ + cpustate->BC.b.h = cpustate->DE.b.l; break; - case 0x44: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV B,H */ - I.BC.b.h = I.HL.b.h; + case 0x44: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV B,H */ + cpustate->BC.b.h = cpustate->HL.b.h; break; - case 0x45: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV B,L */ - I.BC.b.h = I.HL.b.l; + case 0x45: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV B,L */ + cpustate->BC.b.h = cpustate->HL.b.l; break; - case 0x46: i8085_ICount -= 7; /* MOV B,M */ - I.BC.b.h = RM(I.HL.d); + case 0x46: cpustate->icount -= 7; /* MOV B,M */ + cpustate->BC.b.h = RM(cpustate, cpustate->HL.d); break; - case 0x47: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV B,A */ - I.BC.b.h = I.AF.b.h; + case 0x47: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV B,A */ + cpustate->BC.b.h = cpustate->AF.b.h; break; - case 0x48: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV C,B */ - I.BC.b.l = I.BC.b.h; + case 0x48: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV C,B */ + cpustate->BC.b.l = cpustate->BC.b.h; break; - case 0x49: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV C,C */ + case 0x49: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV C,C */ /* no op */ break; - case 0x4a: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV C,D */ - I.BC.b.l = I.DE.b.h; + case 0x4a: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV C,D */ + cpustate->BC.b.l = cpustate->DE.b.h; break; - case 0x4b: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV C,E */ - I.BC.b.l = I.DE.b.l; + case 0x4b: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV C,E */ + cpustate->BC.b.l = cpustate->DE.b.l; break; - case 0x4c: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV C,H */ - I.BC.b.l = I.HL.b.h; + case 0x4c: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV C,H */ + cpustate->BC.b.l = cpustate->HL.b.h; break; - case 0x4d: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV C,L */ - I.BC.b.l = I.HL.b.l; + case 0x4d: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV C,L */ + cpustate->BC.b.l = cpustate->HL.b.l; break; - case 0x4e: i8085_ICount -= 7; /* MOV C,M */ - I.BC.b.l = RM(I.HL.d); + case 0x4e: cpustate->icount -= 7; /* MOV C,M */ + cpustate->BC.b.l = RM(cpustate, cpustate->HL.d); break; - case 0x4f: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV C,A */ - I.BC.b.l = I.AF.b.h; + case 0x4f: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV C,A */ + cpustate->BC.b.l = cpustate->AF.b.h; break; - case 0x50: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV D,B */ - I.DE.b.h = I.BC.b.h; + case 0x50: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV D,B */ + cpustate->DE.b.h = cpustate->BC.b.h; break; - case 0x51: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV D,C */ - I.DE.b.h = I.BC.b.l; + case 0x51: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV D,C */ + cpustate->DE.b.h = cpustate->BC.b.l; break; - case 0x52: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV D,D */ + case 0x52: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV D,D */ /* no op */ break; - case 0x53: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV D,E */ - I.DE.b.h = I.DE.b.l; + case 0x53: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV D,E */ + cpustate->DE.b.h = cpustate->DE.b.l; break; - case 0x54: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV D,H */ - I.DE.b.h = I.HL.b.h; + case 0x54: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV D,H */ + cpustate->DE.b.h = cpustate->HL.b.h; break; - case 0x55: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV D,L */ - I.DE.b.h = I.HL.b.l; + case 0x55: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV D,L */ + cpustate->DE.b.h = cpustate->HL.b.l; break; - case 0x56: i8085_ICount -= 7; /* MOV D,M */ - I.DE.b.h = RM(I.HL.d); + case 0x56: cpustate->icount -= 7; /* MOV D,M */ + cpustate->DE.b.h = RM(cpustate, cpustate->HL.d); break; - case 0x57: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV D,A */ - I.DE.b.h = I.AF.b.h; + case 0x57: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV D,A */ + cpustate->DE.b.h = cpustate->AF.b.h; break; - case 0x58: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV E,B */ - I.DE.b.l = I.BC.b.h; + case 0x58: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV E,B */ + cpustate->DE.b.l = cpustate->BC.b.h; break; - case 0x59: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV E,C */ - I.DE.b.l = I.BC.b.l; + case 0x59: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV E,C */ + cpustate->DE.b.l = cpustate->BC.b.l; break; - case 0x5a: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV E,D */ - I.DE.b.l = I.DE.b.h; + case 0x5a: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV E,D */ + cpustate->DE.b.l = cpustate->DE.b.h; break; - case 0x5b: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV E,E */ + case 0x5b: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV E,E */ /* no op */ break; - case 0x5c: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV E,H */ - I.DE.b.l = I.HL.b.h; + case 0x5c: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV E,H */ + cpustate->DE.b.l = cpustate->HL.b.h; break; - case 0x5d: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV E,L */ - I.DE.b.l = I.HL.b.l; + case 0x5d: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV E,L */ + cpustate->DE.b.l = cpustate->HL.b.l; break; - case 0x5e: i8085_ICount -= 7; /* MOV E,M */ - I.DE.b.l = RM(I.HL.d); + case 0x5e: cpustate->icount -= 7; /* MOV E,M */ + cpustate->DE.b.l = RM(cpustate, cpustate->HL.d); break; - case 0x5f: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV E,A */ - I.DE.b.l = I.AF.b.h; + case 0x5f: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV E,A */ + cpustate->DE.b.l = cpustate->AF.b.h; break; - case 0x60: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV H,B */ - I.HL.b.h = I.BC.b.h; + case 0x60: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV H,B */ + cpustate->HL.b.h = cpustate->BC.b.h; break; - case 0x61: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV H,C */ - I.HL.b.h = I.BC.b.l; + case 0x61: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV H,C */ + cpustate->HL.b.h = cpustate->BC.b.l; break; - case 0x62: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV H,D */ - I.HL.b.h = I.DE.b.h; + case 0x62: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV H,D */ + cpustate->HL.b.h = cpustate->DE.b.h; break; - case 0x63: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV H,E */ - I.HL.b.h = I.DE.b.l; + case 0x63: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV H,E */ + cpustate->HL.b.h = cpustate->DE.b.l; break; - case 0x64: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV H,H */ + case 0x64: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV H,H */ /* no op */ break; - case 0x65: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV H,L */ - I.HL.b.h = I.HL.b.l; + case 0x65: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV H,L */ + cpustate->HL.b.h = cpustate->HL.b.l; break; - case 0x66: i8085_ICount -= 7; /* MOV H,M */ - I.HL.b.h = RM(I.HL.d); + case 0x66: cpustate->icount -= 7; /* MOV H,M */ + cpustate->HL.b.h = RM(cpustate, cpustate->HL.d); break; - case 0x67: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV H,A */ - I.HL.b.h = I.AF.b.h; + case 0x67: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV H,A */ + cpustate->HL.b.h = cpustate->AF.b.h; break; - case 0x68: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV L,B */ - I.HL.b.l = I.BC.b.h; + case 0x68: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV L,B */ + cpustate->HL.b.l = cpustate->BC.b.h; break; - case 0x69: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV L,C */ - I.HL.b.l = I.BC.b.l; + case 0x69: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV L,C */ + cpustate->HL.b.l = cpustate->BC.b.l; break; - case 0x6a: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV L,D */ - I.HL.b.l = I.DE.b.h; + case 0x6a: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV L,D */ + cpustate->HL.b.l = cpustate->DE.b.h; break; - case 0x6b: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV L,E */ - I.HL.b.l = I.DE.b.l; + case 0x6b: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV L,E */ + cpustate->HL.b.l = cpustate->DE.b.l; break; - case 0x6c: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV L,H */ - I.HL.b.l = I.HL.b.h; + case 0x6c: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV L,H */ + cpustate->HL.b.l = cpustate->HL.b.h; break; - case 0x6d: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV L,L */ + case 0x6d: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV L,L */ /* no op */ break; - case 0x6e: i8085_ICount -= 7; /* MOV L,M */ - I.HL.b.l = RM(I.HL.d); + case 0x6e: cpustate->icount -= 7; /* MOV L,M */ + cpustate->HL.b.l = RM(cpustate, cpustate->HL.d); break; - case 0x6f: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV L,A */ - I.HL.b.l = I.AF.b.h; + case 0x6f: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV L,A */ + cpustate->HL.b.l = cpustate->AF.b.h; break; - case 0x70: i8085_ICount -= 7; /* MOV M,B */ - WM(I.HL.d, I.BC.b.h); + case 0x70: cpustate->icount -= 7; /* MOV M,B */ + WM(cpustate, cpustate->HL.d, cpustate->BC.b.h); break; - case 0x71: i8085_ICount -= 7; /* MOV M,C */ - WM(I.HL.d, I.BC.b.l); + case 0x71: cpustate->icount -= 7; /* MOV M,C */ + WM(cpustate, cpustate->HL.d, cpustate->BC.b.l); break; - case 0x72: i8085_ICount -= 7; /* MOV M,D */ - WM(I.HL.d, I.DE.b.h); + case 0x72: cpustate->icount -= 7; /* MOV M,D */ + WM(cpustate, cpustate->HL.d, cpustate->DE.b.h); break; - case 0x73: i8085_ICount -= 7; /* MOV M,E */ - WM(I.HL.d, I.DE.b.l); + case 0x73: cpustate->icount -= 7; /* MOV M,E */ + WM(cpustate, cpustate->HL.d, cpustate->DE.b.l); break; - case 0x74: i8085_ICount -= 7; /* MOV M,H */ - WM(I.HL.d, I.HL.b.h); + case 0x74: cpustate->icount -= 7; /* MOV M,H */ + WM(cpustate, cpustate->HL.d, cpustate->HL.b.h); break; - case 0x75: i8085_ICount -= 7; /* MOV M,L */ - WM(I.HL.d, I.HL.b.l); + case 0x75: cpustate->icount -= 7; /* MOV M,L */ + WM(cpustate, cpustate->HL.d, cpustate->HL.b.l); break; - case 0x76: i8085_ICount -= (I.cputype) ? 5 : 7; /* HLT */ - I.PC.w.l--; - I.HALT = 1; - I.STATUS = 0x8a; // halt acknowledge - if (i8085_ICount > 0) i8085_ICount = 0; + case 0x76: cpustate->icount -= (cpustate->cputype) ? 5 : 7; /* HLT */ + cpustate->PC.w.l--; + cpustate->HALT = 1; + cpustate->STATUS = 0x8a; // halt acknowledge + if (cpustate->icount > 0) cpustate->icount = 0; break; - case 0x77: i8085_ICount -= 7; /* MOV M,A */ - WM(I.HL.d, I.AF.b.h); + case 0x77: cpustate->icount -= 7; /* MOV M,A */ + WM(cpustate, cpustate->HL.d, cpustate->AF.b.h); break; - case 0x78: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV A,B */ - I.AF.b.h = I.BC.b.h; + case 0x78: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV A,B */ + cpustate->AF.b.h = cpustate->BC.b.h; break; - case 0x79: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV A,C */ - I.AF.b.h = I.BC.b.l; + case 0x79: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV A,C */ + cpustate->AF.b.h = cpustate->BC.b.l; break; - case 0x7a: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV A,D */ - I.AF.b.h = I.DE.b.h; + case 0x7a: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV A,D */ + cpustate->AF.b.h = cpustate->DE.b.h; break; - case 0x7b: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV A,E */ - I.AF.b.h = I.DE.b.l; + case 0x7b: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV A,E */ + cpustate->AF.b.h = cpustate->DE.b.l; break; - case 0x7c: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV A,H */ - I.AF.b.h = I.HL.b.h; + case 0x7c: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV A,H */ + cpustate->AF.b.h = cpustate->HL.b.h; break; - case 0x7d: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV A,L */ - I.AF.b.h = I.HL.b.l; + case 0x7d: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV A,L */ + cpustate->AF.b.h = cpustate->HL.b.l; break; - case 0x7e: i8085_ICount -= 7; /* MOV A,M */ - I.AF.b.h = RM(I.HL.d); + case 0x7e: cpustate->icount -= 7; /* MOV A,M */ + cpustate->AF.b.h = RM(cpustate, cpustate->HL.d); break; - case 0x7f: i8085_ICount -= (I.cputype) ? 4 : 5; /* MOV A,A */ + case 0x7f: cpustate->icount -= (cpustate->cputype) ? 4 : 5; /* MOV A,A */ /* no op */ break; - case 0x80: i8085_ICount -= 4; /* ADD B */ - M_ADD(I.BC.b.h); + case 0x80: cpustate->icount -= 4; /* ADD B */ + M_ADD(cpustate->BC.b.h); break; - case 0x81: i8085_ICount -= 4; /* ADD C */ - M_ADD(I.BC.b.l); + case 0x81: cpustate->icount -= 4; /* ADD C */ + M_ADD(cpustate->BC.b.l); break; - case 0x82: i8085_ICount -= 4; /* ADD D */ - M_ADD(I.DE.b.h); + case 0x82: cpustate->icount -= 4; /* ADD D */ + M_ADD(cpustate->DE.b.h); break; - case 0x83: i8085_ICount -= 4; /* ADD E */ - M_ADD(I.DE.b.l); + case 0x83: cpustate->icount -= 4; /* ADD E */ + M_ADD(cpustate->DE.b.l); break; - case 0x84: i8085_ICount -= 4; /* ADD H */ - M_ADD(I.HL.b.h); + case 0x84: cpustate->icount -= 4; /* ADD H */ + M_ADD(cpustate->HL.b.h); break; - case 0x85: i8085_ICount -= 4; /* ADD L */ - M_ADD(I.HL.b.l); + case 0x85: cpustate->icount -= 4; /* ADD L */ + M_ADD(cpustate->HL.b.l); break; - case 0x86: i8085_ICount -= 7; /* ADD M */ - M_ADD(RM(I.HL.d)); + case 0x86: cpustate->icount -= 7; /* ADD M */ + M_ADD(RM(cpustate, cpustate->HL.d)); break; - case 0x87: i8085_ICount -= 4; /* ADD A */ - M_ADD(I.AF.b.h); + case 0x87: cpustate->icount -= 4; /* ADD A */ + M_ADD(cpustate->AF.b.h); break; - case 0x88: i8085_ICount -= 4; /* ADC B */ - M_ADC(I.BC.b.h); + case 0x88: cpustate->icount -= 4; /* ADC B */ + M_ADC(cpustate->BC.b.h); break; - case 0x89: i8085_ICount -= 4; /* ADC C */ - M_ADC(I.BC.b.l); + case 0x89: cpustate->icount -= 4; /* ADC C */ + M_ADC(cpustate->BC.b.l); break; - case 0x8a: i8085_ICount -= 4; /* ADC D */ - M_ADC(I.DE.b.h); + case 0x8a: cpustate->icount -= 4; /* ADC D */ + M_ADC(cpustate->DE.b.h); break; - case 0x8b: i8085_ICount -= 4; /* ADC E */ - M_ADC(I.DE.b.l); + case 0x8b: cpustate->icount -= 4; /* ADC E */ + M_ADC(cpustate->DE.b.l); break; - case 0x8c: i8085_ICount -= 4; /* ADC H */ - M_ADC(I.HL.b.h); + case 0x8c: cpustate->icount -= 4; /* ADC H */ + M_ADC(cpustate->HL.b.h); break; - case 0x8d: i8085_ICount -= 4; /* ADC L */ - M_ADC(I.HL.b.l); + case 0x8d: cpustate->icount -= 4; /* ADC L */ + M_ADC(cpustate->HL.b.l); break; - case 0x8e: i8085_ICount -= 7; /* ADC M */ - M_ADC(RM(I.HL.d)); + case 0x8e: cpustate->icount -= 7; /* ADC M */ + M_ADC(RM(cpustate, cpustate->HL.d)); break; - case 0x8f: i8085_ICount -= 4; /* ADC A */ - M_ADC(I.AF.b.h); + case 0x8f: cpustate->icount -= 4; /* ADC A */ + M_ADC(cpustate->AF.b.h); break; - case 0x90: i8085_ICount -= 4; /* SUB B */ - M_SUB(I.BC.b.h); + case 0x90: cpustate->icount -= 4; /* SUB B */ + M_SUB(cpustate->BC.b.h); break; - case 0x91: i8085_ICount -= 4; /* SUB C */ - M_SUB(I.BC.b.l); + case 0x91: cpustate->icount -= 4; /* SUB C */ + M_SUB(cpustate->BC.b.l); break; - case 0x92: i8085_ICount -= 4; /* SUB D */ - M_SUB(I.DE.b.h); + case 0x92: cpustate->icount -= 4; /* SUB D */ + M_SUB(cpustate->DE.b.h); break; - case 0x93: i8085_ICount -= 4; /* SUB E */ - M_SUB(I.DE.b.l); + case 0x93: cpustate->icount -= 4; /* SUB E */ + M_SUB(cpustate->DE.b.l); break; - case 0x94: i8085_ICount -= 4; /* SUB H */ - M_SUB(I.HL.b.h); + case 0x94: cpustate->icount -= 4; /* SUB H */ + M_SUB(cpustate->HL.b.h); break; - case 0x95: i8085_ICount -= 4; /* SUB L */ - M_SUB(I.HL.b.l); + case 0x95: cpustate->icount -= 4; /* SUB L */ + M_SUB(cpustate->HL.b.l); break; - case 0x96: i8085_ICount -= 7; /* SUB M */ - M_SUB(RM(I.HL.d)); + case 0x96: cpustate->icount -= 7; /* SUB M */ + M_SUB(RM(cpustate, cpustate->HL.d)); break; - case 0x97: i8085_ICount -= 4; /* SUB A */ - M_SUB(I.AF.b.h); + case 0x97: cpustate->icount -= 4; /* SUB A */ + M_SUB(cpustate->AF.b.h); break; - case 0x98: i8085_ICount -= 4; /* SBB B */ - M_SBB(I.BC.b.h); + case 0x98: cpustate->icount -= 4; /* SBB B */ + M_SBB(cpustate->BC.b.h); break; - case 0x99: i8085_ICount -= 4; /* SBB C */ - M_SBB(I.BC.b.l); + case 0x99: cpustate->icount -= 4; /* SBB C */ + M_SBB(cpustate->BC.b.l); break; - case 0x9a: i8085_ICount -= 4; /* SBB D */ - M_SBB(I.DE.b.h); + case 0x9a: cpustate->icount -= 4; /* SBB D */ + M_SBB(cpustate->DE.b.h); break; - case 0x9b: i8085_ICount -= 4; /* SBB E */ - M_SBB(I.DE.b.l); + case 0x9b: cpustate->icount -= 4; /* SBB E */ + M_SBB(cpustate->DE.b.l); break; - case 0x9c: i8085_ICount -= 4; /* SBB H */ - M_SBB(I.HL.b.h); + case 0x9c: cpustate->icount -= 4; /* SBB H */ + M_SBB(cpustate->HL.b.h); break; - case 0x9d: i8085_ICount -= 4; /* SBB L */ - M_SBB(I.HL.b.l); + case 0x9d: cpustate->icount -= 4; /* SBB L */ + M_SBB(cpustate->HL.b.l); break; - case 0x9e: i8085_ICount -= 7; /* SBB M */ - M_SBB(RM(I.HL.d)); + case 0x9e: cpustate->icount -= 7; /* SBB M */ + M_SBB(RM(cpustate, cpustate->HL.d)); break; - case 0x9f: i8085_ICount -= 4; /* SBB A */ - M_SBB(I.AF.b.h); + case 0x9f: cpustate->icount -= 4; /* SBB A */ + M_SBB(cpustate->AF.b.h); break; - case 0xa0: i8085_ICount -= 4; /* ANA B */ - M_ANA(I.BC.b.h); + case 0xa0: cpustate->icount -= 4; /* ANA B */ + M_ANA(cpustate->BC.b.h); break; - case 0xa1: i8085_ICount -= 4; /* ANA C */ - M_ANA(I.BC.b.l); + case 0xa1: cpustate->icount -= 4; /* ANA C */ + M_ANA(cpustate->BC.b.l); break; - case 0xa2: i8085_ICount -= 4; /* ANA D */ - M_ANA(I.DE.b.h); + case 0xa2: cpustate->icount -= 4; /* ANA D */ + M_ANA(cpustate->DE.b.h); break; - case 0xa3: i8085_ICount -= 4; /* ANA E */ - M_ANA(I.DE.b.l); + case 0xa3: cpustate->icount -= 4; /* ANA E */ + M_ANA(cpustate->DE.b.l); break; - case 0xa4: i8085_ICount -= 4; /* ANA H */ - M_ANA(I.HL.b.h); + case 0xa4: cpustate->icount -= 4; /* ANA H */ + M_ANA(cpustate->HL.b.h); break; - case 0xa5: i8085_ICount -= 4; /* ANA L */ - M_ANA(I.HL.b.l); + case 0xa5: cpustate->icount -= 4; /* ANA L */ + M_ANA(cpustate->HL.b.l); break; - case 0xa6: i8085_ICount -= 7; /* ANA M */ - M_ANA(RM(I.HL.d)); + case 0xa6: cpustate->icount -= 7; /* ANA M */ + M_ANA(RM(cpustate, cpustate->HL.d)); break; - case 0xa7: i8085_ICount -= 4; /* ANA A */ - M_ANA(I.AF.b.h); + case 0xa7: cpustate->icount -= 4; /* ANA A */ + M_ANA(cpustate->AF.b.h); break; - case 0xa8: i8085_ICount -= 4; /* XRA B */ - M_XRA(I.BC.b.h); + case 0xa8: cpustate->icount -= 4; /* XRA B */ + M_XRA(cpustate->BC.b.h); break; - case 0xa9: i8085_ICount -= 4; /* XRA C */ - M_XRA(I.BC.b.l); + case 0xa9: cpustate->icount -= 4; /* XRA C */ + M_XRA(cpustate->BC.b.l); break; - case 0xaa: i8085_ICount -= 4; /* XRA D */ - M_XRA(I.DE.b.h); + case 0xaa: cpustate->icount -= 4; /* XRA D */ + M_XRA(cpustate->DE.b.h); break; - case 0xab: i8085_ICount -= 4; /* XRA E */ - M_XRA(I.DE.b.l); + case 0xab: cpustate->icount -= 4; /* XRA E */ + M_XRA(cpustate->DE.b.l); break; - case 0xac: i8085_ICount -= 4; /* XRA H */ - M_XRA(I.HL.b.h); + case 0xac: cpustate->icount -= 4; /* XRA H */ + M_XRA(cpustate->HL.b.h); break; - case 0xad: i8085_ICount -= 4; /* XRA L */ - M_XRA(I.HL.b.l); + case 0xad: cpustate->icount -= 4; /* XRA L */ + M_XRA(cpustate->HL.b.l); break; - case 0xae: i8085_ICount -= 7; /* XRA M */ - M_XRA(RM(I.HL.d)); + case 0xae: cpustate->icount -= 7; /* XRA M */ + M_XRA(RM(cpustate, cpustate->HL.d)); break; - case 0xaf: i8085_ICount -= 4; /* XRA A */ - M_XRA(I.AF.b.h); + case 0xaf: cpustate->icount -= 4; /* XRA A */ + M_XRA(cpustate->AF.b.h); break; - case 0xb0: i8085_ICount -= 4; /* ORA B */ - M_ORA(I.BC.b.h); + case 0xb0: cpustate->icount -= 4; /* ORA B */ + M_ORA(cpustate->BC.b.h); break; - case 0xb1: i8085_ICount -= 4; /* ORA C */ - M_ORA(I.BC.b.l); + case 0xb1: cpustate->icount -= 4; /* ORA C */ + M_ORA(cpustate->BC.b.l); break; - case 0xb2: i8085_ICount -= 4; /* ORA D */ - M_ORA(I.DE.b.h); + case 0xb2: cpustate->icount -= 4; /* ORA D */ + M_ORA(cpustate->DE.b.h); break; - case 0xb3: i8085_ICount -= 4; /* ORA E */ - M_ORA(I.DE.b.l); + case 0xb3: cpustate->icount -= 4; /* ORA E */ + M_ORA(cpustate->DE.b.l); break; - case 0xb4: i8085_ICount -= 4; /* ORA H */ - M_ORA(I.HL.b.h); + case 0xb4: cpustate->icount -= 4; /* ORA H */ + M_ORA(cpustate->HL.b.h); break; - case 0xb5: i8085_ICount -= 4; /* ORA L */ - M_ORA(I.HL.b.l); + case 0xb5: cpustate->icount -= 4; /* ORA L */ + M_ORA(cpustate->HL.b.l); break; - case 0xb6: i8085_ICount -= 7; /* ORA M */ - M_ORA(RM(I.HL.d)); + case 0xb6: cpustate->icount -= 7; /* ORA M */ + M_ORA(RM(cpustate, cpustate->HL.d)); break; - case 0xb7: i8085_ICount -= 4; /* ORA A */ - M_ORA(I.AF.b.h); + case 0xb7: cpustate->icount -= 4; /* ORA A */ + M_ORA(cpustate->AF.b.h); break; - case 0xb8: i8085_ICount -= 4; /* CMP B */ - M_CMP(I.BC.b.h); + case 0xb8: cpustate->icount -= 4; /* CMP B */ + M_CMP(cpustate->BC.b.h); break; - case 0xb9: i8085_ICount -= 4; /* CMP C */ - M_CMP(I.BC.b.l); + case 0xb9: cpustate->icount -= 4; /* CMP C */ + M_CMP(cpustate->BC.b.l); break; - case 0xba: i8085_ICount -= 4; /* CMP D */ - M_CMP(I.DE.b.h); + case 0xba: cpustate->icount -= 4; /* CMP D */ + M_CMP(cpustate->DE.b.h); break; - case 0xbb: i8085_ICount -= 4; /* CMP E */ - M_CMP(I.DE.b.l); + case 0xbb: cpustate->icount -= 4; /* CMP E */ + M_CMP(cpustate->DE.b.l); break; - case 0xbc: i8085_ICount -= 4; /* CMP H */ - M_CMP(I.HL.b.h); + case 0xbc: cpustate->icount -= 4; /* CMP H */ + M_CMP(cpustate->HL.b.h); break; - case 0xbd: i8085_ICount -= 4; /* CMP L */ - M_CMP(I.HL.b.l); + case 0xbd: cpustate->icount -= 4; /* CMP L */ + M_CMP(cpustate->HL.b.l); break; - case 0xbe: i8085_ICount -= 7; /* CMP M */ - M_CMP(RM(I.HL.d)); + case 0xbe: cpustate->icount -= 7; /* CMP M */ + M_CMP(RM(cpustate, cpustate->HL.d)); break; - case 0xbf: i8085_ICount -= 4; /* CMP A */ - M_CMP(I.AF.b.h); + case 0xbf: cpustate->icount -= 4; /* CMP A */ + M_CMP(cpustate->AF.b.h); break; - case 0xc0: i8085_ICount -= (I.cputype) ? 6 : 5; /* RNZ */ - M_RET( !(I.AF.b.l & ZF) ); + case 0xc0: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* RNZ */ + M_RET( !(cpustate->AF.b.l & ZF) ); break; - case 0xc1: i8085_ICount -= 10; /* POP B */ + case 0xc1: cpustate->icount -= 10; /* POP B */ M_POP(BC); break; - case 0xc2: i8085_ICount -= 10; /* JNZ nnnn */ - M_JMP( !(I.AF.b.l & ZF) ); + case 0xc2: cpustate->icount -= 10; /* JNZ nnnn */ + M_JMP( !(cpustate->AF.b.l & ZF) ); break; - case 0xc3: i8085_ICount -= 10; /* JMP nnnn */ + case 0xc3: cpustate->icount -= 10; /* JMP nnnn */ M_JMP(1); break; - case 0xc4: i8085_ICount -= 11; /* CNZ nnnn */ - M_CALL( !(I.AF.b.l & ZF) ); + case 0xc4: cpustate->icount -= 11; /* CNZ nnnn */ + M_CALL( !(cpustate->AF.b.l & ZF) ); break; - case 0xc5: i8085_ICount -= (I.cputype) ? 12 : 11; /* PUSH B */ + case 0xc5: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* PUSH B */ M_PUSH(BC); break; - case 0xc6: i8085_ICount -= 7; /* ADI nn */ - I.XX.b.l = ARG(); - M_ADD(I.XX.b.l); + case 0xc6: cpustate->icount -= 7; /* ADI nn */ + cpustate->XX.b.l = ARG(cpustate); + M_ADD(cpustate->XX.b.l); break; - case 0xc7: i8085_ICount -= (I.cputype) ? 12 : 11; /* RST 0 */ + case 0xc7: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* RST 0 */ M_RST(0); break; - case 0xc8: i8085_ICount -= (I.cputype) ? 6 : 5; /* RZ */ - M_RET( I.AF.b.l & ZF ); + case 0xc8: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* RZ */ + M_RET( cpustate->AF.b.l & ZF ); break; - case 0xc9: i8085_ICount -= 10; /* RET */ + case 0xc9: cpustate->icount -= 10; /* RET */ M_RET(1); break; - case 0xca: i8085_ICount -= 10; /* JZ nnnn */ - M_JMP( I.AF.b.l & ZF ); + case 0xca: cpustate->icount -= 10; /* JZ nnnn */ + M_JMP( cpustate->AF.b.l & ZF ); break; case 0xcb: - if( I.cputype ) { - if (I.AF.b.l & VF) { - i8085_ICount -= 12; + if( cpustate->cputype ) { + if (cpustate->AF.b.l & VF) { + cpustate->icount -= 12; M_RST(8); /* call 0x40 */ } else { - i8085_ICount -= 6; /* RST V */ + cpustate->icount -= 6; /* RST V */ } } else { - i8085_ICount -= 10; /* JMP nnnn undocumented*/ + cpustate->icount -= 10; /* JMP nnnn undocumented*/ M_JMP(1); } break; - case 0xcc: i8085_ICount -= 11; /* CZ nnnn */ - M_CALL( I.AF.b.l & ZF ); + case 0xcc: cpustate->icount -= 11; /* CZ nnnn */ + M_CALL( cpustate->AF.b.l & ZF ); break; - case 0xcd: i8085_ICount -= 17; /* CALL nnnn */ + case 0xcd: cpustate->icount -= 17; /* CALL nnnn */ M_CALL(1); break; - case 0xce: i8085_ICount -= 7; /* ACI nn */ - I.XX.b.l = ARG(); - M_ADC(I.XX.b.l); + case 0xce: cpustate->icount -= 7; /* ACI nn */ + cpustate->XX.b.l = ARG(cpustate); + M_ADC(cpustate->XX.b.l); break; - case 0xcf: i8085_ICount -= (I.cputype) ? 12 : 11; /* RST 1 */ + case 0xcf: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* RST 1 */ M_RST(1); break; - case 0xd0: i8085_ICount -= (I.cputype) ? 6 : 5; /* RNC */ - M_RET( !(I.AF.b.l & CF) ); + case 0xd0: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* RNC */ + M_RET( !(cpustate->AF.b.l & CF) ); break; - case 0xd1: i8085_ICount -= 10; /* POP D */ + case 0xd1: cpustate->icount -= 10; /* POP D */ M_POP(DE); break; - case 0xd2: i8085_ICount -= 10; /* JNC nnnn */ - M_JMP( !(I.AF.b.l & CF) ); + case 0xd2: cpustate->icount -= 10; /* JNC nnnn */ + M_JMP( !(cpustate->AF.b.l & CF) ); break; - case 0xd3: i8085_ICount -= 10; /* OUT nn */ + case 0xd3: cpustate->icount -= 10; /* OUT nn */ M_OUT; break; - case 0xd4: i8085_ICount -= 11; /* CNC nnnn */ - M_CALL( !(I.AF.b.l & CF) ); + case 0xd4: cpustate->icount -= 11; /* CNC nnnn */ + M_CALL( !(cpustate->AF.b.l & CF) ); break; - case 0xd5: i8085_ICount -= (I.cputype) ? 12 : 11; /* PUSH D */ + case 0xd5: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* PUSH D */ M_PUSH(DE); break; - case 0xd6: i8085_ICount -= 7; /* SUI nn */ - I.XX.b.l = ARG(); - M_SUB(I.XX.b.l); + case 0xd6: cpustate->icount -= 7; /* SUI nn */ + cpustate->XX.b.l = ARG(cpustate); + M_SUB(cpustate->XX.b.l); break; - case 0xd7: i8085_ICount -= (I.cputype) ? 12 : 11; /* RST 2 */ + case 0xd7: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* RST 2 */ M_RST(2); break; - case 0xd8: i8085_ICount -= (I.cputype) ? 6 : 5; /* RC */ - M_RET( I.AF.b.l & CF ); + case 0xd8: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* RC */ + M_RET( cpustate->AF.b.l & CF ); break; case 0xd9: - if( I.cputype ) { - i8085_ICount -= 10; /* SHLX */ - I.XX.w.l = I.DE.w.l; - WM(I.XX.d, I.HL.b.l); - I.XX.w.l++; - WM(I.XX.d, I.HL.b.h); + if( cpustate->cputype ) { + cpustate->icount -= 10; /* SHLX */ + cpustate->XX.w.l = cpustate->DE.w.l; + WM(cpustate, cpustate->XX.d, cpustate->HL.b.l); + cpustate->XX.w.l++; + WM(cpustate, cpustate->XX.d, cpustate->HL.b.h); } else { - i8085_ICount -= 10; /* RET undocumented */ + cpustate->icount -= 10; /* RET undocumented */ M_RET(1); } break; - case 0xda: i8085_ICount -= 10; /* JC nnnn */ - M_JMP( I.AF.b.l & CF ); + case 0xda: cpustate->icount -= 10; /* JC nnnn */ + M_JMP( cpustate->AF.b.l & CF ); break; - case 0xdb: i8085_ICount -= 10; /* IN nn */ + case 0xdb: cpustate->icount -= 10; /* IN nn */ M_IN; break; - case 0xdc: i8085_ICount -= 11; /* CC nnnn */ - M_CALL( I.AF.b.l & CF ); + case 0xdc: cpustate->icount -= 11; /* CC nnnn */ + M_CALL( cpustate->AF.b.l & CF ); break; case 0xdd: - if( I.cputype ) { - i8085_ICount -= 7; /* JNX nnnn */ - M_JMP( !(I.AF.b.l & XF) ); + if( cpustate->cputype ) { + cpustate->icount -= 7; /* JNX nnnn */ + M_JMP( !(cpustate->AF.b.l & XF) ); } else { - i8085_ICount -= 17; /* CALL nnnn undocumented */ + cpustate->icount -= 17; /* CALL nnnn undocumented */ M_CALL(1); } break; - case 0xde: i8085_ICount -= 7; /* SBI nn */ - I.XX.b.l = ARG(); - M_SBB(I.XX.b.l); + case 0xde: cpustate->icount -= 7; /* SBI nn */ + cpustate->XX.b.l = ARG(cpustate); + M_SBB(cpustate->XX.b.l); break; - case 0xdf: i8085_ICount -= (I.cputype) ? 12 : 11; /* RST 3 */ + case 0xdf: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* RST 3 */ M_RST(3); break; - case 0xe0: i8085_ICount -= (I.cputype) ? 6 : 5; /* RPO */ - M_RET( !(I.AF.b.l & VF) ); + case 0xe0: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* RPO */ + M_RET( !(cpustate->AF.b.l & VF) ); break; - case 0xe1: i8085_ICount -= 10; /* POP H */ + case 0xe1: cpustate->icount -= 10; /* POP H */ M_POP(HL); break; - case 0xe2: i8085_ICount -= 10; /* JPO nnnn */ - M_JMP( !(I.AF.b.l & VF) ); + case 0xe2: cpustate->icount -= 10; /* JPO nnnn */ + M_JMP( !(cpustate->AF.b.l & VF) ); break; - case 0xe3: i8085_ICount -= (I.cputype) ? 16 : 18; /* XTHL */ + case 0xe3: cpustate->icount -= (cpustate->cputype) ? 16 : 18; /* XTHL */ M_POP(XX); M_PUSH(HL); - I.HL.d = I.XX.d; + cpustate->HL.d = cpustate->XX.d; break; - case 0xe4: i8085_ICount -= 11; /* CPO nnnn */ - M_CALL( !(I.AF.b.l & VF) ); + case 0xe4: cpustate->icount -= 11; /* CPO nnnn */ + M_CALL( !(cpustate->AF.b.l & VF) ); break; - case 0xe5: i8085_ICount -= (I.cputype) ? 12 : 11; /* PUSH H */ + case 0xe5: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* PUSH H */ M_PUSH(HL); break; - case 0xe6: i8085_ICount -= 7; /* ANI nn */ - I.XX.b.l = ARG(); - M_ANA(I.XX.b.l); + case 0xe6: cpustate->icount -= 7; /* ANI nn */ + cpustate->XX.b.l = ARG(cpustate); + M_ANA(cpustate->XX.b.l); break; - case 0xe7: i8085_ICount -= (I.cputype) ? 12 : 11; /* RST 4 */ + case 0xe7: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* RST 4 */ M_RST(4); break; - case 0xe8: i8085_ICount -= (I.cputype) ? 6 : 5; /* RPE */ - M_RET( I.AF.b.l & VF ); + case 0xe8: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* RPE */ + M_RET( cpustate->AF.b.l & VF ); break; - case 0xe9: i8085_ICount -= (I.cputype) ? 6 : 5; /* PCHL */ - I.PC.d = I.HL.w.l; + case 0xe9: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* PCHL */ + cpustate->PC.d = cpustate->HL.w.l; break; - case 0xea: i8085_ICount -= 10; /* JPE nnnn */ - M_JMP( I.AF.b.l & VF ); + case 0xea: cpustate->icount -= 10; /* JPE nnnn */ + M_JMP( cpustate->AF.b.l & VF ); break; - case 0xeb: i8085_ICount -= 5; /* XCHG */ - I.XX.d = I.DE.d; - I.DE.d = I.HL.d; - I.HL.d = I.XX.d; + case 0xeb: cpustate->icount -= 5; /* XCHG */ + cpustate->XX.d = cpustate->DE.d; + cpustate->DE.d = cpustate->HL.d; + cpustate->HL.d = cpustate->XX.d; break; - case 0xec: i8085_ICount -= 11; /* CPE nnnn */ - M_CALL( I.AF.b.l & VF ); + case 0xec: cpustate->icount -= 11; /* CPE nnnn */ + M_CALL( cpustate->AF.b.l & VF ); break; case 0xed: - if( I.cputype ) { - i8085_ICount -= 10; /* LHLX */ - I.XX.w.l = I.DE.w.l; - I.HL.b.l = RM(I.XX.d); - I.XX.w.l++; - I.HL.b.h = RM(I.XX.d); + if( cpustate->cputype ) { + cpustate->icount -= 10; /* LHLX */ + cpustate->XX.w.l = cpustate->DE.w.l; + cpustate->HL.b.l = RM(cpustate, cpustate->XX.d); + cpustate->XX.w.l++; + cpustate->HL.b.h = RM(cpustate, cpustate->XX.d); } else { - i8085_ICount -= 17; /* CALL nnnn undocumented */ + cpustate->icount -= 17; /* CALL nnnn undocumented */ M_CALL(1); } break; - case 0xee: i8085_ICount -= 7; /* XRI nn */ - I.XX.b.l = ARG(); - M_XRA(I.XX.b.l); + case 0xee: cpustate->icount -= 7; /* XRI nn */ + cpustate->XX.b.l = ARG(cpustate); + M_XRA(cpustate->XX.b.l); break; - case 0xef: i8085_ICount -= (I.cputype) ? 12 : 11; /* RST 5 */ + case 0xef: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* RST 5 */ M_RST(5); break; - case 0xf0: i8085_ICount -= (I.cputype) ? 6 : 5; /* RP */ - M_RET( !(I.AF.b.l&SF) ); + case 0xf0: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* RP */ + M_RET( !(cpustate->AF.b.l&SF) ); break; - case 0xf1: i8085_ICount -= 10; /* POP A */ + case 0xf1: cpustate->icount -= 10; /* POP A */ M_POP(AF); break; - case 0xf2: i8085_ICount -= 10; /* JP nnnn */ - M_JMP( !(I.AF.b.l & SF) ); + case 0xf2: cpustate->icount -= 10; /* JP nnnn */ + M_JMP( !(cpustate->AF.b.l & SF) ); break; - case 0xf3: i8085_ICount -= 4; /* DI */ + case 0xf3: cpustate->icount -= 4; /* DI */ /* remove interrupt enable */ - I.IM &= ~IM_IEN; + cpustate->IM &= ~IM_IEN; break; - case 0xf4: i8085_ICount -= 11; /* CP nnnn */ - M_CALL( !(I.AF.b.l & SF) ); + case 0xf4: cpustate->icount -= 11; /* CP nnnn */ + M_CALL( !(cpustate->AF.b.l & SF) ); break; - case 0xf5: i8085_ICount -= (I.cputype) ? 12 : 11; /* PUSH A */ + case 0xf5: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* PUSH A */ M_PUSH(AF); break; - case 0xf6: i8085_ICount -= 7; /* ORI nn */ - I.XX.b.l = ARG(); - M_ORA(I.XX.b.l); + case 0xf6: cpustate->icount -= 7; /* ORI nn */ + cpustate->XX.b.l = ARG(cpustate); + M_ORA(cpustate->XX.b.l); break; - case 0xf7: i8085_ICount -= (I.cputype) ? 12 : 11; /* RST 6 */ + case 0xf7: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* RST 6 */ M_RST(6); break; - case 0xf8: i8085_ICount -= (I.cputype) ? 6 : 5; /* RM */ - M_RET( I.AF.b.l & SF ); + case 0xf8: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* RM */ + M_RET( cpustate->AF.b.l & SF ); break; - case 0xf9: i8085_ICount -= (I.cputype) ? 6 : 5; /* SPHL */ - I.SP.d = I.HL.d; + case 0xf9: cpustate->icount -= (cpustate->cputype) ? 6 : 5; /* SPHL */ + cpustate->SP.d = cpustate->HL.d; break; - case 0xfa: i8085_ICount -= 10; /* JM nnnn */ - M_JMP( I.AF.b.l & SF ); + case 0xfa: cpustate->icount -= 10; /* JM nnnn */ + M_JMP( cpustate->AF.b.l & SF ); break; - case 0xfb: i8085_ICount -= 4; /* EI */ + case 0xfb: cpustate->icount -= 4; /* EI */ /* set interrupt enable */ - I.IM |= IM_IEN; + cpustate->IM |= IM_IEN; /* remove serviced IRQ flag */ - I.IREQ &= ~I.ISRV; + cpustate->IREQ &= ~cpustate->ISRV; /* reset serviced IRQ */ - I.ISRV = 0; - if( I.irq_state[I8085_INTR_LINE] != CLEAR_LINE ) { + cpustate->ISRV = 0; + if( cpustate->irq_state[I8085_INTR_LINE] != CLEAR_LINE ) { LOG(("i8085 EI sets INTR\n")); - I.IREQ |= IM_INTR; - I.INTR = I8085_INTR; + cpustate->IREQ |= IM_INTR; + cpustate->INTR = I8085_INTR; } - if( I.cputype ) { - if( I.irq_state[I8085_RST55_LINE] != CLEAR_LINE ) { + if( cpustate->cputype ) { + if( cpustate->irq_state[I8085_RST55_LINE] != CLEAR_LINE ) { LOG(("i8085 EI sets RST5.5\n")); - I.IREQ |= IM_RST55; + cpustate->IREQ |= IM_RST55; } - if( I.irq_state[I8085_RST65_LINE] != CLEAR_LINE ) { + if( cpustate->irq_state[I8085_RST65_LINE] != CLEAR_LINE ) { LOG(("i8085 EI sets RST6.5\n")); - I.IREQ |= IM_RST65; + cpustate->IREQ |= IM_RST65; } - if( I.irq_state[I8085_RST75_LINE] != CLEAR_LINE ) { + if( cpustate->irq_state[I8085_RST75_LINE] != CLEAR_LINE ) { LOG(("i8085 EI sets RST7.5\n")); - I.IREQ |= IM_RST75; - I.irq_state[I8085_RST75_LINE] = CLEAR_LINE; /* clear latch */ + cpustate->IREQ |= IM_RST75; + cpustate->irq_state[I8085_RST75_LINE] = CLEAR_LINE; /* clear latch */ } /* find highest priority IREQ flag with IM enabled and schedule for execution */ - if( !(I.IM & IM_RST75) && (I.IREQ & IM_RST75) ) { - I.ISRV = IM_RST75; - I.IRQ2 = ADDR_RST75; + if( !(cpustate->IM & IM_RST75) && (cpustate->IREQ & IM_RST75) ) { + cpustate->ISRV = IM_RST75; + cpustate->IRQ2 = ADDR_RST75; } else - if( !(I.IM & IM_RST65) && (I.IREQ & IM_RST65) ) { - I.ISRV = IM_RST65; - I.IRQ2 = ADDR_RST65; - } else if( !(I.IM & IM_RST55) && (I.IREQ & IM_RST55) ) { - I.ISRV = IM_RST55; - I.IRQ2 = ADDR_RST55; - } else if( !(I.IM & IM_INTR) && (I.IREQ & IM_INTR) ) { - I.ISRV = IM_INTR; - I.IRQ2 = I.INTR; + if( !(cpustate->IM & IM_RST65) && (cpustate->IREQ & IM_RST65) ) { + cpustate->ISRV = IM_RST65; + cpustate->IRQ2 = ADDR_RST65; + } else if( !(cpustate->IM & IM_RST55) && (cpustate->IREQ & IM_RST55) ) { + cpustate->ISRV = IM_RST55; + cpustate->IRQ2 = ADDR_RST55; + } else if( !(cpustate->IM & IM_INTR) && (cpustate->IREQ & IM_INTR) ) { + cpustate->ISRV = IM_INTR; + cpustate->IRQ2 = cpustate->INTR; } } else { - if( !(I.IM & IM_INTR) && (I.IREQ & IM_INTR) ) { - I.ISRV = IM_INTR; - I.IRQ2 = I.INTR; + if( !(cpustate->IM & IM_INTR) && (cpustate->IREQ & IM_INTR) ) { + cpustate->ISRV = IM_INTR; + cpustate->IRQ2 = cpustate->INTR; } } break; - case 0xfc: i8085_ICount -= 11; /* CM nnnn */ - M_CALL( I.AF.b.l & SF ); + case 0xfc: cpustate->icount -= 11; /* CM nnnn */ + M_CALL( cpustate->AF.b.l & SF ); break; case 0xfd: - if( I.cputype ) { - i8085_ICount -= 7; /* JX nnnn */ - M_JMP( I.AF.b.l & XF ); + if( cpustate->cputype ) { + cpustate->icount -= 7; /* JX nnnn */ + M_JMP( cpustate->AF.b.l & XF ); } else { - i8085_ICount -= 17; /* CALL nnnn undocumented */ + cpustate->icount -= 17; /* CALL nnnn undocumented */ M_CALL(1); } break; - case 0xfe: i8085_ICount -= 7; /* CPI nn */ - I.XX.b.l = ARG(); - M_CMP(I.XX.b.l); + case 0xfe: cpustate->icount -= 7; /* CPI nn */ + cpustate->XX.b.l = ARG(cpustate); + M_CMP(cpustate->XX.b.l); break; - case 0xff: i8085_ICount -= (I.cputype) ? 12 : 11; /* RST 7 */ + case 0xff: cpustate->icount -= (cpustate->cputype) ? 12 : 11; /* RST 7 */ M_RST(7); break; } } -static void Interrupt(void) +static void Interrupt(i8085_state *cpustate) { - if( I.HALT ) /* if the CPU was halted */ + if( cpustate->HALT ) /* if the CPU was halted */ { - I.PC.w.l++; /* skip HALT instr */ - I.HALT = 0; - I.STATUS = 0x26; // int ack while halt + cpustate->PC.w.l++; /* skip HALT instr */ + cpustate->HALT = 0; + cpustate->STATUS = 0x26; // int ack while halt } else { - I.STATUS = 0x23; // int ack + cpustate->STATUS = 0x23; // int ack } //AT - I.IREQ &= ~I.ISRV; // remove serviced IRQ flag - RIM_IEN = (I.ISRV==IM_TRAP) ? I.IM & IM_IEN : 0; // latch general interrupt enable bit on TRAP or NMI + cpustate->IREQ &= ~cpustate->ISRV; // remove serviced IRQ flag + cpustate->rim_ien = (cpustate->ISRV==IM_TRAP) ? cpustate->IM & IM_IEN : 0; // latch general interrupt enable bit on TRAP or NMI //ZT - //I.IM &= ~IM_IEN; /* remove general interrupt enable bit */ + //cpustate->IM &= ~IM_IEN; /* remove general interrupt enable bit */ - if( I.ISRV == IM_INTR ) + if( cpustate->ISRV == IM_INTR ) { LOG(("Interrupt get INTR vector\n")); - I.IRQ1 = (I.irq_callback)(I.device, 0); + cpustate->IRQ1 = (cpustate->irq_callback)(cpustate->device, 0); } - if( I.cputype ) + if( cpustate->cputype ) { - if( I.ISRV == IM_RST55 ) + if( cpustate->ISRV == IM_RST55 ) { LOG(("Interrupt get RST5.5 vector\n")); - //I.IRQ1 = (I.irq_callback)(I.device, 1); - I.irq_state[I8085_RST55_LINE] = CLEAR_LINE; //AT: processing RST5.5, reset interrupt line + //cpustate->IRQ1 = (cpustate->irq_callback)(cpustate->device, 1); + cpustate->irq_state[I8085_RST55_LINE] = CLEAR_LINE; //AT: processing RST5.5, reset interrupt line } - if( I.ISRV == IM_RST65 ) + if( cpustate->ISRV == IM_RST65 ) { LOG(("Interrupt get RST6.5 vector\n")); - //I.IRQ1 = (I.irq_callback)(I.device, 2); - I.irq_state[I8085_RST65_LINE] = CLEAR_LINE; //AT: processing RST6.5, reset interrupt line + //cpustate->IRQ1 = (cpustate->irq_callback)(cpustate->device, 2); + cpustate->irq_state[I8085_RST65_LINE] = CLEAR_LINE; //AT: processing RST6.5, reset interrupt line } - if( I.ISRV == IM_RST75 ) + if( cpustate->ISRV == IM_RST75 ) { LOG(("Interrupt get RST7.5 vector\n")); - //I.IRQ1 = (I.irq_callback)(I.device, 3); - I.irq_state[I8085_RST75_LINE] = CLEAR_LINE; //AT: processing RST7.5, reset interrupt line + //cpustate->IRQ1 = (cpustate->irq_callback)(cpustate->device, 3); + cpustate->irq_state[I8085_RST75_LINE] = CLEAR_LINE; //AT: processing RST7.5, reset interrupt line } } - switch( I.IRQ1 & 0xff0000 ) + switch( cpustate->IRQ1 & 0xff0000 ) { case 0xcd0000: /* CALL nnnn */ - i8085_ICount -= 7; + cpustate->icount -= 7; M_PUSH(PC); case 0xc30000: /* JMP nnnn */ - i8085_ICount -= 10; - I.PC.d = I.IRQ1 & 0xffff; + cpustate->icount -= 10; + cpustate->PC.d = cpustate->IRQ1 & 0xffff; break; default: - switch( I.ISRV ) + switch( cpustate->ISRV ) { case IM_TRAP: case IM_RST75: case IM_RST65: case IM_RST55: M_PUSH(PC); - if (I.IRQ1 != (1 << I8085_RST75_LINE)) - I.PC.d = I.IRQ1; + if (cpustate->IRQ1 != (1 << I8085_RST75_LINE)) + cpustate->PC.d = cpustate->IRQ1; else - I.PC.d = 0x3c; + cpustate->PC.d = 0x3c; break; default: - LOG(("i8085 take int $%02x\n", I.IRQ1)); - execute_one(I.IRQ1 & 0xff); + LOG(("i8085 take int $%02x\n", cpustate->IRQ1)); + execute_one(cpustate, cpustate->IRQ1 & 0xff); } } - I.ISRV = 0; + cpustate->ISRV = 0; } static CPU_EXECUTE( i8085 ) { - - i8085_ICount = cycles; + i8085_state *cpustate = device->token; + + cpustate->icount = cycles; do { - debugger_instruction_hook(device, I.PC.d); + debugger_instruction_hook(device, cpustate->PC.d); /* interrupts enabled or TRAP pending ? */ - if ( (I.IM & IM_IEN) || (I.IREQ & IM_TRAP) ) + if ( (cpustate->IM & IM_IEN) || (cpustate->IREQ & IM_TRAP) ) { /* copy scheduled to executed interrupt request */ - I.IRQ1 = I.IRQ2; + cpustate->IRQ1 = cpustate->IRQ2; /* reset scheduled interrupt request */ - I.IRQ2 = 0; + cpustate->IRQ2 = 0; /* interrupt now ? */ - if (I.IRQ1) Interrupt(); + if (cpustate->IRQ1) Interrupt(cpustate); } /* here we go... */ - execute_one(ROP()); + execute_one(cpustate, ROP(cpustate)); - } while (i8085_ICount > 0); + } while (cpustate->icount > 0); - return cycles - i8085_ICount; + return cycles - cpustate->icount; } /**************************************************************************** @@ -1358,28 +1360,30 @@ static void init_tables (void) ****************************************************************************/ static CPU_INIT( i8085 ) { + i8085_state *cpustate = device->token; + init_tables(); - I.cputype = 1; - I.irq_callback = irqcallback; - I.device = device; - I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); - I.io = memory_find_address_space(device, ADDRESS_SPACE_IO); - - state_save_register_device_item(device, 0, I.AF.w.l); - state_save_register_device_item(device, 0, I.BC.w.l); - state_save_register_device_item(device, 0, I.DE.w.l); - state_save_register_device_item(device, 0, I.HL.w.l); - state_save_register_device_item(device, 0, I.SP.w.l); - state_save_register_device_item(device, 0, I.PC.w.l); - state_save_register_device_item(device, 0, I.HALT); - state_save_register_device_item(device, 0, I.IM); - state_save_register_device_item(device, 0, I.IREQ); - state_save_register_device_item(device, 0, I.ISRV); - state_save_register_device_item(device, 0, I.INTR); - state_save_register_device_item(device, 0, I.IRQ2); - state_save_register_device_item(device, 0, I.IRQ1); - state_save_register_device_item(device, 0, I.STATUS); - state_save_register_device_item_array(device, 0, I.irq_state); + cpustate->cputype = 1; + cpustate->irq_callback = irqcallback; + cpustate->device = device; + cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO); + + state_save_register_device_item(device, 0, cpustate->AF.w.l); + state_save_register_device_item(device, 0, cpustate->BC.w.l); + state_save_register_device_item(device, 0, cpustate->DE.w.l); + state_save_register_device_item(device, 0, cpustate->HL.w.l); + state_save_register_device_item(device, 0, cpustate->SP.w.l); + state_save_register_device_item(device, 0, cpustate->PC.w.l); + state_save_register_device_item(device, 0, cpustate->HALT); + state_save_register_device_item(device, 0, cpustate->IM); + state_save_register_device_item(device, 0, cpustate->IREQ); + state_save_register_device_item(device, 0, cpustate->ISRV); + state_save_register_device_item(device, 0, cpustate->INTR); + state_save_register_device_item(device, 0, cpustate->IRQ2); + state_save_register_device_item(device, 0, cpustate->IRQ1); + state_save_register_device_item(device, 0, cpustate->STATUS); + state_save_register_device_item_array(device, 0, cpustate->irq_state); } /**************************************************************************** @@ -1387,24 +1391,25 @@ static CPU_INIT( i8085 ) ****************************************************************************/ static CPU_RESET( i8085 ) { + i8085_state *cpustate = device->token; cpu_irq_callback save_irqcallback; - void (*save_sodcallback)(int); - int (*save_sidcallback)(void); - int cputype_bak = I.cputype; + i8085_sod_func save_sodcallback; + i8085_sid_func save_sidcallback; + int cputype_bak = cpustate->cputype; init_tables(); - save_irqcallback = I.irq_callback; - save_sodcallback = I.sod_callback; - save_sidcallback = I.sid_callback; - memset(&I, 0, sizeof(i8085_Regs)); - I.irq_callback = save_irqcallback; - I.sod_callback = save_sodcallback; - I.sid_callback = save_sidcallback; - I.device = device; - I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); - I.io = memory_find_address_space(device, ADDRESS_SPACE_IO); - - I.cputype = cputype_bak; + save_irqcallback = cpustate->irq_callback; + save_sodcallback = cpustate->sod_callback; + save_sidcallback = cpustate->sid_callback; + memset(cpustate, 0, sizeof(*cpustate)); + cpustate->irq_callback = save_irqcallback; + cpustate->sod_callback = save_sodcallback; + cpustate->sid_callback = save_sidcallback; + cpustate->device = device; + cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO); + + cpustate->cputype = cputype_bak; } /**************************************************************************** @@ -1415,61 +1420,41 @@ static CPU_EXIT( i8085 ) /* nothing to do */ } -/**************************************************************************** - * Get the current 8085 context - ****************************************************************************/ -static CPU_GET_CONTEXT( i8085 ) -{ - if( dst ) - *(i8085_Regs*)dst = I; -} - -/**************************************************************************** - * Set the current 8085 context - ****************************************************************************/ -static CPU_SET_CONTEXT( i8085 ) -{ - if( src ) - { - I = *(i8085_Regs*)src; - } -} - /****************************************************************************/ /* Set TRAP signal state */ /****************************************************************************/ -static void i8085_set_TRAP(int state) +static void i8085_set_TRAP(i8085_state *cpustate, int state) { LOG(("i8085: TRAP %d\n", state)); if (state) { - I.IREQ |= IM_TRAP; - if( I.ISRV & IM_TRAP ) return; /* already servicing TRAP ? */ - I.ISRV = IM_TRAP; /* service TRAP */ - I.IRQ2 = ADDR_TRAP; + cpustate->IREQ |= IM_TRAP; + if( cpustate->ISRV & IM_TRAP ) return; /* already servicing TRAP ? */ + cpustate->ISRV = IM_TRAP; /* service TRAP */ + cpustate->IRQ2 = ADDR_TRAP; } else { - I.IREQ &= ~IM_TRAP; /* remove request for TRAP */ + cpustate->IREQ &= ~IM_TRAP; /* remove request for TRAP */ } } /****************************************************************************/ /* Set RST7.5 signal state */ /****************************************************************************/ -static void i8085_set_RST75(int state) +static void i8085_set_RST75(i8085_state *cpustate, int state) { LOG(("i8085: RST7.5 %d\n", state)); if( state ) { - I.IREQ |= IM_RST75; /* request RST7.5 */ - I.irq_state[I8085_RST75_LINE] = CLEAR_LINE; /* clear latch */ - if( I.IM & IM_RST75 ) return; /* if masked, ignore it for now */ - if( !I.ISRV ) /* if no higher priority IREQ is serviced */ + cpustate->IREQ |= IM_RST75; /* request RST7.5 */ + cpustate->irq_state[I8085_RST75_LINE] = CLEAR_LINE; /* clear latch */ + if( cpustate->IM & IM_RST75 ) return; /* if masked, ignore it for now */ + if( !cpustate->ISRV ) /* if no higher priority IREQ is serviced */ { - I.ISRV = IM_RST75; /* service RST7.5 */ - I.IRQ2 = ADDR_RST75; + cpustate->ISRV = IM_RST75; /* service RST7.5 */ + cpustate->IRQ2 = ADDR_RST75; } } /* RST7.5 is reset only by SIM or end of service routine ! */ @@ -1478,111 +1463,111 @@ static void i8085_set_RST75(int state) /****************************************************************************/ /* Set RST6.5 signal state */ /****************************************************************************/ -static void i8085_set_RST65(int state) +static void i8085_set_RST65(i8085_state *cpustate, int state) { LOG(("i8085: RST6.5 %d\n", state)); if( state ) { - I.IREQ |= IM_RST65; /* request RST6.5 */ - if( I.IM & IM_RST65 ) return; /* if masked, ignore it for now */ - if( !I.ISRV ) /* if no higher priority IREQ is serviced */ + cpustate->IREQ |= IM_RST65; /* request RST6.5 */ + if( cpustate->IM & IM_RST65 ) return; /* if masked, ignore it for now */ + if( !cpustate->ISRV ) /* if no higher priority IREQ is serviced */ { - I.ISRV = IM_RST65; /* service RST6.5 */ - I.IRQ2 = ADDR_RST65; + cpustate->ISRV = IM_RST65; /* service RST6.5 */ + cpustate->IRQ2 = ADDR_RST65; } } else { - I.IREQ &= ~IM_RST65; /* remove request for RST6.5 */ + cpustate->IREQ &= ~IM_RST65; /* remove request for RST6.5 */ } } /****************************************************************************/ /* Set RST5.5 signal state */ /****************************************************************************/ -static void i8085_set_RST55(int state) +static void i8085_set_RST55(i8085_state *cpustate, int state) { LOG(("i8085: RST5.5 %d\n", state)); if( state ) { - I.IREQ |= IM_RST55; /* request RST5.5 */ - if( I.IM & IM_RST55 ) return; /* if masked, ignore it for now */ - if( !I.ISRV ) /* if no higher priority IREQ is serviced */ + cpustate->IREQ |= IM_RST55; /* request RST5.5 */ + if( cpustate->IM & IM_RST55 ) return; /* if masked, ignore it for now */ + if( !cpustate->ISRV ) /* if no higher priority IREQ is serviced */ { - I.ISRV = IM_RST55; /* service RST5.5 */ - I.IRQ2 = ADDR_RST55; + cpustate->ISRV = IM_RST55; /* service RST5.5 */ + cpustate->IRQ2 = ADDR_RST55; } } else { - I.IREQ &= ~IM_RST55; /* remove request for RST5.5 */ + cpustate->IREQ &= ~IM_RST55; /* remove request for RST5.5 */ } } /****************************************************************************/ /* Set INTR signal */ /****************************************************************************/ -static void i8085_set_INTR(int state) +static void i8085_set_INTR(i8085_state *cpustate, int state) { LOG(("i8085: INTR %d\n", state)); if( state ) { - I.IREQ |= IM_INTR; /* request INTR */ - //I.INTR = state; - I.INTR = I8085_INTR; //AT: I.INTR is supposed to hold IRQ0 vector(0x38) (0xff in this implementation) - if( I.IM & IM_INTR ) return; /* if masked, ignore it for now */ - if( !I.ISRV ) /* if no higher priority IREQ is serviced */ + cpustate->IREQ |= IM_INTR; /* request INTR */ + //cpustate->INTR = state; + cpustate->INTR = I8085_INTR; //AT: cpustate->INTR is supposed to hold IRQ0 vector(0x38) (0xff in this implementation) + if( cpustate->IM & IM_INTR ) return; /* if masked, ignore it for now */ + if( !cpustate->ISRV ) /* if no higher priority IREQ is serviced */ { - I.ISRV = IM_INTR; /* service INTR */ - I.IRQ2 = I.INTR; + cpustate->ISRV = IM_INTR; /* service INTR */ + cpustate->IRQ2 = cpustate->INTR; } } else { - I.IREQ &= ~IM_INTR; /* remove request for INTR */ + cpustate->IREQ &= ~IM_INTR; /* remove request for INTR */ } } -static void i8085_set_irq_line(int irqline, int state) +static void i8085_set_irq_line(i8085_state *cpustate, int irqline, int state) { if (irqline == INPUT_LINE_NMI) { if( state != CLEAR_LINE ) - i8085_set_TRAP(1); + i8085_set_TRAP(cpustate, 1); } else if (irqline < 4) { if (irqline == I8085_RST75_LINE) /* RST7.5 is latched on rising edge, the others are sampled */ { if( state != CLEAR_LINE ) - I.irq_state[irqline] = state; + cpustate->irq_state[irqline] = state; } else - I.irq_state[irqline] = state; + cpustate->irq_state[irqline] = state; if (state == CLEAR_LINE) { - if( !(I.IM & IM_IEN) ) + if( !(cpustate->IM & IM_IEN) ) { switch (irqline) { - case I8085_INTR_LINE: i8085_set_INTR(0); break; - case I8085_RST55_LINE: i8085_set_RST55(0); break; - case I8085_RST65_LINE: i8085_set_RST65(0); break; - case I8085_RST75_LINE: i8085_set_RST75(0); break; + case I8085_INTR_LINE: i8085_set_INTR(cpustate, 0); break; + case I8085_RST55_LINE: i8085_set_RST55(cpustate, 0); break; + case I8085_RST65_LINE: i8085_set_RST65(cpustate, 0); break; + case I8085_RST75_LINE: i8085_set_RST75(cpustate, 0); break; } } } else { - if( I.IM & IM_IEN ) + if( cpustate->IM & IM_IEN ) { switch( irqline ) { - case I8085_INTR_LINE: i8085_set_INTR(1); break; - case I8085_RST55_LINE: i8085_set_RST55(1); break; - case I8085_RST65_LINE: i8085_set_RST65(1); break; - case I8085_RST75_LINE: i8085_set_RST75(1); break; + case I8085_INTR_LINE: i8085_set_INTR(cpustate, 1); break; + case I8085_RST55_LINE: i8085_set_RST55(cpustate, 1); break; + case I8085_RST65_LINE: i8085_set_RST65(cpustate, 1); break; + case I8085_RST75_LINE: i8085_set_RST75(cpustate, 1); break; } } } @@ -1597,47 +1582,49 @@ static void i8085_set_irq_line(int irqline, int state) static CPU_INIT( i8080 ) { + i8085_state *cpustate = device->token; + init_tables(); - I.cputype = 0; - I.irq_callback = irqcallback; - I.device = device; - - state_save_register_device_item(device, 0, I.AF.w.l); - state_save_register_device_item(device, 0, I.BC.w.l); - state_save_register_device_item(device, 0, I.DE.w.l); - state_save_register_device_item(device, 0, I.HL.w.l); - state_save_register_device_item(device, 0, I.SP.w.l); - state_save_register_device_item(device, 0, I.PC.w.l); - state_save_register_device_item(device, 0, I.HALT); - state_save_register_device_item(device, 0, I.IM); - state_save_register_device_item(device, 0, I.IREQ); - state_save_register_device_item(device, 0, I.ISRV); - state_save_register_device_item(device, 0, I.INTR); - state_save_register_device_item(device, 0, I.IRQ2); - state_save_register_device_item(device, 0, I.IRQ1); - state_save_register_device_item(device, 0, I.STATUS); - state_save_register_device_item_array(device, 0, I.irq_state); + cpustate->cputype = 0; + cpustate->irq_callback = irqcallback; + cpustate->device = device; + + state_save_register_device_item(device, 0, cpustate->AF.w.l); + state_save_register_device_item(device, 0, cpustate->BC.w.l); + state_save_register_device_item(device, 0, cpustate->DE.w.l); + state_save_register_device_item(device, 0, cpustate->HL.w.l); + state_save_register_device_item(device, 0, cpustate->SP.w.l); + state_save_register_device_item(device, 0, cpustate->PC.w.l); + state_save_register_device_item(device, 0, cpustate->HALT); + state_save_register_device_item(device, 0, cpustate->IM); + state_save_register_device_item(device, 0, cpustate->IREQ); + state_save_register_device_item(device, 0, cpustate->ISRV); + state_save_register_device_item(device, 0, cpustate->INTR); + state_save_register_device_item(device, 0, cpustate->IRQ2); + state_save_register_device_item(device, 0, cpustate->IRQ1); + state_save_register_device_item(device, 0, cpustate->STATUS); + state_save_register_device_item_array(device, 0, cpustate->irq_state); } -static void i8080_set_irq_line(int irqline, int state) +static void i8080_set_irq_line(i8085_state *cpustate, int irqline, int state) { if (irqline == INPUT_LINE_NMI) { if( state != CLEAR_LINE ) - i8085_set_TRAP(1); + i8085_set_TRAP(cpustate, 1); } else { - I.irq_state[irqline] = state; + cpustate->irq_state[irqline] = state; if (state == CLEAR_LINE) { - if (!(I.IM & IM_IEN)) - i8085_set_INTR(0); + if (!(cpustate->IM & IM_IEN)) + i8085_set_INTR(cpustate, 0); } else { - if (I.IM & IM_IEN) - i8085_set_INTR(1); + if (cpustate->IM & IM_IEN) + i8085_set_INTR(cpustate, 1); } } } @@ -1650,35 +1637,36 @@ static void i8080_set_irq_line(int irqline, int state) static CPU_SET_INFO( i8085 ) { + i8085_state *cpustate = device->token; switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + I8085_INTR_LINE: i8085_set_irq_line(I8085_INTR_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + I8085_RST55_LINE:i8085_set_irq_line(I8085_RST55_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + I8085_RST65_LINE:i8085_set_irq_line(I8085_RST65_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + I8085_RST75_LINE:i8085_set_irq_line(I8085_RST75_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: i8085_set_irq_line(INPUT_LINE_NMI, info->i); break; - - case CPUINFO_INT_PC: I.PC.w.l = info->i; break; - case CPUINFO_INT_REGISTER + I8085_PC: I.PC.w.l = info->i; break; - case CPUINFO_INT_SP: I.SP.w.l = info->i; break; - case CPUINFO_INT_REGISTER + I8085_SP: I.SP.w.l = info->i; break; - case CPUINFO_INT_REGISTER + I8085_AF: I.AF.w.l = info->i; break; - case CPUINFO_INT_REGISTER + I8085_BC: I.BC.w.l = info->i; break; - case CPUINFO_INT_REGISTER + I8085_DE: I.DE.w.l = info->i; break; - case CPUINFO_INT_REGISTER + I8085_HL: I.HL.w.l = info->i; break; - case CPUINFO_INT_REGISTER + I8085_IM: I.IM = info->i; break; - case CPUINFO_INT_REGISTER + I8085_HALT: I.HALT = info->i; break; - case CPUINFO_INT_REGISTER + I8085_IREQ: I.IREQ = info->i; break; - case CPUINFO_INT_REGISTER + I8085_ISRV: I.ISRV = info->i; break; - case CPUINFO_INT_REGISTER + I8085_VECTOR: I.INTR = info->i; break; - case CPUINFO_INT_REGISTER + I8085_STATUS: I.STATUS = info->i; break; - - case CPUINFO_INT_I8085_SID: if (info->i) I.IM |= IM_SID; else I.IM &= ~IM_SID; break; + case CPUINFO_INT_INPUT_STATE + I8085_INTR_LINE: i8085_set_irq_line(cpustate, I8085_INTR_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + I8085_RST55_LINE:i8085_set_irq_line(cpustate, I8085_RST55_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + I8085_RST65_LINE:i8085_set_irq_line(cpustate, I8085_RST65_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + I8085_RST75_LINE:i8085_set_irq_line(cpustate, I8085_RST75_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: i8085_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; + + case CPUINFO_INT_PC: cpustate->PC.w.l = info->i; break; + case CPUINFO_INT_REGISTER + I8085_PC: cpustate->PC.w.l = info->i; break; + case CPUINFO_INT_SP: cpustate->SP.w.l = info->i; break; + case CPUINFO_INT_REGISTER + I8085_SP: cpustate->SP.w.l = info->i; break; + case CPUINFO_INT_REGISTER + I8085_AF: cpustate->AF.w.l = info->i; break; + case CPUINFO_INT_REGISTER + I8085_BC: cpustate->BC.w.l = info->i; break; + case CPUINFO_INT_REGISTER + I8085_DE: cpustate->DE.w.l = info->i; break; + case CPUINFO_INT_REGISTER + I8085_HL: cpustate->HL.w.l = info->i; break; + case CPUINFO_INT_REGISTER + I8085_IM: cpustate->IM = info->i; break; + case CPUINFO_INT_REGISTER + I8085_HALT: cpustate->HALT = info->i; break; + case CPUINFO_INT_REGISTER + I8085_IREQ: cpustate->IREQ = info->i; break; + case CPUINFO_INT_REGISTER + I8085_ISRV: cpustate->ISRV = info->i; break; + case CPUINFO_INT_REGISTER + I8085_VECTOR: cpustate->INTR = info->i; break; + case CPUINFO_INT_REGISTER + I8085_STATUS: cpustate->STATUS = info->i; break; + + case CPUINFO_INT_I8085_SID: if (info->i) cpustate->IM |= IM_SID; else cpustate->IM &= ~IM_SID; break; /* --- the following bits of info are set as pointers to data or functions --- */ - case CPUINFO_PTR_I8085_SOD_CALLBACK: I.sod_callback = (void (*)(int))info->f; break; - case CPUINFO_PTR_I8085_SID_CALLBACK: I.sid_callback = (int (*)(void))info->f; break; + case CPUINFO_PTR_I8085_SOD_CALLBACK: cpustate->sod_callback = (i8085_sod_func)info->f; break; + case CPUINFO_PTR_I8085_SID_CALLBACK: cpustate->sid_callback = (i8085_sid_func)info->f; break; } } @@ -1690,13 +1678,14 @@ static CPU_SET_INFO( i8085 ) CPU_GET_INFO( i8085 ) { + i8085_state *cpustate = (device != NULL) ? device->token : NULL; switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(I); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i8085_state); break; case CPUINFO_INT_INPUT_LINES: info->i = 4; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; case CPUINFO_INT_CLOCK_DIVIDER: info->i = 2; break; case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; @@ -1714,40 +1703,40 @@ CPU_GET_INFO( i8085 ) case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break; case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_INPUT_STATE + I8085_INTR_LINE: info->i = (I.IREQ & IM_INTR) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + I8085_RST55_LINE:info->i = (I.IREQ & IM_RST55) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + I8085_RST65_LINE:info->i = (I.IREQ & IM_RST65) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + I8085_RST75_LINE:info->i = (I.IREQ & IM_RST75) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = (I.IREQ & IM_TRAP) ? ASSERT_LINE : CLEAR_LINE; break; + case CPUINFO_INT_INPUT_STATE + I8085_INTR_LINE: info->i = (cpustate->IREQ & IM_INTR) ? ASSERT_LINE : CLEAR_LINE; break; + case CPUINFO_INT_INPUT_STATE + I8085_RST55_LINE:info->i = (cpustate->IREQ & IM_RST55) ? ASSERT_LINE : CLEAR_LINE; break; + case CPUINFO_INT_INPUT_STATE + I8085_RST65_LINE:info->i = (cpustate->IREQ & IM_RST65) ? ASSERT_LINE : CLEAR_LINE; break; + case CPUINFO_INT_INPUT_STATE + I8085_RST75_LINE:info->i = (cpustate->IREQ & IM_RST75) ? ASSERT_LINE : CLEAR_LINE; break; + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = (cpustate->IREQ & IM_TRAP) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_PREVIOUSPC: /* not supported */ break; - case CPUINFO_INT_PC: info->i = I.PC.d; break; - case CPUINFO_INT_REGISTER + I8085_PC: info->i = I.PC.w.l; break; - case CPUINFO_INT_SP: info->i = I.SP.d; break; - case CPUINFO_INT_REGISTER + I8085_SP: info->i = I.SP.w.l; break; - case CPUINFO_INT_REGISTER + I8085_AF: info->i = I.AF.w.l; break; - case CPUINFO_INT_REGISTER + I8085_BC: info->i = I.BC.w.l; break; - case CPUINFO_INT_REGISTER + I8085_DE: info->i = I.DE.w.l; break; - case CPUINFO_INT_REGISTER + I8085_HL: info->i = I.HL.w.l; break; - case CPUINFO_INT_REGISTER + I8085_IM: info->i = I.IM; break; - case CPUINFO_INT_REGISTER + I8085_HALT: info->i = I.HALT; break; - case CPUINFO_INT_REGISTER + I8085_IREQ: info->i = I.IREQ; break; - case CPUINFO_INT_REGISTER + I8085_ISRV: info->i = I.ISRV; break; - case CPUINFO_INT_REGISTER + I8085_VECTOR: info->i = I.INTR; break; - case CPUINFO_INT_REGISTER + I8085_STATUS: info->i = I.STATUS; break; + case CPUINFO_INT_PC: info->i = cpustate->PC.d; break; + case CPUINFO_INT_REGISTER + I8085_PC: info->i = cpustate->PC.w.l; break; + case CPUINFO_INT_SP: info->i = cpustate->SP.d; break; + case CPUINFO_INT_REGISTER + I8085_SP: info->i = cpustate->SP.w.l; break; + case CPUINFO_INT_REGISTER + I8085_AF: info->i = cpustate->AF.w.l; break; + case CPUINFO_INT_REGISTER + I8085_BC: info->i = cpustate->BC.w.l; break; + case CPUINFO_INT_REGISTER + I8085_DE: info->i = cpustate->DE.w.l; break; + case CPUINFO_INT_REGISTER + I8085_HL: info->i = cpustate->HL.w.l; break; + case CPUINFO_INT_REGISTER + I8085_IM: info->i = cpustate->IM; break; + case CPUINFO_INT_REGISTER + I8085_HALT: info->i = cpustate->HALT; break; + case CPUINFO_INT_REGISTER + I8085_IREQ: info->i = cpustate->IREQ; break; + case CPUINFO_INT_REGISTER + I8085_ISRV: info->i = cpustate->ISRV; break; + case CPUINFO_INT_REGISTER + I8085_VECTOR: info->i = cpustate->INTR; break; + case CPUINFO_INT_REGISTER + I8085_STATUS: info->i = cpustate->STATUS; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i8085); break; - case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(i8085); break; - case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(i8085); break; + case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break; + case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break; case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i8085); break; case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(i8085); break; case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(i8085); break; case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(i8085); break; case CPUINFO_PTR_BURN: info->burn = NULL; break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8085); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &i8085_ICount; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ case CPUINFO_STR_NAME: strcpy(info->s, "8085A"); break; @@ -1758,28 +1747,28 @@ CPU_GET_INFO( i8085 ) case CPUINFO_STR_FLAGS: sprintf(info->s, "%c%c%c%c%c%c%c%c", - I.AF.b.l & 0x80 ? 'S':'.', - I.AF.b.l & 0x40 ? 'Z':'.', - I.AF.b.l & 0x20 ? '?':'.', - I.AF.b.l & 0x10 ? 'H':'.', - I.AF.b.l & 0x08 ? '?':'.', - I.AF.b.l & 0x04 ? 'P':'.', - I.AF.b.l & 0x02 ? 'N':'.', - I.AF.b.l & 0x01 ? 'C':'.'); - break; - - case CPUINFO_STR_REGISTER + I8085_AF: sprintf(info->s, "AF:%04X", I.AF.w.l); break; - case CPUINFO_STR_REGISTER + I8085_BC: sprintf(info->s, "BC:%04X", I.BC.w.l); break; - case CPUINFO_STR_REGISTER + I8085_DE: sprintf(info->s, "DE:%04X", I.DE.w.l); break; - case CPUINFO_STR_REGISTER + I8085_HL: sprintf(info->s, "HL:%04X", I.HL.w.l); break; - case CPUINFO_STR_REGISTER + I8085_SP: sprintf(info->s, "SP:%04X", I.SP.w.l); break; - case CPUINFO_STR_REGISTER + I8085_PC: sprintf(info->s, "PC:%04X", I.PC.w.l); break; - case CPUINFO_STR_REGISTER + I8085_IM: sprintf(info->s, "IM:%02X", I.IM); break; - case CPUINFO_STR_REGISTER + I8085_HALT: sprintf(info->s, "HALT:%d", I.HALT); break; - case CPUINFO_STR_REGISTER + I8085_IREQ: sprintf(info->s, "IREQ:%02X", I.IREQ); break; - case CPUINFO_STR_REGISTER + I8085_ISRV: sprintf(info->s, "ISRV:%02X", I.ISRV); break; - case CPUINFO_STR_REGISTER + I8085_VECTOR: sprintf(info->s, "VEC:%02X", I.INTR); break; - case CPUINFO_STR_REGISTER + I8085_STATUS: sprintf(info->s, "SW:%02X", I.STATUS); break; + cpustate->AF.b.l & 0x80 ? 'S':'.', + cpustate->AF.b.l & 0x40 ? 'Z':'.', + cpustate->AF.b.l & 0x20 ? '?':'.', + cpustate->AF.b.l & 0x10 ? 'H':'.', + cpustate->AF.b.l & 0x08 ? '?':'.', + cpustate->AF.b.l & 0x04 ? 'P':'.', + cpustate->AF.b.l & 0x02 ? 'N':'.', + cpustate->AF.b.l & 0x01 ? 'C':'.'); + break; + + case CPUINFO_STR_REGISTER + I8085_AF: sprintf(info->s, "AF:%04X", cpustate->AF.w.l); break; + case CPUINFO_STR_REGISTER + I8085_BC: sprintf(info->s, "BC:%04X", cpustate->BC.w.l); break; + case CPUINFO_STR_REGISTER + I8085_DE: sprintf(info->s, "DE:%04X", cpustate->DE.w.l); break; + case CPUINFO_STR_REGISTER + I8085_HL: sprintf(info->s, "HL:%04X", cpustate->HL.w.l); break; + case CPUINFO_STR_REGISTER + I8085_SP: sprintf(info->s, "SP:%04X", cpustate->SP.w.l); break; + case CPUINFO_STR_REGISTER + I8085_PC: sprintf(info->s, "PC:%04X", cpustate->PC.w.l); break; + case CPUINFO_STR_REGISTER + I8085_IM: sprintf(info->s, "IM:%02X", cpustate->IM); break; + case CPUINFO_STR_REGISTER + I8085_HALT: sprintf(info->s, "HALT:%d", cpustate->HALT); break; + case CPUINFO_STR_REGISTER + I8085_IREQ: sprintf(info->s, "IREQ:%02X", cpustate->IREQ); break; + case CPUINFO_STR_REGISTER + I8085_ISRV: sprintf(info->s, "ISRV:%02X", cpustate->ISRV); break; + case CPUINFO_STR_REGISTER + I8085_VECTOR: sprintf(info->s, "VEC:%02X", cpustate->INTR); break; + case CPUINFO_STR_REGISTER + I8085_STATUS: sprintf(info->s, "SW:%02X", cpustate->STATUS); break; } } @@ -1791,11 +1780,12 @@ CPU_GET_INFO( i8085 ) static CPU_SET_INFO( i8080 ) { + i8085_state *cpustate = device->token; switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + I8080_INTR_LINE: i8080_set_irq_line(I8080_INTR_LINE, info->i); break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: i8080_set_irq_line(INPUT_LINE_NMI, info->i); break; + case CPUINFO_INT_INPUT_STATE + I8080_INTR_LINE: i8080_set_irq_line(cpustate, I8080_INTR_LINE, info->i); break; + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: i8080_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; default: CPU_SET_INFO_CALL(i8085); break; } @@ -1803,13 +1793,14 @@ static CPU_SET_INFO( i8080 ) CPU_GET_INFO( i8080 ) { + i8085_state *cpustate = (device != NULL) ? device->token : NULL; switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; case CPUINFO_INT_INPUT_LINES: info->i = 1; break; - case CPUINFO_INT_INPUT_STATE + I8085_INTR_LINE: info->i = (I.IREQ & IM_INTR) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = (I.IREQ & IM_TRAP) ? ASSERT_LINE : CLEAR_LINE; break; + case CPUINFO_INT_INPUT_STATE + I8085_INTR_LINE: info->i = (cpustate->IREQ & IM_INTR) ? ASSERT_LINE : CLEAR_LINE; break; + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = (cpustate->IREQ & IM_TRAP) ? ASSERT_LINE : CLEAR_LINE; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i8080); break; diff --git a/src/emu/cpu/i8085/i8085.h b/src/emu/cpu/i8085/i8085.h index 4458f64df87..4ef6cc4873e 100644 --- a/src/emu/cpu/i8085/i8085.h +++ b/src/emu/cpu/i8085/i8085.h @@ -18,6 +18,10 @@ enum CPUINFO_INT_I8085_SID = CPUINFO_INT_CPU_SPECIFIC }; +typedef void (*i8085_sod_func)(const device_config *device, int state); +typedef int (*i8085_sid_func)(const device_config *device); + + #define I8085_INTR_LINE 0 #define I8085_RST55_LINE 1 #define I8085_RST65_LINE 2 @@ -55,4 +59,19 @@ CPU_GET_INFO( i8080 ); CPU_DISASSEMBLE( i8085 ); +INLINE void i8085_set_sod_callback(const device_config *device, i8085_sod_func callback) +{ + cpu_set_info_fct(device, CPUINFO_PTR_I8085_SOD_CALLBACK, (genf *)callback); +} + +INLINE void i8085_set_sid_callback(const device_config *device, i8085_sid_func callback) +{ + cpu_set_info_fct(device, CPUINFO_PTR_I8085_SID_CALLBACK, (genf *)callback); +} + +INLINE void i8085_set_sid(const device_config *device, int sid) +{ + cpu_set_info_int(device, CPUINFO_INT_I8085_SID, sid); +} + #endif diff --git a/src/emu/cpu/i8085/i8085cpu.h b/src/emu/cpu/i8085/i8085cpu.h index f1fed3c83a0..f1dafc26bf5 100644 --- a/src/emu/cpu/i8085/i8085cpu.h +++ b/src/emu/cpu/i8085/i8085cpu.h @@ -37,110 +37,110 @@ #define ADDR_RST75 0x003c #define ADDR_INTR 0x0038 -#define M_INR(R) {UINT8 hc = ((R & 0x0f) == 0x0f) ? HF : 0; ++R; I.AF.b.l= (I.AF.b.l & CF ) | ZSP[R] | hc; } -#define M_DCR(R) {UINT8 hc = ((R & 0x0f) == 0x00) ? HF : 0; --R; I.AF.b.l= (I.AF.b.l & CF ) | ZSP[R] | hc | NF; } -#define M_MVI(R) R=ARG() +#define M_INR(R) {UINT8 hc = ((R & 0x0f) == 0x0f) ? HF : 0; ++R; cpustate->AF.b.l= (cpustate->AF.b.l & CF ) | ZSP[R] | hc; } +#define M_DCR(R) {UINT8 hc = ((R & 0x0f) == 0x00) ? HF : 0; --R; cpustate->AF.b.l= (cpustate->AF.b.l & CF ) | ZSP[R] | hc | NF; } +#define M_MVI(R) R=ARG(cpustate) -#define M_ANA(R) { int i = (((I.AF.b.h | R)>>3) & 1)*HF; I.AF.b.h&=R; I.AF.b.l=ZSP[I.AF.b.h]; if( I.cputype ) { I.AF.b.l |= HF; } else {I.AF.b.l |= i; } } -#define M_ORA(R) I.AF.b.h|=R; I.AF.b.l=ZSP[I.AF.b.h] -#define M_XRA(R) I.AF.b.h^=R; I.AF.b.l=ZSP[I.AF.b.h] +#define M_ANA(R) { int i = (((cpustate->AF.b.h | R)>>3) & 1)*HF; cpustate->AF.b.h&=R; cpustate->AF.b.l=ZSP[cpustate->AF.b.h]; if( cpustate->cputype ) { cpustate->AF.b.l |= HF; } else {cpustate->AF.b.l |= i; } } +#define M_ORA(R) cpustate->AF.b.h|=R; cpustate->AF.b.l=ZSP[cpustate->AF.b.h] +#define M_XRA(R) cpustate->AF.b.h^=R; cpustate->AF.b.l=ZSP[cpustate->AF.b.h] #define M_RLC { \ - I.AF.b.h = (I.AF.b.h << 1) | (I.AF.b.h >> 7); \ - I.AF.b.l = (I.AF.b.l & 0xfe) | (I.AF.b.h & CF); \ + cpustate->AF.b.h = (cpustate->AF.b.h << 1) | (cpustate->AF.b.h >> 7); \ + cpustate->AF.b.l = (cpustate->AF.b.l & 0xfe) | (cpustate->AF.b.h & CF); \ } #define M_RRC { \ - I.AF.b.l = (I.AF.b.l & 0xfe) | (I.AF.b.h & CF); \ - I.AF.b.h = (I.AF.b.h >> 1) | (I.AF.b.h << 7); \ + cpustate->AF.b.l = (cpustate->AF.b.l & 0xfe) | (cpustate->AF.b.h & CF); \ + cpustate->AF.b.h = (cpustate->AF.b.h >> 1) | (cpustate->AF.b.h << 7); \ } #define M_RAL { \ - int c = I.AF.b.l&CF; \ - I.AF.b.l = (I.AF.b.l & 0xfe) | (I.AF.b.h >> 7); \ - I.AF.b.h = (I.AF.b.h << 1) | c; \ + int c = cpustate->AF.b.l&CF; \ + cpustate->AF.b.l = (cpustate->AF.b.l & 0xfe) | (cpustate->AF.b.h >> 7); \ + cpustate->AF.b.h = (cpustate->AF.b.h << 1) | c; \ } #define M_RAR { \ - int c = (I.AF.b.l&CF) << 7; \ - I.AF.b.l = (I.AF.b.l & 0xfe) | (I.AF.b.h & CF); \ - I.AF.b.h = (I.AF.b.h >> 1) | c; \ + int c = (cpustate->AF.b.l&CF) << 7; \ + cpustate->AF.b.l = (cpustate->AF.b.l & 0xfe) | (cpustate->AF.b.h & CF); \ + cpustate->AF.b.h = (cpustate->AF.b.h >> 1) | c; \ } #define M_ADD(R) { \ -int q = I.AF.b.h+R; \ - I.AF.b.l=ZSP[q&255]|((q>>8)&CF)| \ - ((I.AF.b.h^q^R)&HF)| \ - (((R^I.AF.b.h^SF)&(R^q)&SF)>>5); \ - I.AF.b.h=q; \ +int q = cpustate->AF.b.h+R; \ + cpustate->AF.b.l=ZSP[q&255]|((q>>8)&CF)| \ + ((cpustate->AF.b.h^q^R)&HF)| \ + (((R^cpustate->AF.b.h^SF)&(R^q)&SF)>>5); \ + cpustate->AF.b.h=q; \ } #define M_ADC(R) { \ - int q = I.AF.b.h+R+(I.AF.b.l&CF); \ - I.AF.b.l=ZSP[q&255]|((q>>8)&CF)| \ - ((I.AF.b.h^q^R)&HF)| \ - (((R^I.AF.b.h^SF)&(R^q)&SF)>>5); \ - I.AF.b.h=q; \ + int q = cpustate->AF.b.h+R+(cpustate->AF.b.l&CF); \ + cpustate->AF.b.l=ZSP[q&255]|((q>>8)&CF)| \ + ((cpustate->AF.b.h^q^R)&HF)| \ + (((R^cpustate->AF.b.h^SF)&(R^q)&SF)>>5); \ + cpustate->AF.b.h=q; \ } #define M_SUB(R) { \ - int q = I.AF.b.h-R; \ - I.AF.b.l=ZSP[q&255]|((q>>8)&CF)|NF| \ - ((I.AF.b.h^q^R)&HF)| \ - (((R^I.AF.b.h)&(I.AF.b.h^q)&SF)>>5); \ - I.AF.b.h=q; \ + int q = cpustate->AF.b.h-R; \ + cpustate->AF.b.l=ZSP[q&255]|((q>>8)&CF)|NF| \ + ((cpustate->AF.b.h^q^R)&HF)| \ + (((R^cpustate->AF.b.h)&(cpustate->AF.b.h^q)&SF)>>5); \ + cpustate->AF.b.h=q; \ } #define M_SBB(R) { \ - int q = I.AF.b.h-R-(I.AF.b.l&CF); \ - I.AF.b.l=ZSP[q&255]|((q>>8)&CF)|NF| \ - ((I.AF.b.h^q^R)&HF)| \ - (((R^I.AF.b.h)&(I.AF.b.h^q)&SF)>>5); \ - I.AF.b.h=q; \ + int q = cpustate->AF.b.h-R-(cpustate->AF.b.l&CF); \ + cpustate->AF.b.l=ZSP[q&255]|((q>>8)&CF)|NF| \ + ((cpustate->AF.b.h^q^R)&HF)| \ + (((R^cpustate->AF.b.h)&(cpustate->AF.b.h^q)&SF)>>5); \ + cpustate->AF.b.h=q; \ } #define M_CMP(R) { \ - int q = I.AF.b.h-R; \ - I.AF.b.l=ZSP[q&255]|((q>>8)&CF)|NF| \ - ((I.AF.b.h^q^R)&HF)| \ - (((R^I.AF.b.h)&(I.AF.b.h^q)&SF)>>5); \ + int q = cpustate->AF.b.h-R; \ + cpustate->AF.b.l=ZSP[q&255]|((q>>8)&CF)|NF| \ + ((cpustate->AF.b.h^q^R)&HF)| \ + (((R^cpustate->AF.b.h)&(cpustate->AF.b.h^q)&SF)>>5); \ } #define M_IN \ - I.STATUS = 0x42; \ - I.XX.d=ARG(); \ - I.AF.b.h=memory_read_byte_8le(I.io, I.XX.d); + cpustate->STATUS = 0x42; \ + cpustate->XX.d=ARG(cpustate); \ + cpustate->AF.b.h=memory_read_byte_8le(cpustate->io, cpustate->XX.d); #define M_OUT \ - I.STATUS = 0x10; \ - I.XX.d=ARG(); \ - memory_write_byte_8le(I.io, I.XX.d,I.AF.b.h) + cpustate->STATUS = 0x10; \ + cpustate->XX.d=ARG(cpustate); \ + memory_write_byte_8le(cpustate->io, cpustate->XX.d,cpustate->AF.b.h) #define M_DAD(R) { \ - int q = I.HL.d + I.R.d; \ - I.AF.b.l = ( I.AF.b.l & ~(HF+CF) ) | \ - ( ((I.HL.d^q^I.R.d) >> 8) & HF ) | \ + int q = cpustate->HL.d + cpustate->R.d; \ + cpustate->AF.b.l = ( cpustate->AF.b.l & ~(HF+CF) ) | \ + ( ((cpustate->HL.d^q^cpustate->R.d) >> 8) & HF ) | \ ( (q>>16) & CF ); \ - I.HL.w.l = q; \ + cpustate->HL.w.l = q; \ } #define M_PUSH(R) { \ - I.STATUS = 0x04; \ - memory_write_byte_8le(I.program, --I.SP.w.l, I.R.b.h); \ - memory_write_byte_8le(I.program, --I.SP.w.l, I.R.b.l); \ + cpustate->STATUS = 0x04; \ + memory_write_byte_8le(cpustate->program, --cpustate->SP.w.l, cpustate->R.b.h); \ + memory_write_byte_8le(cpustate->program, --cpustate->SP.w.l, cpustate->R.b.l); \ } #define M_POP(R) { \ - I.STATUS = 0x86; \ - I.R.b.l = memory_read_byte_8le(I.program, I.SP.w.l++); \ - I.R.b.h = memory_read_byte_8le(I.program, I.SP.w.l++); \ + cpustate->STATUS = 0x86; \ + cpustate->R.b.l = memory_read_byte_8le(cpustate->program, cpustate->SP.w.l++); \ + cpustate->R.b.h = memory_read_byte_8le(cpustate->program, cpustate->SP.w.l++); \ } #define M_RET(cc) \ { \ if (cc) \ { \ - i8085_ICount -= 6; \ + cpustate->icount -= 6; \ M_POP(PC); \ } \ } @@ -148,10 +148,10 @@ int q = I.AF.b.h+R; \ // On 8085 jump if condition is not satisfied is shorter #define M_JMP(cc) { \ if (cc) { \ - I.PC.w.l = ARG16(); \ + cpustate->PC.w.l = ARG16(cpustate); \ } else { \ - I.PC.w.l += 2; \ - i8085_ICount += (I.cputype) ? 3 : 0; \ + cpustate->PC.w.l += 2; \ + cpustate->icount += (cpustate->cputype) ? 3 : 0; \ } \ } @@ -160,30 +160,30 @@ int q = I.AF.b.h+R; \ { \ if (cc) \ { \ - UINT16 a = ARG16(); \ - i8085_ICount -= (I.cputype) ? 7 : 6 ; \ + UINT16 a = ARG16(cpustate); \ + cpustate->icount -= (cpustate->cputype) ? 7 : 6 ; \ M_PUSH(PC); \ - I.PC.d = a; \ + cpustate->PC.d = a; \ } else { \ - I.PC.w.l += 2; \ - i8085_ICount += (I.cputype) ? 2 : 0; \ + cpustate->PC.w.l += 2; \ + cpustate->icount += (cpustate->cputype) ? 2 : 0; \ } \ } #define M_RST(nn) { \ M_PUSH(PC); \ - I.PC.d = 8 * nn; \ -} - -#define M_DSUB() { \ - int q = I.HL.b.l-I.BC.b.l; \ - I.AF.b.l=ZS[q&255]|((q>>8)&CF)|NF| \ - ((I.HL.b.l^q^I.BC.b.l)&HF)| \ - (((I.BC.b.l^I.HL.b.l)&(I.HL.b.l^q)&SF)>>5); \ - I.HL.b.l=q; \ - q = I.HL.b.h-I.BC.b.h-(I.AF.b.l&CF); \ - I.AF.b.l=ZS[q&255]|((q>>8)&CF)|NF| \ - ((I.HL.b.h^q^I.BC.b.h)&HF)| \ - (((I.BC.b.h^I.HL.b.h)&(I.HL.b.h^q)&SF)>>5); \ - if (I.HL.b.l!=0) I.AF.b.l&=~ZF; \ + cpustate->PC.d = 8 * nn; \ +} + +#define M_DSUB(cpustate) { \ + int q = cpustate->HL.b.l-cpustate->BC.b.l; \ + cpustate->AF.b.l=ZS[q&255]|((q>>8)&CF)|NF| \ + ((cpustate->HL.b.l^q^cpustate->BC.b.l)&HF)| \ + (((cpustate->BC.b.l^cpustate->HL.b.l)&(cpustate->HL.b.l^q)&SF)>>5); \ + cpustate->HL.b.l=q; \ + q = cpustate->HL.b.h-cpustate->BC.b.h-(cpustate->AF.b.l&CF); \ + cpustate->AF.b.l=ZS[q&255]|((q>>8)&CF)|NF| \ + ((cpustate->HL.b.h^q^cpustate->BC.b.h)&HF)| \ + (((cpustate->BC.b.h^cpustate->HL.b.h)&(cpustate->HL.b.h^q)&SF)>>5); \ + if (cpustate->HL.b.l!=0) cpustate->AF.b.l&=~ZF; \ } diff --git a/src/mame/audio/redalert.c b/src/mame/audio/redalert.c index 878475e8fdb..86ce402bad6 100644 --- a/src/mame/audio/redalert.c +++ b/src/mame/audio/redalert.c @@ -169,13 +169,13 @@ WRITE8_HANDLER( redalert_voice_command_w ) } -static void sod_callback(int data) +static void sod_callback(const device_config *device, int data) { hc55516_digit_w(0, data); } -static int sid_callback(void) +static int sid_callback(const device_config *device) { return hc55516_clock_state_r(0); } @@ -183,8 +183,8 @@ static int sid_callback(void) static SOUND_START( redalert_voice ) { - cpu_set_info_fct(machine->cpu[2], CPUINFO_PTR_I8085_SOD_CALLBACK, (void *)sod_callback); - cpu_set_info_fct(machine->cpu[2], CPUINFO_PTR_I8085_SID_CALLBACK, (void *)sid_callback); + i8085_set_sod_callback(machine->cpu[2], sod_callback); + i8085_set_sid_callback(machine->cpu[2], sid_callback); } diff --git a/src/mame/drivers/dwarfd.c b/src/mame/drivers/dwarfd.c index 76fb5cfea36..dbae2c6055f 100644 --- a/src/mame/drivers/dwarfd.c +++ b/src/mame/drivers/dwarfd.c @@ -534,7 +534,7 @@ static VIDEO_UPDATE( dwarfd ) return 0; } -static void dwarfd_sod_callback(int nSO) +static void dwarfd_sod_callback(const device_config *device, int nSO) { crt_access=nSO; } @@ -544,7 +544,7 @@ static INTERRUPT_GEN( dwarfd_interrupt ) { if(cpu_getiloops(device) < NUM_LINES) { - cpu_set_info_fct(device, CPUINFO_PTR_I8085_SOD_CALLBACK, (void*)dwarfd_sod_callback); + i8085_set_sod_callback(device, dwarfd_sod_callback); cpu_set_input_line(device,I8085_RST65_LINE,HOLD_LINE); // 34 - every 8th line line=cpu_getiloops(device); idx=0; @@ -776,7 +776,7 @@ static DRIVER_INIT(dwarfd) // src[i] = src[i]&0xe0; } - cpu_set_info_fct(machine->cpu[0], CPUINFO_PTR_I8085_SOD_CALLBACK, (void*)dwarfd_sod_callback); + i8085_set_sod_callback(machine->cpu[0], dwarfd_sod_callback); videobuf=auto_malloc(0x8000); dwarfd_ram=auto_malloc(0x1000); diff --git a/src/mame/drivers/phoenix.c b/src/mame/drivers/phoenix.c index e12eeb8eb0e..31faf2f3ef8 100644 --- a/src/mame/drivers/phoenix.c +++ b/src/mame/drivers/phoenix.c @@ -1020,7 +1020,7 @@ static DRIVER_INIT( condor ) static DRIVER_INIT( survival ) { - cpu_set_info_fct(machine->cpu[0], CPUINFO_PTR_I8085_SID_CALLBACK, (void*)survival_sid_callback); + i8085_set_sid_callback(machine->cpu[0], survival_sid_callback); } diff --git a/src/mame/includes/phoenix.h b/src/mame/includes/phoenix.h index 848b05de334..519daf4018b 100644 --- a/src/mame/includes/phoenix.h +++ b/src/mame/includes/phoenix.h @@ -68,5 +68,5 @@ CUSTOM_INPUT( pleiads_protection_r ); READ8_HANDLER( survival_input_port_0_r ); READ8_HANDLER( survival_protection_r ); -int survival_sid_callback( void ); +int survival_sid_callback( const device_config *device ); diff --git a/src/mame/video/phoenix.c b/src/mame/video/phoenix.c index 1c8d8fd2745..50552b4790a 100644 --- a/src/mame/video/phoenix.c +++ b/src/mame/video/phoenix.c @@ -437,7 +437,7 @@ READ8_HANDLER( survival_protection_r ) return survival_protection_value; } -int survival_sid_callback( void ) +int survival_sid_callback( const device_config *device ) { return survival_sid_value; } |