diff options
-rw-r--r-- | src/devices/bus/ti99/internal/998board.cpp | 226 | ||||
-rw-r--r-- | src/devices/bus/ti99/internal/998board.h | 41 | ||||
-rw-r--r-- | src/mame/drivers/altair.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/ccs2810.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/cd2650.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/cv1k.cpp | 16 | ||||
-rw-r--r-- | src/mame/drivers/dual68.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/imsai.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/jade.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/marinedt.cpp | 315 | ||||
-rw-r--r-- | src/mame/drivers/ptcsol.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/seattlecmp.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/super6.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/superslave.cpp | 1 | ||||
-rw-r--r-- | src/mame/drivers/techno.cpp | 56 | ||||
-rw-r--r-- | src/mame/drivers/z100.cpp | 1 | ||||
-rw-r--r-- | src/mame/mame.lst | 1 |
17 files changed, 609 insertions, 57 deletions
diff --git a/src/devices/bus/ti99/internal/998board.cpp b/src/devices/bus/ti99/internal/998board.cpp index f6eaf940e4d..13258348133 100644 --- a/src/devices/bus/ti99/internal/998board.cpp +++ b/src/devices/bus/ti99/internal/998board.cpp @@ -2245,13 +2245,24 @@ enum oso_device::oso_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : bus::hexbus::hexbus_chained_device(mconfig, TI99_OSO, tag, owner, clock), + m_int(*this), m_data(0), m_status(0xff), m_control(0), - m_xmit(0), + m_xmit(0), m_lasthxvalue(0x01), m_clkcount(0), - m_xmit_send(0) -{ + m_sbav(false), m_sbavold(true), + m_bav(false), m_bavhold(false), + m_shsk(false), m_shskold(true), + m_hsk(false), m_hskhold(false), + m_wq1(false), m_wq1old(true), m_wq2(false), m_wq2old(true), + m_wnp(false), + m_wbusy(false), m_wbusyold(false), + m_sendbyte(false), + m_wrst(false), m_counting(false), + m_rq2(false), m_rq2old(true) +{ + (void)m_shskold; m_hexbus_inbound = nullptr; m_hexbus_outbound = nullptr; } @@ -2270,7 +2281,11 @@ READ8_MEMBER( oso_device::read ) case 1: // read 5FFA: read status register value = m_status; - if (TRACE_OSO) logerror("Read status %02x\n", value); + clear_int_status(); + if (TRACE_OSO) logerror("Read status %02x (HSKWT=%d,HSKRD=%d,BAVIAS=%d,BAVAIS=%d,SBAV=%d,WBUSY=%d,RBUSY=%d,SHSK=%d)\n", value, + (value&HSKWT)? 1:0, (value&HSKRD)? 1:0, (value&BAVIAS)? 1:0, + (value&BAVAIS)? 1:0, (value&SBAV)? 1:0, (value&WBUSY)? 1:0, + (value&RBUSY)? 1:0,(value&SHSK)? 1:0); break; case 2: // read 5FFC: read control register @@ -2294,14 +2309,30 @@ WRITE8_MEMBER( oso_device::write ) case 0: // write 5FF8: write transmit register if (TRACE_OSO) logerror("Write transmit register %02x\n", data); + + // trigger some actions in the write subsystem + m_sendbyte = true; + if (!m_wq1) + { + m_wbusy = true; + m_wbusyold = true; + set_status(WBUSY, m_wbusy); + } + m_xmit = data; - m_xmit_send = 2; - m_status |= HSKWT; break; case 1: // write 5FFA: write control register - if (TRACE_OSO) logerror("Write control register %02x\n", data); + if (TRACE_OSO) logerror("Write control register %02x (WIEN=%d, RIEN=%d, BAVIAEN=%d, BAVAIEN=%d, BAVC=%d, WEN=%d, REN=%d)\n", + data, (data & WIEN)? 1:0, (data & RIEN)? 1:0, (data&BAVIAEN)? 1:0, (data&BAVAIEN)? 1:0, + (data & BAVC)? 1:0, (data & WEN)? 1:0, (data & REN)? 1:0); m_control = data; + if (!control_bit(WEN)) + { + // Reset some flipflops in the write timing section + m_wq1 = m_wq2 = m_wrst = false; + } + m_bav = control_bit(BAVC); break; default: // write 5FFC, 5FFE: undefined @@ -2310,6 +2341,12 @@ WRITE8_MEMBER( oso_device::write ) } } +void oso_device::clear_int_status() +{ + m_status &= ~(HSKWT | HSKRD | BAVIAS | BAVAIS); + m_int(CLEAR_LINE); +} + void oso_device::hexbus_value_changed(uint8_t data) { if (TRACE_OSO) logerror("Hexbus value changed to %02x\n", data); @@ -2320,28 +2357,185 @@ void oso_device::hexbus_value_changed(uint8_t data) */ WRITE_LINE_MEMBER( oso_device::clock_in ) { - if (state==ASSERT_LINE) m_clkcount++; - if (m_clkcount > 30 && ((m_control & WEN)!=0) && (m_xmit_send > 0)) + if (state==ASSERT_LINE) { - if (TRACE_OSO) logerror("Write nibble %d\n", 3-m_xmit_send); - hexbus_write(((m_xmit & 0x0c)<<4) | (m_xmit & 0x03)); - m_xmit >>= 4; - m_clkcount = 0; - m_xmit_send--; + // Control lines SHSK, SBAV + // When BAV/HSK is 0/1 for two rising edges of Phi3*, SBAV/SHSK goes to + // 0/1 at the following falling edge of Phi3*. + // Page 5 + m_sbav = m_bavhold && m_bav; + m_bavhold = m_bav; + m_shsk = m_hskhold && m_hsk; + m_hskhold = m_hsk; + set_status(SHSK, m_shsk); + set_status(SBAV, m_sbav); + + // Implement the write timing logic + // This subcircuit in the OSO chip autonomously runs the Hexbus + // protocol. After loading a byte into the transmit register, it sends + // both nibbles (little-endian) one after another over the Hexbus, + // pausing for 30 cycles, and checking the HSK line. + + // The schematics show some fascinating signal line spaghetti with + // embedded JK* flipflops which may give you some major headaches. + // Compared to that, the lines below are a true relief. + + if (control_bit(WEN)) // Nothing happens without WEN + { + if (TRACE_OSO) if (!m_wrst && m_sendbyte) logerror("Starting write process\n"); + // Page 3: Write timing + // Note: First pass counts to 30, second to 31 + bool cnt30 = ((m_clkcount & 0x1e) == 30); + bool cont = (m_wrst && !m_wq2 && !m_wq1) || (cnt30 && m_wq2 && !m_wq1) + || (cnt30 && !m_wq2 && m_wq1) || (m_shsk && m_wq2 && m_wq1); + + bool jwq1 = cont && m_wq2; + bool kwq1 = !((cont && !m_wq2) || (!cont && m_wq2 && m_wnp)); + + bool jwq2 = cont; + bool kwq2 = !(m_wq1 && !cont); + + if (m_wq1 == m_wq2) m_clkcount = 0; + + // Reset "byte loaded" flipflop during the second phase + if (m_wq1 == true) + m_sendbyte = false; + + // WBUSY is asserted on byte load, during phase 1, and phase 2. + m_wbusy = m_sendbyte || m_wq1 || m_wq2; + + // Set status bits and raise interrupt (p. 4) + set_status(WBUSY, m_wbusy); + if (m_wbusy != m_wbusyold) + { + // Raising edge of wbusy* + if (!m_wbusy) set_status(HSKWT, !m_wbusy); + m_wbusyold = m_wbusy; + } + + if (m_rq2 != m_rq2old) + { + // Raising edge of RQ2* + if (!m_rq2) + { + set_status(HSKRD, m_rq2); + } + m_wbusyold = m_wbusy; + } + + if (m_sbav != m_sbavold) + { + // Raising edge of SBAV -> BAVIA + // Falling edge of SBAV -> BAVAI + if (m_sbav) + set_status(BAVIAS, m_sbav); + else + set_status(BAVAIS, !m_sbav); + } + + // Operate flipflops + // Write phases + // 74LS109: J-K* flipflop (inverted K) + if (jwq1) + { + if (!kwq1) m_wq1 = !m_wq1; + else m_wq1 = true; + } + else + if (!kwq1) m_wq1 = false; + + if (jwq2) + { + if (!kwq2) m_wq2 = !m_wq2; + else m_wq2 = true; + } + else + if (!kwq2) m_wq2 = false; + + // Set WNP on rising edge of WQ2* + if (m_wq2 != m_wq2old) + { + if (!m_wq2) + m_wnp = true; + + m_wq2old = m_wq2; + } + m_wq1old = m_wq1; + + // Set HSK + m_hsk = !m_wq1 && m_wq2; + + // Reset WNP if phases are done + if (!m_wq2 && !m_wq1) + { + m_wnp = false; + } + update_hexbus(); + } + else + { + m_wq1 = m_wq2 = m_wrst = m_counting = false; + m_clkcount = 0; + } + } + // Actions that occur for Phi3=0 + else + { + m_wrst = m_sendbyte; + // Only count when one phase is active + m_counting = !(m_wq1==m_wq2); + + if (m_counting) + m_clkcount++; + else + m_clkcount = 0; // Reset when not counting + } + + // Show some lines in log + if (TRACE_OSO) { + if (m_sbav != m_sbavold) { + logerror("SBAV = %d\n", m_sbav? 1 : 0); + m_sbavold = m_sbav; + } + } + + // Raise interrupt + if ((control_bit(WIEN) && status_bit(HSKWT)) + || (control_bit(RIEN) && status_bit(HSKRD)) + || (control_bit(BAVAIEN) && status_bit(BAVAIS)) + || (control_bit(BAVIAEN) && status_bit(BAVIAS))) + { + m_int(ASSERT_LINE); } } +void oso_device::update_hexbus() +{ + uint8_t value = 0x00; + uint8_t nibble = m_xmit; + if (m_wnp) nibble >>= 4; + + value = ((m_xmit & 0x0c)<<4) | (m_xmit & 0x03); + if (!m_hsk) value |= 0x10; + if (!m_bav) value |= 0x04; + if (value != m_lasthxvalue) + { + if (TRACE_OSO) logerror("Set hexbus = %02x (BAV*=%d, HSK*=%d, data=%01x)\n", value, (value & 0x04)? 1:0, (value & 0x10)? 1:0, ((value>>4)&0x0c) | (value&0x03)); + hexbus_write(value); + } + m_lasthxvalue = value; +} + void oso_device::device_start() { logerror("Starting\n"); m_status = m_xmit = m_control = m_data = 0; + m_int.resolve_safe(); m_hexbus_outbound = dynamic_cast<bus::hexbus::hexbus_device*>(machine().device(TI_HEXBUS_TAG)); // Establish callback for inbound propagations m_hexbus_outbound->set_chain_element(this); - // Establish callback - m_hexbus_outbound->set_chain_element(this); save_item(NAME(m_data)); save_item(NAME(m_status)); diff --git a/src/devices/bus/ti99/internal/998board.h b/src/devices/bus/ti99/internal/998board.h index bde035d7d73..b3c2d112254 100644 --- a/src/devices/bus/ti99/internal/998board.h +++ b/src/devices/bus/ti99/internal/998board.h @@ -436,15 +436,51 @@ public: WRITE_LINE_MEMBER( clock_in ); + // INT line + devcb_write_line m_int; + private: + bool control_bit(int bit) { return (m_control & bit)!=0; } + bool status_bit(int bit) { return (m_status & bit)!=0; } + void clear_int_status(); + void set_status(int bit, bool set) { m_status = (set)? (m_status | bit) : (m_status & ~bit); } + void update_hexbus(); + uint8_t m_data; uint8_t m_status; uint8_t m_control; uint8_t m_xmit; + uint8_t m_lasthxvalue; + int m_clkcount; - int m_xmit_send; + bool m_sbav; + bool m_sbavold; + bool m_bav; + bool m_bavhold; + + bool m_shsk; + bool m_shskold; + bool m_hsk; + bool m_hskhold; + + // Page 3 in OSO schematics + bool m_wq1; + bool m_wq1old; + bool m_wq2; + bool m_wq2old; + bool m_wnp; + bool m_wbusy; + bool m_wbusyold; + bool m_sendbyte; + + bool m_wrst; + + bool m_counting; + + bool m_rq2; + bool m_rq2old; }; class mainboard8_device : public device_t @@ -612,6 +648,9 @@ private: #define MCFG_MAINBOARD8_HOLD_CALLBACK(_write) \ devcb = &bus::ti99::internal::mainboard8_device::set_hold_wr_callback(*device, DEVCB_##_write); +#define MCFG_OSO_INT_CALLBACK(_int) \ + devcb = &bus::ti99::internal::oso_device::set_int_callback(*device, DEVCB##_int); + DECLARE_DEVICE_TYPE_NS(TI99_MAINBOARD8, bus::ti99::internal, mainboard8_device) DECLARE_DEVICE_TYPE_NS(TI99_VAQUERRO, bus::ti99::internal, vaquerro_device) DECLARE_DEVICE_TYPE_NS(TI99_MOFETTA, bus::ti99::internal, mofetta_device) diff --git a/src/mame/drivers/altair.cpp b/src/mame/drivers/altair.cpp index a1cb7132f21..7abf8bc7ca6 100644 --- a/src/mame/drivers/altair.cpp +++ b/src/mame/drivers/altair.cpp @@ -25,6 +25,7 @@ #include "emu.h" #include "bus/rs232/rs232.h" +//#include "bus/s100/s100.h" #include "cpu/i8085/i8085.h" #include "machine/6850acia.h" #include "machine/clock.h" diff --git a/src/mame/drivers/ccs2810.cpp b/src/mame/drivers/ccs2810.cpp index 0cd00a0b08a..c7120a266e8 100644 --- a/src/mame/drivers/ccs2810.cpp +++ b/src/mame/drivers/ccs2810.cpp @@ -65,6 +65,7 @@ ToDo: #include "emu.h" #include "cpu/z80/z80.h" #include "bus/rs232/rs232.h" +//#include "bus/s100/s100.h" #include "machine/ins8250.h" #include "machine/ram.h" #include "machine/wd_fdc.h" diff --git a/src/mame/drivers/cd2650.cpp b/src/mame/drivers/cd2650.cpp index 88a3dba1c9c..81ccfd40c71 100644 --- a/src/mame/drivers/cd2650.cpp +++ b/src/mame/drivers/cd2650.cpp @@ -30,6 +30,7 @@ TODO #include "emu.h" #include "cpu/s2650/s2650.h" +//#include "bus/s100/s100.h" #include "imagedev/cassette.h" #include "imagedev/snapquik.h" #include "machine/keyboard.h" diff --git a/src/mame/drivers/cv1k.cpp b/src/mame/drivers/cv1k.cpp index 870787cbdb7..eca9c1259ea 100644 --- a/src/mame/drivers/cv1k.cpp +++ b/src/mame/drivers/cv1k.cpp @@ -832,6 +832,18 @@ ROM_START( dfkbl ) ROM_LOAD16_WORD_SWAP( "u24", 0x400000, 0x400000, CRC(31f9eb0a) SHA1(322158779e969bb321241065dd49c1167b91ff6c) ) ROM_END +ROM_START( akatana ) + ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF) + ROM_LOAD16_WORD_SWAP( "u4", 0x000000, 0x400000, CRC(613fd380) SHA1(6e28480eef3b483d00b42d811a9d2c7fa1097924) ) // (2010/ 8/13 MASTER VER.) + + ROM_REGION( 0x8400000, "game", ROMREGION_ERASEFF) + ROM_LOAD( "u2", 0x000000, 0x8400000, CRC(89a2e1a5) SHA1(e6f4ec974406283665697fdd52bd606d0337dd11) ) + + ROM_REGION( 0x800000, "ymz770", ROMREGION_ERASEFF) + ROM_LOAD16_WORD_SWAP( "u23", 0x000000, 0x400000, CRC(34a67e24) SHA1(78a7e82123b86311f1116a80c39f147b8b695549) ) + ROM_LOAD16_WORD_SWAP( "u24", 0x400000, 0x400000, CRC(10760fed) SHA1(b70f4506c00f3901ff38f5efd4b897af1afc7a0c) ) +ROM_END + READ64_MEMBER(cv1k_state::speedup_r) { offs_t pc = downcast<cpu_device *>(&space.device())->pc(); @@ -892,7 +904,6 @@ DRIVER_INIT_MEMBER(cv1k_state,deathsml) DRIVER_INIT_MEMBER(cv1k_state,dpddfk) { install_speedups(0x02310, 0xc1d1346, true); - } #define GAME_FLAGS (MACHINE_IMPERFECT_TIMING) @@ -949,5 +960,8 @@ GAME( 2008, ddpdfk10, ddpdfk, cv1k_d, cv1k, cv1k_state, dpddfk, ROT270, " // CA019B Do-Don-Pachi Dai-Fukkatsu Black Label GAME( 2010, dfkbl, 0, cv1k_d, cv1k, cv1k_state, dpddfk, ROT270, "Cave (AMI license)", "DoDonPachi Dai-Fukkatsu Black Label (2010/1/18 BLACK LABEL)", GAME_FLAGS ) +// CA021 Akai Katana +GAME( 2010, akatana, 0, cv1k_d, cv1k, cv1k_state, dpddfk, ROT0, "Cave (AMI license)", "Akai Katana (2010/ 8/13 MASTER VER.)", GAME_FLAGS ) + // CMDL01 Medal Mahjong Moukari Bancho GAME( 2007, mmmbanc, 0, cv1k, cv1k, cv1k_state, pinkswts, ROT0, "Cave (AMI license)", "Medal Mahjong Moukari Bancho (2007/06/05 MASTER VER.)", MACHINE_NOT_WORKING ) diff --git a/src/mame/drivers/dual68.cpp b/src/mame/drivers/dual68.cpp index 214d58dd4e9..e6c410b8ad5 100644 --- a/src/mame/drivers/dual68.cpp +++ b/src/mame/drivers/dual68.cpp @@ -11,6 +11,7 @@ #include "emu.h" #include "cpu/m68000/m68000.h" #include "cpu/i8085/i8085.h" +//#include "bus/s100/s100.h" #include "machine/terminal.h" diff --git a/src/mame/drivers/imsai.cpp b/src/mame/drivers/imsai.cpp index dc87d6ae0c1..d3f21760f0f 100644 --- a/src/mame/drivers/imsai.cpp +++ b/src/mame/drivers/imsai.cpp @@ -18,6 +18,7 @@ #include "emu.h" #include "cpu/i8085/i8085.h" +//#include "bus/s100/s100.h" #include "machine/i8251.h" #include "machine/pit8253.h" #include "machine/terminal.h" diff --git a/src/mame/drivers/jade.cpp b/src/mame/drivers/jade.cpp index e9c1343a828..32a09838b76 100644 --- a/src/mame/drivers/jade.cpp +++ b/src/mame/drivers/jade.cpp @@ -22,6 +22,7 @@ #include "machine/z80ctc.h" #include "machine/z80sio.h" #include "bus/rs232/rs232.h" +//#include "bus/s100/s100.h" class jade_state : public driver_device diff --git a/src/mame/drivers/marinedt.cpp b/src/mame/drivers/marinedt.cpp index b4b1518757c..09bf33f18e8 100644 --- a/src/mame/drivers/marinedt.cpp +++ b/src/mame/drivers/marinedt.cpp @@ -1,18 +1,26 @@ // license:BSD-3-Clause -// copyright-holders:David Haywood +// copyright-holders:Angelo Salese +/*************************************************************************** -// **** SKELETON DRIVER **** original removed due to unresolved licensing. + Marine Date (c) 1981 Taito -/* + similar to crbaloon.cpp + + TODO: + - sprites + - sound + - inputs + - colors + - collision detection + - Merge devices from crbaloon driver. + +============================================================================ Marine Date Taito 1981 - PCB Layout ---------- - Top board - MGO70001 MGN00001 |---------------------------------------------| @@ -39,10 +47,7 @@ Notes: (PCB contains lots of resistors/caps/transistors etc) 4030 - RCA CD4030 Quad Exclusive-Or Gate VR* - Volume pots for each sound VOL - Master Volume pot - - Middle board - MGO70002 MGN00002 |---------------------------------------------| @@ -63,10 +68,7 @@ Notes: MG12/13 - Hitachi HN462532 4kx8 EPROM MG14/15/16 - 82S123 bipolar PROM PC3259 - PC3259 8025 H08 unknown DIP24 IC. Package design indicates it was manufactured by Fujitsu - - Lower board - AA017779 sticker: MGN00003 sticker: CLN00002 @@ -91,32 +93,303 @@ Notes: Wire jumpers for ROM configuration - J1 open J2 1-2, 3-9, 4-8, 5-7 J4 1-2, 4-5, 7-8, 10-11 - Top and Middle PCBs are plugged in with the solder-sides together. Lower PCB is plugged in with components facing up. -------------------------------------------------------------------------- -*/ + +***************************************************************************/ + #include "emu.h" +#include "cpu/z80/z80.h" +#include "screen.h" +#include "speaker.h" + +#define MAIN_CLOCK XTAL_9_987MHz class marinedt_state : public driver_device { public: marinedt_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag) - { } + , m_maincpu(*this, "maincpu") + , m_vram(*this, "vram") + , m_gfxdecode(*this, "gfxdecode") + { + } + + // screen updates + uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); + DECLARE_PALETTE_INIT(marinedt); + DECLARE_WRITE8_MEMBER(vram_w); + TILE_GET_INFO_MEMBER(get_tile_info); + +protected: + // driver_device overrides + virtual void machine_start() override; + virtual void machine_reset() override; + + virtual void video_start() override; + +private: + // devices + required_device<cpu_device> m_maincpu; + required_shared_ptr<uint8_t> m_vram; + required_device<gfxdecode_device> m_gfxdecode; + + tilemap_t *m_tilemap; }; +TILE_GET_INFO_MEMBER(marinedt_state::get_tile_info) +{ + int code = m_vram[tile_index]; + + SET_TILE_INFO_MEMBER(0, code, 0, 0); +} + +void marinedt_state::video_start() +{ + m_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(FUNC(marinedt_state::get_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 32, 32); + m_tilemap->set_transparent_pen(0); +} + +uint32_t marinedt_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect ) +{ + bitmap.fill(64, cliprect); + + for (int y = cliprect.min_y; y <= cliprect.max_y; y++) + for (int x = 32; x <= cliprect.max_x; x++) + { + // TODO: exact formula (related to total h size?) + uint8_t blue_pen = 0x48 + ((x-32) / 8); + // clamp + if(blue_pen > 0x5f) + blue_pen = 0x5f; + + bitmap.pix16(y, x) = blue_pen; + } + + m_tilemap->draw(screen, bitmap, cliprect, 0, 0); + return 0; +} + +WRITE8_MEMBER(marinedt_state::vram_w) +{ + m_vram[offset] = data; + m_tilemap->mark_tile_dirty(offset); +} + +static ADDRESS_MAP_START( marinedt_map, AS_PROGRAM, 8, marinedt_state ) + ADDRESS_MAP_GLOBAL_MASK(0x7fff) /* A15 is not decoded */ + AM_RANGE(0x0000, 0x3fff) AM_ROM AM_REGION("ipl",0) + AM_RANGE(0x4000, 0x43ff) AM_MIRROR(0x0400) AM_RAM + AM_RANGE(0x4800, 0x4bff) AM_MIRROR(0x0400) AM_RAM_WRITE(vram_w) AM_SHARE("vram") + +ADDRESS_MAP_END + +static ADDRESS_MAP_START( marinedt_io, AS_IO, 8, marinedt_state ) + ADDRESS_MAP_GLOBAL_MASK(0x0f) + AM_RANGE(0x00, 0x00) AM_READ_PORT("DSW1") + AM_RANGE(0x03, 0x03) AM_READ_PORT("SYSTEM") + AM_RANGE(0x04, 0x04) AM_READ_PORT("DSW2") + AM_RANGE(0x0e, 0x0e) AM_WRITENOP // watchdog +ADDRESS_MAP_END static INPUT_PORTS_START( marinedt ) + /* dummy active high structure */ + PORT_START("SYSA") + PORT_DIPNAME( 0x01, 0x00, "SYSA" ) + PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x01, DEF_STR( On ) ) + PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x02, DEF_STR( On ) ) + PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x04, DEF_STR( On ) ) + PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x08, DEF_STR( On ) ) + PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x10, DEF_STR( On ) ) + PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x20, DEF_STR( On ) ) + PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x40, DEF_STR( On ) ) + PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x80, DEF_STR( On ) ) + + PORT_START("SYSTEM") + PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 ) + PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 ) + PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_SERVICE1 ) + PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_TILT ) + PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) + PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2) + PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START2 ) + PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_START1 ) + + // TODO: diplocations needs to be verified + PORT_START("DSW1") + PORT_DIPNAME( 0x0f, 0x00, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SWA:4,3,2,1") + PORT_DIPSETTING( 0x0f, DEF_STR( 9C_1C ) ) + PORT_DIPSETTING( 0x0e, DEF_STR( 8C_1C ) ) + PORT_DIPSETTING( 0x0d, DEF_STR( 7C_1C ) ) + PORT_DIPSETTING( 0x0c, DEF_STR( 6C_1C ) ) + PORT_DIPSETTING( 0x0b, DEF_STR( 5C_1C ) ) + PORT_DIPSETTING( 0x0a, DEF_STR( 4C_1C ) ) + PORT_DIPSETTING( 0x09, DEF_STR( 3C_1C ) ) + PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) ) + PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) + PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) ) + PORT_DIPSETTING( 0x02, DEF_STR( 1C_3C ) ) + PORT_DIPSETTING( 0x03, DEF_STR( 1C_4C ) ) + PORT_DIPSETTING( 0x04, DEF_STR( 1C_5C ) ) + PORT_DIPSETTING( 0x05, DEF_STR( 1C_6C ) ) + PORT_DIPSETTING( 0x06, DEF_STR( 1C_7C ) ) + PORT_DIPSETTING( 0x07, DEF_STR( 1C_8C ) ) + PORT_DIPNAME( 0xf0, 0x00, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SWA:8,7,6,5") + PORT_DIPSETTING( 0xf0, DEF_STR( 9C_1C ) ) + PORT_DIPSETTING( 0xe0, DEF_STR( 8C_1C ) ) + PORT_DIPSETTING( 0xd0, DEF_STR( 7C_1C ) ) + PORT_DIPSETTING( 0xc0, DEF_STR( 6C_1C ) ) + PORT_DIPSETTING( 0xb0, DEF_STR( 5C_1C ) ) + PORT_DIPSETTING( 0xa0, DEF_STR( 4C_1C ) ) + PORT_DIPSETTING( 0x90, DEF_STR( 3C_1C ) ) + PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) ) + PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) + PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) ) + PORT_DIPSETTING( 0x20, DEF_STR( 1C_3C ) ) + PORT_DIPSETTING( 0x30, DEF_STR( 1C_4C ) ) + PORT_DIPSETTING( 0x40, DEF_STR( 1C_5C ) ) + PORT_DIPSETTING( 0x50, DEF_STR( 1C_6C ) ) + PORT_DIPSETTING( 0x60, DEF_STR( 1C_7C ) ) + PORT_DIPSETTING( 0x70, DEF_STR( 1C_8C ) ) + + PORT_START("DSW2") + PORT_DIPNAME( 0x01, 0x00, "DSWB" ) PORT_DIPLOCATION("SWB:1") + PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SWB:2") + PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_SERVICE_DIPLOC( 0x04, IP_ACTIVE_HIGH, "SWB:3") + PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SWB:4") + PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SWB:5") + PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SWB:6") + PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SWB:7") + PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SWB:8") + PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) INPUT_PORTS_END +static const gfx_layout charlayout = +{ + 8,8, + RGN_FRAC(1,3), + 3, + { RGN_FRAC(0,3), RGN_FRAC(1,3), RGN_FRAC(2,3) }, + { STEP8(7,-1) }, + { STEP8(0,8) }, + 8*8 +}; + +static GFXDECODE_START( marinedt ) + GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 1 ) +GFXDECODE_END + + +void marinedt_state::machine_start() +{ +} + +void marinedt_state::machine_reset() +{ +} + + +PALETTE_INIT_MEMBER(marinedt_state, marinedt) +{ + const uint8_t *color_prom = memregion("proms")->base(); + int i; + int bit0, bit1, bit2; + int r, g, b; + + for (i = 0; i < 64; i++) + { + /* red component */ + bit0 = (color_prom[i] >> 0) & 0x01; + bit1 = (color_prom[i] >> 1) & 0x01; + bit2 = (color_prom[i] >> 2) & 0x01; + r = (0x21 * bit0 + 0x47 * bit1 + 0x97 * bit2); + + /* green component */ + bit0 = (color_prom[i] >> 3) & 0x01; + bit1 = (color_prom[i] >> 4) & 0x01; + bit2 = (color_prom[i] >> 5) & 0x01; + g = (0x21 * bit0 + 0x47 * bit1 + 0x97 * bit2); + + /* blue component */ + bit0 = (color_prom[i] >> 6) & 0x01; + bit1 = (color_prom[i] >> 7) & 0x01; + // TODO: blue arrangement wrong according to screenshot, gameplay border should be red instead of blue + b = (0x47 * bit0 + 0x97 * bit1); + + palette.set_pen_color(i, rgb_t(r, g, b)); + } + + for (i = 0; i < 32; i++) + { + b = color_prom[i+0x60]; + palette.set_pen_color(64+31-i, rgb_t(0, 0, b)); + } +} static MACHINE_CONFIG_START( marinedt ) + + /* basic machine hardware */ + MCFG_CPU_ADD("maincpu",Z80,MAIN_CLOCK/4) + MCFG_CPU_PROGRAM_MAP(marinedt_map) + MCFG_CPU_IO_MAP(marinedt_io) + MCFG_CPU_VBLANK_INT_DRIVER("screen", marinedt_state, irq0_line_hold) + + /* video hardware */ + MCFG_SCREEN_ADD("screen", RASTER) + MCFG_SCREEN_UPDATE_DRIVER(marinedt_state, screen_update) + MCFG_SCREEN_RAW_PARAMS(MAIN_CLOCK/2, 328, 0, 256, 263, 32, 256) // template to get ~60 fps + MCFG_SCREEN_PALETTE("palette") + + MCFG_GFXDECODE_ADD("gfxdecode", "palette", marinedt) + + MCFG_PALETTE_ADD("palette", 64+32) + MCFG_PALETTE_INIT_OWNER(marinedt_state, marinedt) + + /* sound hardware */ + MCFG_SPEAKER_STANDARD_MONO("mono") +// MCFG_SOUND_ADD("aysnd", AY8910, MAIN_CLOCK/4) +// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30) MACHINE_CONFIG_END + +/*************************************************************************** + + Machine driver(s) + +***************************************************************************/ + ROM_START( marinedt ) - ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_REGION( 0x4000, "ipl", ROMREGION_ERASEFF ) ROM_LOAD( "mg01.3d", 0x0000, 0x0800, CRC(ad09f04d) SHA1(932fc973b4a2fbbebd7e6437ed30c8444e3d4afb)) ROM_LOAD( "mg02.4d", 0x0800, 0x0800, CRC(555a2b0f) SHA1(143a8953ce5070c31dc4c1f623833b2a5a2cf657)) ROM_LOAD( "mg03.5d", 0x1000, 0x0800, CRC(2abc79b3) SHA1(1afb331a2c0e320b6d026bc5cb47a53ac3356c2a)) @@ -126,9 +399,9 @@ ROM_START( marinedt ) ROM_LOAD( "mg07.10d", 0x3000, 0x0800, CRC(b85d1f9a) SHA1(4fd3e76b1816912df84477dba4655d395f5e7072) ) ROM_REGION( 0x1800, "gfx1", 0 ) - ROM_LOAD( "mg09.4f", 0x0000, 0x0800, CRC(f4c349ca) SHA1(077f65eeac616a778d6c42bb95677fa2892ab697) ) + ROM_LOAD( "mg11.1f", 0x0000, 0x0800, CRC(50d66dd7) SHA1(858d1d2a75e091b0e382d964c5e4ddcd8e6f07dd)) ROM_LOAD( "mg10.3f", 0x0800, 0x0800, CRC(b41251e3) SHA1(e125a971b401c78efeb4b03d0fab43e392d3fc14) ) - ROM_LOAD( "mg11.1f", 0x1000, 0x0800, CRC(50d66dd7) SHA1(858d1d2a75e091b0e382d964c5e4ddcd8e6f07dd)) + ROM_LOAD( "mg09.4f", 0x1000, 0x0800, CRC(f4c349ca) SHA1(077f65eeac616a778d6c42bb95677fa2892ab697) ) ROM_REGION( 0x1000, "gfx2", 0 ) ROM_LOAD( "mg12.6c", 0x0000, 0x1000, CRC(7c6486d5) SHA1(a7f17a803937937f05fc90621883a0fd44b297a0) ) @@ -136,11 +409,11 @@ ROM_START( marinedt ) ROM_REGION( 0x1000, "gfx3", 0 ) ROM_LOAD( "mg13.6h", 0x0000, 0x1000, CRC(17817044) SHA1(8c9b96620e3c414952e6d85c6e81b0df85c88e7a) ) - ROM_REGION( 0x0080, "proms", 0 ) + ROM_REGION( 0x0080, "proms", ROMREGION_INVERT ) ROM_LOAD( "mg14.2a", 0x0000, 0x0020, CRC(f75f4e3a) SHA1(36e665987f475c57435fa8c224a2a3ce0c5e672b) ) ROM_LOAD( "mg15.1a", 0x0020, 0x0020, CRC(cd3ab489) SHA1(a77478fb94d0cf8f4317f89cc9579def7c294b4f) ) ROM_LOAD( "mg16.4e", 0x0040, 0x0020, CRC(92c868bc) SHA1(483ae6f47845ddacb701528e82bd388d7d66a0fb) ) ROM_LOAD( "mg17.bpr", 0x0060, 0x0020, CRC(13261a02) SHA1(050edd18e4f79d19d5206f55f329340432fd4099) ) ROM_END -GAME( 1981, marinedt, 0, marinedt, marinedt, marinedt_state, 0, ROT270, "Taito", "Marine Date", MACHINE_IS_SKELETON ) +GAME( 1981, marinedt, 0, marinedt, marinedt, marinedt_state, 0, ROT270, "Taito", "Marine Date", MACHINE_IS_SKELETON ) diff --git a/src/mame/drivers/ptcsol.cpp b/src/mame/drivers/ptcsol.cpp index 3e7fa3ed6e1..c17cd0490ed 100644 --- a/src/mame/drivers/ptcsol.cpp +++ b/src/mame/drivers/ptcsol.cpp @@ -113,6 +113,7 @@ #include "emu.h" #include "cpu/i8085/i8085.h" +//#include "bus/s100/s100.h" #include "imagedev/cassette.h" #include "machine/ay31015.h" #include "machine/keyboard.h" diff --git a/src/mame/drivers/seattlecmp.cpp b/src/mame/drivers/seattlecmp.cpp index 3ce4e6f88b6..11d18f13721 100644 --- a/src/mame/drivers/seattlecmp.cpp +++ b/src/mame/drivers/seattlecmp.cpp @@ -35,6 +35,7 @@ There is a 4MHz crystal connected to the 9513. #include "machine/i8251.h" #include "machine/pic8259.h" #include "bus/rs232/rs232.h" +//#include "bus/s100/s100.h" class seattle_comp_state : public driver_device diff --git a/src/mame/drivers/super6.cpp b/src/mame/drivers/super6.cpp index 17f069478d3..af0c70056b0 100644 --- a/src/mame/drivers/super6.cpp +++ b/src/mame/drivers/super6.cpp @@ -13,6 +13,7 @@ #include "emu.h" #include "bus/rs232/rs232.h" +//#include "bus/s100/s100.h" #include "includes/super6.h" #include "softlist.h" diff --git a/src/mame/drivers/superslave.cpp b/src/mame/drivers/superslave.cpp index 0afcdd76c42..6c45a221ede 100644 --- a/src/mame/drivers/superslave.cpp +++ b/src/mame/drivers/superslave.cpp @@ -22,6 +22,7 @@ Oxx,yy = Out port #include "emu.h" #include "bus/rs232/rs232.h" +//#include "bus/s100/s100.h" #include "cpu/z80/z80.h" #include "cpu/z80/z80daisy.h" #include "machine/com8116.h" diff --git a/src/mame/drivers/techno.cpp b/src/mame/drivers/techno.cpp index 171b60eece9..eba5c5ef94b 100644 --- a/src/mame/drivers/techno.cpp +++ b/src/mame/drivers/techno.cpp @@ -29,6 +29,12 @@ public: , m_switch(*this, "SWITCH.%u", 0) { } + enum + { + IRQ_SET_TIMER, + IRQ_ADVANCE_TIMER + }; + DECLARE_READ16_MEMBER(key_r); DECLARE_READ16_MEMBER(rtrg_r); DECLARE_READ16_MEMBER(sound_r); @@ -40,17 +46,22 @@ public: DECLARE_WRITE16_MEMBER(sol1_w); DECLARE_WRITE16_MEMBER(sol2_w); DECLARE_WRITE16_MEMBER(sound_w); - INTERRUPT_GEN_MEMBER(techno_intgen); - IRQ_CALLBACK_MEMBER(intack); private: + virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; + virtual void machine_start() override; + virtual void machine_reset() override; + + required_device<cpu_device> m_maincpu; + required_ioport_array<8> m_switch; + + emu_timer *m_irq_set_timer; + emu_timer *m_irq_advance_timer; + bool m_digwait; uint8_t m_keyrow; uint16_t m_digit; uint8_t m_vector; - virtual void machine_reset() override; - required_device<cpu_device> m_maincpu; - required_ioport_array<8> m_switch; }; @@ -230,26 +241,38 @@ static INPUT_PORTS_START( techno ) PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Fix top left target middle") PORT_CODE(KEYCODE_EQUALS) INPUT_PORTS_END -INTERRUPT_GEN_MEMBER(techno_state::techno_intgen) +void techno_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) { - // vectors change per int: 88-8F, 98-9F) - if ((m_vector & 7) == 7) - m_vector = (m_vector ^ 0x10) & 0x97; - m_vector++; - m_maincpu->set_input_line(M68K_IRQ_1, ASSERT_LINE); + if (id == IRQ_ADVANCE_TIMER) + { + // vectors change per int: 88-8F, 98-9F) + if ((m_vector & 7) == 7) + m_vector = (m_vector ^ 0x10) & 0x97; + m_vector++; + + // schematics show a 74HC74 cleared only upon IRQ acknowledgment or reset, but this is clearly incorrect for xforce + m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE); + } + else if (id == IRQ_SET_TIMER) + { + m_maincpu->set_input_line_and_vector(M68K_IRQ_1, ASSERT_LINE, m_vector); + m_irq_advance_timer->adjust(attotime::from_hz(XTAL_8MHz / 32)); + } } -IRQ_CALLBACK_MEMBER(techno_state::intack) +void techno_state::machine_start() { - // IRQ is cleared via hardware - m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE); - return m_vector; + m_irq_set_timer = timer_alloc(IRQ_SET_TIMER); + m_irq_advance_timer = timer_alloc(IRQ_ADVANCE_TIMER); } void techno_state::machine_reset() { m_vector = 0x88; m_digit = 0; + + attotime freq = attotime::from_hz(XTAL_8MHz / 256); // 31250Hz + m_irq_set_timer->adjust(freq, 0, freq); m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE); } @@ -257,9 +280,6 @@ static MACHINE_CONFIG_START( techno ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", M68000, XTAL_8MHz) MCFG_CPU_PROGRAM_MAP(techno_map) - MCFG_CPU_PERIODIC_INT_DRIVER(techno_state, techno_intgen, XTAL_8MHz/256) // 31250Hz - MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(techno_state, intack) - MCFG_NVRAM_ADD_0FILL("nvram") //MCFG_CPU_ADD("cpu2", TMS7000, XTAL_4MHz) diff --git a/src/mame/drivers/z100.cpp b/src/mame/drivers/z100.cpp index f873c6d7ef3..5042eeaa6e6 100644 --- a/src/mame/drivers/z100.cpp +++ b/src/mame/drivers/z100.cpp @@ -145,6 +145,7 @@ ZDIPSW EQU 0FFH ; Configuration dip switches #include "emu.h" #include "cpu/i86/i86.h" +//#include "bus/s100/s100.h" #include "imagedev/flopdrv.h" #include "machine/6821pia.h" #include "machine/pic8259.h" diff --git a/src/mame/mame.lst b/src/mame/mame.lst index ae9f1b0fac9..fb647075650 100644 --- a/src/mame/mame.lst +++ b/src/mame/mame.lst @@ -10621,6 +10621,7 @@ tsarevna // tsarevnaa // @source:cv1k.cpp +akatana // (c) 2010 Cave (AMI license) - 2010/ 8/13 MASTER VER. ddpdfk // (c) 2008 Cave (AMI license) - 2008/06/23 MASTER VER 1.5 ddpdfk10 // (c) 2008 Cave (AMI license) - 2008/05/16 MASTER VER deathsml // (c) 2007 Cave (AMI license) - 2007/10/09 MASTER VER |